1 | /* Copyright (c) 2002,2005 Marek Michalkiewicz |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* avr/iotn12.h - definitions for ATtiny12 */ |
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34 | |
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35 | #ifndef _AVR_IOTN12_H_ |
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36 | #define _AVR_IOTN12_H_ 1 |
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37 | |
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38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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39 | |
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40 | #ifndef _AVR_IO_H_ |
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41 | # error "Include <avr/io.h> instead of this file." |
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42 | #endif |
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43 | |
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44 | #ifndef _AVR_IOXXX_H_ |
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45 | # define _AVR_IOXXX_H_ "iotn12.h" |
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46 | #else |
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47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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48 | #endif |
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49 | |
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50 | #ifndef __ASSEMBLER__ |
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51 | # warning "MCU not supported by the C compiler" |
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52 | #endif |
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53 | |
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54 | /* I/O registers */ |
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55 | |
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56 | /* 0x00..0x07 reserved */ |
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57 | |
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58 | /* Analog Comparator Control and Status Register */ |
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59 | #define ACSR _SFR_IO8(0x08) |
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60 | |
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61 | /* 0x09..0x15 reserved */ |
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62 | |
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63 | /* Input Pins, Port B */ |
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64 | #define PINB _SFR_IO8(0x16) |
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65 | |
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66 | /* Data Direction Register, Port B */ |
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67 | #define DDRB _SFR_IO8(0x17) |
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68 | |
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69 | /* Data Register, Port B */ |
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70 | #define PORTB _SFR_IO8(0x18) |
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71 | |
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72 | /* 0x19..0x1B reserved */ |
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73 | |
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74 | /* EEPROM Control Register */ |
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75 | #define EECR _SFR_IO8(0x1C) |
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76 | |
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77 | /* EEPROM Data Register */ |
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78 | #define EEDR _SFR_IO8(0x1D) |
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79 | |
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80 | /* EEPROM Address Register */ |
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81 | #define EEAR _SFR_IO8(0x1E) |
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82 | #define EEARL _SFR_IO8(0x1E) |
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83 | |
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84 | /* 0x1F..0x20 reserved */ |
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85 | |
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86 | /* Watchdog Timer Control Register */ |
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87 | #define WDTCR _SFR_IO8(0x21) |
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88 | |
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89 | /* 0x22..0x30 reserved */ |
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90 | |
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91 | /* Oscillator Calibration Register */ |
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92 | #define OSCCAL _SFR_IO8(0x31) |
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93 | |
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94 | /* Timer/Counter0 (8-bit) */ |
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95 | #define TCNT0 _SFR_IO8(0x32) |
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96 | |
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97 | /* Timer/Counter0 Control Register */ |
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98 | #define TCCR0 _SFR_IO8(0x33) |
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99 | |
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100 | /* MCU general Status Register */ |
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101 | #define MCUSR _SFR_IO8(0x34) |
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102 | |
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103 | /* MCU general Control Register */ |
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104 | #define MCUCR _SFR_IO8(0x35) |
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105 | |
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106 | /* 0x36..0x37 reserved */ |
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107 | |
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108 | /* Timer/Counter Interrupt Flag Register */ |
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109 | #define TIFR _SFR_IO8(0x38) |
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110 | |
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111 | /* Timer/Counter Interrupt MaSK Register */ |
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112 | #define TIMSK _SFR_IO8(0x39) |
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113 | |
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114 | /* General Interrupt Flag Register */ |
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115 | #define GIFR _SFR_IO8(0x3A) |
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116 | |
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117 | /* General Interrupt MaSK register */ |
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118 | #define GIMSK _SFR_IO8(0x3B) |
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119 | |
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120 | /* 0x3C..0x3E reserved */ |
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121 | |
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122 | /* 0x3F SREG */ |
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123 | |
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124 | /* Interrupt vectors */ |
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125 | |
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126 | /* External Interrupt 0 */ |
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127 | #define INT0_vect _VECTOR(1) |
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128 | #define SIG_INTERRUPT0 _VECTOR(1) |
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129 | |
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130 | /* External Interrupt Request 0 */ |
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131 | #define IO_PINS_vect _VECTOR(2) |
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132 | #define SIG_PIN _VECTOR(2) |
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133 | #define SIG_PIN_CHANGE _VECTOR(2) |
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134 | |
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135 | /* Timer/Counter0 Overflow */ |
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136 | #define TIMER0_OVF_vect _VECTOR(3) |
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137 | #define SIG_OVERFLOW0 _VECTOR(3) |
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138 | |
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139 | /* EEPROM Ready */ |
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140 | #define EE_RDY_vect _VECTOR(4) |
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141 | #define SIG_EEPROM_READY _VECTOR(4) |
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142 | |
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143 | /* Analog Comparator */ |
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144 | #define ANA_COMP_vect _VECTOR(5) |
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145 | #define SIG_COMPARATOR _VECTOR(5) |
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146 | |
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147 | #define _VECTORS_SIZE 12 |
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148 | |
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149 | /* Bit numbers */ |
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150 | |
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151 | /* GIMSK */ |
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152 | #define INT0 6 |
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153 | #define PCIE 5 |
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154 | |
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155 | /* GIFR */ |
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156 | #define INTF0 6 |
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157 | #define PCIF 5 |
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158 | |
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159 | /* TIMSK */ |
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160 | #define TOIE0 1 |
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161 | |
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162 | /* TIFR */ |
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163 | #define TOV0 1 |
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164 | |
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165 | /* MCUCR */ |
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166 | #define PUD 6 |
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167 | #define SE 5 |
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168 | #define SM 4 |
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169 | #define ISC01 1 |
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170 | #define ISC00 0 |
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171 | |
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172 | /* TCCR0 */ |
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173 | #define CS02 2 |
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174 | #define CS01 1 |
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175 | #define CS00 0 |
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176 | |
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177 | /* WDTCR */ |
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178 | #define WDTOE 4 |
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179 | #define WDE 3 |
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180 | #define WDP2 2 |
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181 | #define WDP1 1 |
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182 | #define WDP0 0 |
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183 | |
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184 | /* |
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185 | PB5 = RESET# |
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186 | PB4 = XTAL2 |
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187 | PB3 = XTAL1 |
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188 | PB2 = T0 / SCK |
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189 | PB1 = INT0 / AIN1 / MISO |
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190 | PB0 = AIN0 / MOSI |
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191 | */ |
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192 | |
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193 | /* PORTB */ |
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194 | #define PB4 4 |
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195 | #define PB3 3 |
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196 | #define PB2 2 |
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197 | #define PB1 1 |
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198 | #define PB0 0 |
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199 | |
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200 | /* DDRB */ |
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201 | #define DDB5 5 |
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202 | #define DDB4 4 |
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203 | #define DDB3 3 |
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204 | #define DDB2 2 |
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205 | #define DDB1 1 |
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206 | #define DDB0 0 |
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207 | |
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208 | /* PINB */ |
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209 | #define PINB5 5 |
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210 | #define PINB4 4 |
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211 | #define PINB3 3 |
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212 | #define PINB2 2 |
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213 | #define PINB1 1 |
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214 | #define PINB0 0 |
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215 | |
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216 | /* ACSR */ |
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217 | #define ACD 7 |
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218 | #define AINBG 6 |
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219 | #define ACO 5 |
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220 | #define ACI 4 |
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221 | #define ACIE 3 |
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222 | #define ACIS1 1 |
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223 | #define ACIS0 0 |
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224 | |
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225 | /* EEPROM Control Register */ |
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226 | #define EERIE 3 |
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227 | #define EEMWE 2 |
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228 | #define EEWE 1 |
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229 | #define EERE 0 |
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230 | |
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231 | /* Last memory addresses */ |
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232 | #define RAMEND 0x1F |
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233 | #define XRAMEND 0x0 |
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234 | #define E2END 0x3F |
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235 | #define E2PAGESIZE 2 |
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236 | #define FLASHEND 0x3FF |
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237 | |
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238 | |
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239 | /* Fuses */ |
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240 | |
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241 | #define FUSE_MEMORY_SIZE 1 |
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242 | |
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243 | /* Low Fuse Byte */ |
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244 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
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245 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
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246 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
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247 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
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248 | #define FUSE_RSTDISBL (unsigned char)~_BV(4) |
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249 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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250 | #define FUSE_BODEN (unsigned char)~_BV(6) |
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251 | #define FUSE_BODLEVEL (unsigned char)~_BV(7) |
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252 | #define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL) |
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253 | |
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254 | |
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255 | /* Lock Bits */ |
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256 | #define __LOCK_BITS_EXIST |
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257 | |
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258 | |
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259 | /* Signature */ |
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260 | #define SIGNATURE_0 0x1E |
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261 | #define SIGNATURE_1 0x90 |
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262 | #define SIGNATURE_2 0x05 |
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263 | |
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264 | |
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265 | #endif /* _AVR_IOTN12_H_ */ |
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