source: rtems/cpukit/score/cpu/avr/avr/iotn12.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 5.7 KB
Line 
1/* Copyright (c) 2002,2005 Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iotn12.h - definitions for ATtiny12 */
34
35#ifndef _AVR_IOTN12_H_
36#define _AVR_IOTN12_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iotn12.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50#ifndef __ASSEMBLER__
51#  warning "MCU not supported by the C compiler"
52#endif
53
54/* I/O registers */
55
56/* 0x00..0x07 reserved */
57
58/* Analog Comparator Control and Status Register */
59#define ACSR    _SFR_IO8(0x08)
60
61/* 0x09..0x15 reserved */
62
63/* Input Pins, Port B */
64#define PINB    _SFR_IO8(0x16)
65
66/* Data Direction Register, Port B */
67#define DDRB    _SFR_IO8(0x17)
68
69/* Data Register, Port B */
70#define PORTB   _SFR_IO8(0x18)
71
72/* 0x19..0x1B reserved */
73
74/* EEPROM Control Register */
75#define EECR    _SFR_IO8(0x1C)
76
77/* EEPROM Data Register */
78#define EEDR    _SFR_IO8(0x1D)
79
80/* EEPROM Address Register */
81#define EEAR    _SFR_IO8(0x1E)
82#define EEARL   _SFR_IO8(0x1E)
83
84/* 0x1F..0x20 reserved */
85
86/* Watchdog Timer Control Register */
87#define WDTCR   _SFR_IO8(0x21)
88
89/* 0x22..0x30 reserved */
90
91/* Oscillator Calibration Register */
92#define OSCCAL  _SFR_IO8(0x31)
93
94/* Timer/Counter0 (8-bit) */
95#define TCNT0   _SFR_IO8(0x32)
96
97/* Timer/Counter0 Control Register */
98#define TCCR0   _SFR_IO8(0x33)
99
100/* MCU general Status Register */
101#define MCUSR   _SFR_IO8(0x34)
102
103/* MCU general Control Register */
104#define MCUCR   _SFR_IO8(0x35)
105
106/* 0x36..0x37 reserved */
107
108/* Timer/Counter Interrupt Flag Register */
109#define TIFR    _SFR_IO8(0x38)
110
111/* Timer/Counter Interrupt MaSK Register */
112#define TIMSK   _SFR_IO8(0x39)
113
114/* General Interrupt Flag Register */
115#define GIFR    _SFR_IO8(0x3A)
116
117/* General Interrupt MaSK register */
118#define GIMSK   _SFR_IO8(0x3B)
119
120/* 0x3C..0x3E reserved */
121
122/* 0x3F SREG */
123
124/* Interrupt vectors */
125
126/* External Interrupt 0 */
127#define INT0_vect                       _VECTOR(1)
128#define SIG_INTERRUPT0                  _VECTOR(1)
129
130/* External Interrupt Request 0 */
131#define IO_PINS_vect                    _VECTOR(2)
132#define SIG_PIN                         _VECTOR(2)
133#define SIG_PIN_CHANGE                  _VECTOR(2)
134
135/* Timer/Counter0 Overflow */
136#define TIMER0_OVF_vect                 _VECTOR(3)
137#define SIG_OVERFLOW0                   _VECTOR(3)
138
139/* EEPROM Ready */
140#define EE_RDY_vect                     _VECTOR(4)
141#define SIG_EEPROM_READY                _VECTOR(4)
142
143/* Analog Comparator */
144#define ANA_COMP_vect                   _VECTOR(5)
145#define SIG_COMPARATOR                  _VECTOR(5)
146
147#define _VECTORS_SIZE 12
148
149/* Bit numbers */
150
151/* GIMSK */
152#define INT0    6
153#define PCIE    5
154
155/* GIFR */
156#define INTF0   6
157#define PCIF    5
158
159/* TIMSK */
160#define TOIE0   1
161
162/* TIFR */
163#define TOV0    1
164
165/* MCUCR */
166#define PUD     6
167#define SE      5
168#define SM      4
169#define ISC01   1
170#define ISC00   0
171
172/* TCCR0 */
173#define CS02    2
174#define CS01    1
175#define CS00    0
176
177/* WDTCR */
178#define WDTOE   4
179#define WDE     3
180#define WDP2    2
181#define WDP1    1
182#define WDP0    0
183
184/*
185   PB5 = RESET#
186   PB4 = XTAL2
187   PB3 = XTAL1
188   PB2 = T0 / SCK
189   PB1 = INT0 / AIN1 / MISO
190   PB0 = AIN0 / MOSI
191 */
192
193/* PORTB */
194#define PB4     4
195#define PB3     3
196#define PB2     2
197#define PB1     1
198#define PB0     0
199
200/* DDRB */
201#define DDB5    5
202#define DDB4    4
203#define DDB3    3
204#define DDB2    2
205#define DDB1    1
206#define DDB0    0
207
208/* PINB */
209#define PINB5   5
210#define PINB4   4
211#define PINB3   3
212#define PINB2   2
213#define PINB1   1
214#define PINB0   0
215
216/* ACSR */
217#define ACD     7
218#define AINBG   6
219#define ACO     5
220#define ACI     4
221#define ACIE    3
222#define ACIS1   1
223#define ACIS0   0
224
225/* EEPROM Control Register */
226#define EERIE   3
227#define EEMWE   2
228#define EEWE    1
229#define EERE    0
230
231/* Last memory addresses */
232#define RAMEND          0x1F
233#define XRAMEND         0x0
234#define E2END           0x3F
235#define E2PAGESIZE  2
236#define FLASHEND        0x3FF
237
238
239/* Fuses */
240
241#define FUSE_MEMORY_SIZE 1
242
243/* Low Fuse Byte */
244#define FUSE_CKSEL0      (unsigned char)~_BV(0)
245#define FUSE_CKSEL1      (unsigned char)~_BV(1)
246#define FUSE_CKSEL2      (unsigned char)~_BV(2)
247#define FUSE_CKSEL3      (unsigned char)~_BV(3)
248#define FUSE_RSTDISBL    (unsigned char)~_BV(4)
249#define FUSE_SPIEN       (unsigned char)~_BV(5)
250#define FUSE_BODEN       (unsigned char)~_BV(6)
251#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
252#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL)
253
254
255/* Lock Bits */
256#define __LOCK_BITS_EXIST
257
258
259/* Signature */
260#define SIGNATURE_0 0x1E
261#define SIGNATURE_1 0x90
262#define SIGNATURE_2 0x05
263
264
265#endif /* _AVR_IOTN12_H_ */
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