1 | /* Copyright (c) 2007, Anatoly Sokolov |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* iomxxhva.h - definitions for ATmega8HVA and ATmega16HVA. */ |
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34 | |
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35 | #ifndef _AVR_IOMXXHVA_H_ |
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36 | #define _AVR_IOMXXHVA_H_ 1 |
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37 | |
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38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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39 | |
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40 | #ifndef _AVR_IO_H_ |
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41 | # error "Include <avr/io.h> instead of this file." |
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42 | #endif |
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43 | |
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44 | #ifndef _AVR_IOXXX_H_ |
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45 | # define _AVR_IOXXX_H_ "iomxxhva.h" |
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46 | #else |
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47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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48 | #endif |
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49 | |
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50 | /* Registers and associated bit numbers */ |
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51 | |
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52 | #define PINA _SFR_IO8(0X00) |
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53 | #define PINA1 1 |
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54 | #define PINA0 0 |
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55 | |
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56 | #define DDRA _SFR_IO8(0x01) |
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57 | #define DDA1 1 |
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58 | #define DDA0 0 |
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59 | |
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60 | #define PORTA _SFR_IO8(0x02) |
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61 | #define PA1 1 |
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62 | #define PA0 0 |
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63 | |
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64 | #define PINB _SFR_IO8(0X03) |
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65 | #define PINB3 3 |
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66 | #define PINB2 2 |
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67 | #define PINB1 1 |
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68 | #define PINB0 0 |
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69 | |
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70 | #define DDRB _SFR_IO8(0x04) |
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71 | #define DDB3 3 |
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72 | #define DDB2 2 |
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73 | #define DDB1 1 |
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74 | #define DDB0 0 |
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75 | |
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76 | #define PORTB _SFR_IO8(0x05) |
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77 | #define PB3 3 |
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78 | #define PB2 2 |
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79 | #define PB1 1 |
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80 | #define PB0 0 |
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81 | |
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82 | #define PINC _SFR_IO8(0x06) |
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83 | #define PINC0 0 |
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84 | |
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85 | /* Reserved [0x7] */ |
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86 | |
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87 | #define PORTC _SFR_IO8(0x08) |
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88 | #define PC0 0 |
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89 | |
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90 | /* Reserved [0x9..0x14] */ |
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91 | |
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92 | #define TIFR0 _SFR_IO8(0x15) |
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93 | #define ICF0 3 |
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94 | #define OCF0B 2 |
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95 | #define OCF0A 1 |
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96 | #define TOV0 0 |
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97 | |
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98 | #define TIFR1 _SFR_IO8(0x16) |
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99 | #define ICF1 3 |
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100 | #define OCF1B 2 |
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101 | #define OCF1A 1 |
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102 | #define TOV1 0 |
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103 | |
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104 | #define OSICSR _SFR_IO8(0x17) |
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105 | #define OSISEL0 4 |
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106 | #define OSIST 1 |
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107 | #define OSIEN 0 |
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108 | |
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109 | /* Reserved [0x18..0x1B] */ |
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110 | |
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111 | #define EIFR _SFR_IO8(0x1C) |
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112 | #define INTF2 2 |
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113 | #define INTF1 1 |
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114 | #define INTF0 0 |
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115 | |
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116 | #define EIMSK _SFR_IO8(0x1D) |
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117 | #define INT2 2 |
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118 | #define INT1 1 |
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119 | #define INT0 0 |
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120 | |
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121 | #define GPIOR0 _SFR_IO8(0x1E) |
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122 | |
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123 | #define EECR _SFR_IO8(0x1F) |
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124 | #define EEPM1 5 |
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125 | #define EEPM0 4 |
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126 | #define EERIE 3 |
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127 | #define EEMPE 2 |
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128 | #define EEPE 1 |
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129 | #define EERE 0 |
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130 | |
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131 | #define EEDR _SFR_IO8(0x20) |
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132 | |
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133 | #define EEAR _SFR_IO8(0x21) |
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134 | #define EEARL _SFR_IO8(0x21) |
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135 | |
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136 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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137 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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138 | subroutines. |
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139 | First two letters: EECR address. |
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140 | Second two letters: EEDR address. |
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141 | Last two letters: EEAR address. */ |
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142 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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143 | |
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144 | /* Reserved [0x22] */ |
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145 | |
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146 | #define GTCCR _SFR_IO8(0x23) |
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147 | #define TSM 7 |
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148 | #define PSRSYNC 0 |
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149 | |
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150 | #define TCCR0A _SFR_IO8(0x24) |
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151 | #define TCW0 7 |
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152 | #define ICEN0 6 |
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153 | #define ICNC0 5 |
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154 | #define ICES0 4 |
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155 | #define ICS0 3 |
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156 | #define WGM00 0 |
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157 | |
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158 | #define TCCR0B _SFR_IO8(0x25) |
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159 | #define CS02 2 |
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160 | #define CS01 1 |
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161 | #define CS00 0 |
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162 | |
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163 | #define TCNT0 _SFR_IO16(0X26) |
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164 | #define TCNT0L _SFR_IO8(0X26) |
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165 | #define TCNT0H _SFR_IO8(0X27) |
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166 | |
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167 | #define OCR0A _SFR_IO8(0x28) |
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168 | |
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169 | #define OCR0B _SFR_IO8(0X29) |
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170 | |
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171 | #define GPIOR1 _SFR_IO8(0x2A) |
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172 | |
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173 | #define GPIOR2 _SFR_IO8(0x2B) |
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174 | |
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175 | #define SPCR _SFR_IO8(0x2C) |
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176 | #define SPIE 7 |
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177 | #define SPE 6 |
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178 | #define DORD 5 |
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179 | #define MSTR 4 |
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180 | #define CPOL 3 |
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181 | #define CPHA 2 |
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182 | #define SPR1 1 |
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183 | #define SPR0 0 |
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184 | |
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185 | #define SPSR _SFR_IO8(0x2D) |
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186 | #define SPIF 7 |
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187 | #define WCOL 6 |
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188 | #define SPI2X 0 |
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189 | |
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190 | #define SPDR _SFR_IO8(0x2E) |
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191 | |
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192 | /* Reserved [0x2F..0x30] */ |
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193 | |
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194 | #define DWDR _SFR_IO8(0x31) |
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195 | #define IDRD 7 |
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196 | |
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197 | /* Reserved [0x32] */ |
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198 | |
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199 | #define SMCR _SFR_IO8(0x33) |
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200 | #define SM2 3 |
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201 | #define SM1 2 |
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202 | #define SM0 1 |
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203 | #define SE 0 |
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204 | |
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205 | #define MCUSR _SFR_IO8(0x34) |
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206 | #define OCDRF 4 |
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207 | #define WDRF 3 |
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208 | #define BORF 2 |
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209 | #define EXTRF 1 |
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210 | #define PORF 0 |
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211 | |
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212 | #define MCUCR _SFR_IO8(0x35) |
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213 | #define CKOE 5 |
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214 | #define PUD 4 |
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215 | |
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216 | /* Reserved [0x36] */ |
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217 | |
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218 | #define SPMCSR _SFR_IO8(0x37) |
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219 | #define SIGRD 5 |
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220 | #define CTPB 4 |
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221 | #define RFLB 3 |
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222 | #define PGWRT 2 |
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223 | #define PGERS 1 |
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224 | #define SPMEN 0 |
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225 | |
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226 | /* Reserved [0x38..0x3C] */ |
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227 | |
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228 | /* SP [0x3D..0x3E] */ |
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229 | /* SREG [0x3F] */ |
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230 | |
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231 | #define WDTCSR _SFR_MEM8(0x60) |
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232 | #define WDIF 7 |
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233 | #define WDIE 6 |
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234 | #define WDP3 5 |
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235 | #define WDCE 4 |
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236 | #define WDE 3 |
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237 | #define WDP2 2 |
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238 | #define WDP1 1 |
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239 | #define WDP0 0 |
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240 | |
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241 | #define CLKPR _SFR_MEM8(0x61) |
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242 | #define CLKPCE 7 |
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243 | #define CLKPS1 1 |
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244 | #define CLKPS0 0 |
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245 | |
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246 | /* Reserved [0x62..0x63] */ |
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247 | |
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248 | #define PRR0 _SFR_MEM8(0x64) |
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249 | #define PRVRM 5 |
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250 | #define PRSPI 3 |
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251 | #define PRTIM1 2 |
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252 | #define PRTIM0 1 |
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253 | #define PRVADC 0 |
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254 | |
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255 | /* Reserved [0x65] */ |
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256 | |
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257 | #define FOSCCAL _SFR_MEM8(0x66) |
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258 | |
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259 | /* Reserved [0x67..0x68] */ |
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260 | |
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261 | #define EICRA _SFR_MEM8(0x69) |
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262 | #define ISC21 5 |
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263 | #define ISC20 4 |
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264 | #define ISC11 3 |
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265 | #define ISC10 2 |
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266 | #define ISC01 1 |
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267 | #define ISC00 0 |
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268 | |
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269 | /* Reserved [0x6A..0x6D] */ |
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270 | |
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271 | #define TIMSK0 _SFR_MEM8(0x6E) |
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272 | #define ICIE0 3 |
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273 | #define OCIE0B 2 |
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274 | #define OCIE0A 1 |
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275 | #define TOIE0 0 |
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276 | |
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277 | #define TIMSK1 _SFR_MEM8(0x6F) |
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278 | #define ICIE1 3 |
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279 | #define OCIE1B 2 |
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280 | #define OCIE1A 1 |
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281 | #define TOIE1 0 |
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282 | |
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283 | /* Reserved [0x70..0x77] */ |
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284 | |
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285 | #define VADC _SFR_MEM16(0x78) |
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286 | #define VADCL _SFR_MEM8(0x78) |
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287 | #define VADCH _SFR_MEM8(0x79) |
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288 | |
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289 | #define VADCSR _SFR_MEM8(0x7A) |
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290 | #define VADEN 3 |
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291 | #define VADSC 2 |
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292 | #define VADCCIF 1 |
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293 | #define VADCCIE 0 |
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294 | |
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295 | /* Reserved [0x7B] */ |
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296 | |
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297 | #define VADMUX _SFR_MEM8(0x7C) |
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298 | #define VADMUX3 3 |
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299 | #define VADMUX2 2 |
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300 | #define VADMUX1 1 |
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301 | #define VADMUX0 0 |
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302 | |
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303 | /* Reserved [0x7D] */ |
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304 | |
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305 | #define DIDR0 _SFR_MEM8(0x7E) |
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306 | #define PA1DID 1 |
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307 | #define PA0DID 0 |
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308 | |
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309 | /* Reserved [0x7F] */ |
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310 | |
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311 | #define TCCR1A _SFR_MEM8(0x80) |
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312 | #define TCW1 7 |
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313 | #define ICEN1 6 |
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314 | #define ICNC1 5 |
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315 | #define ICES1 4 |
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316 | #define ICS1 3 |
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317 | #define WGM10 0 |
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318 | |
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319 | #define TCCR1B _SFR_MEM8(0x81) |
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320 | #define CS12 2 |
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321 | #define CS11 1 |
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322 | #define CS10 0 |
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323 | |
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324 | /* Reserved [0x82..0x83] */ |
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325 | |
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326 | #define TCNT1 _SFR_MEM16(0x84) |
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327 | #define TCNT1L _SFR_MEM8(0x84) |
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328 | #define TCNT1H _SFR_MEM8(0x85) |
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329 | |
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330 | /* Reserved [0x86..0x87] */ |
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331 | |
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332 | #define OCR1A _SFR_MEM8(0x88) |
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333 | |
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334 | #define OCR1B _SFR_MEM8(0x89) |
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335 | |
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336 | /* Reserved [0x8A..0xC7] */ |
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337 | |
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338 | #define ROCR _SFR_MEM8(0xC8) |
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339 | #define ROCS 7 |
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340 | #define ROCWIF 1 |
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341 | #define ROCWIE 0 |
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342 | |
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343 | /* Reserved [0xC9..0xCF] */ |
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344 | |
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345 | #define BGCCR _SFR_MEM8(0xD0) |
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346 | #define BGD 7 |
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347 | #define BGCC5 5 |
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348 | #define BGCC4 4 |
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349 | #define BGCC3 3 |
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350 | #define BGCC2 2 |
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351 | #define BGCC1 1 |
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352 | #define BGCC0 0 |
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353 | |
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354 | #define BGCRR _SFR_MEM8(0xD1) |
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355 | #define BGCR7 7 |
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356 | #define BGCR6 6 |
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357 | #define BGCR5 5 |
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358 | #define BGCR4 4 |
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359 | #define BGCR3 3 |
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360 | #define BGCR2 2 |
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361 | #define BGCR1 1 |
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362 | #define BGCR0 0 |
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363 | |
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364 | /* Reserved [0xD2..0xDF] */ |
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365 | |
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366 | /* CC-ADC Accumulate Current */ |
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367 | /* TODO: Add _SFR_MEM32 */ |
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368 | /* #define CADAC _SFR_MEM32(0xE0) */ |
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369 | #define CADAC0 _SFR_MEM8(0xE0) |
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370 | #define CADAC1 _SFR_MEM8(0xE1) |
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371 | #define CADAC2 _SFR_MEM8(0xE2) |
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372 | #define CADAC3 _SFR_MEM8(0xE3) |
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373 | |
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374 | #define CADCSRA _SFR_MEM8(0xE4) |
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375 | #define CADEN 7 |
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376 | #define CADPOL 6 |
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377 | #define CADUB 5 |
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378 | #define CADAS1 4 |
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379 | #define CADAS0 3 |
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380 | #define CADSI1 2 |
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381 | #define CADSI0 1 |
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382 | #define CADSE 0 |
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383 | |
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384 | #define CADCSRB _SFR_MEM8(0xE5) |
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385 | #define CADACIE 6 |
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386 | #define CADRCIE 5 |
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387 | #define CADICIE 4 |
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388 | #define CADACIF 2 |
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389 | #define CADRCIF 1 |
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390 | #define CADICIF 0 |
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391 | |
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392 | #define CADRC _SFR_MEM8(0xE6) |
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393 | |
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394 | /* Reserved [0xE7] */ |
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395 | |
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396 | #define CADIC _SFR_MEM16(0xE8) |
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397 | #define CADICL _SFR_MEM8(0xE8) |
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398 | #define CADICH _SFR_MEM8(0xE9) |
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399 | |
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400 | /* Reserved [0xEA..0xEF] */ |
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401 | |
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402 | #define FCSR _SFR_MEM8(0xF0) |
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403 | #define DUVRD 3 |
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404 | #define CPS 2 |
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405 | #define DFE 1 |
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406 | #define CFE 0 |
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407 | |
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408 | /* Reserved [0xF1] */ |
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409 | |
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410 | #define BPIMSK _SFR_MEM8(0xF2) |
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411 | #define SCIE 4 |
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412 | #define DOCIE 3 |
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413 | #define COCIE 2 |
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414 | #define DHCIE 1 |
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415 | #define CHCIE 0 |
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416 | |
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417 | #define BPIFR _SFR_MEM8(0xF3) |
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418 | #define SCIF 4 |
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419 | #define DOCIF 3 |
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420 | #define COCIF 2 |
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421 | #define DHCIF 1 |
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422 | #define CHCIF 0 |
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423 | |
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424 | /* Reserved [0xF4] */ |
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425 | |
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426 | #define BPSCD _SFR_MEM8(0xF5) |
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427 | |
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428 | #define BPDOCD _SFR_MEM8(0xF6) |
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429 | |
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430 | #define BPCOCD _SFR_MEM8(0xF7) |
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431 | |
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432 | #define BPDHCD _SFR_MEM8(0xF8) |
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433 | |
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434 | #define BPCHCD _SFR_MEM8(0xF9) |
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435 | |
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436 | #define BPSCTR _SFR_MEM8(0xFA) |
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437 | |
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438 | #define BPOCTR _SFR_MEM8(0xFB) |
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439 | |
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440 | #define BPHCTR _SFR_MEM8(0xFC) |
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441 | |
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442 | #define BPCR _SFR_MEM8(0xFD) |
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443 | #define SCD 4 |
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444 | #define DOCD 3 |
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445 | #define COCD 2 |
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446 | #define DHCD 1 |
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447 | #define CHCD 0 |
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448 | |
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449 | #define BPPLR _SFR_MEM8(0xFE) |
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450 | #define BPPLE 1 |
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451 | #define BPPL 0 |
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452 | |
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453 | /* Reserved [0xFF] */ |
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454 | |
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455 | /* Interrupt vectors */ |
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456 | /* Battery Protection Interrupt */ |
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457 | #define BPINT_vect _VECTOR(1) |
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458 | |
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459 | /* Voltage Regulator Monitor Interrupt */ |
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460 | #define VREGMON_vect _VECTOR(2) |
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461 | |
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462 | /* External Interrupt Request 0 */ |
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463 | #define INT0_vect _VECTOR(3) |
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464 | |
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465 | /* External Interrupt Request 1 */ |
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466 | #define INT1_vect _VECTOR(4) |
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467 | |
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468 | /* External Interrupt Request 2 */ |
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469 | #define INT2_vect _VECTOR(5) |
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470 | |
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471 | /* Watchdog Timeout Interrupt */ |
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472 | #define WDT_vect _VECTOR(6) |
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473 | |
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474 | /* Timer/Counter 1 Input Capture */ |
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475 | #define TIMER1_IC_vect _VECTOR(7) |
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476 | |
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477 | /* Timer/Counter 1 Compare A Match */ |
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478 | #define TIMER1_COMPA_vect _VECTOR(8) |
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479 | |
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480 | /* Timer/Counter 1 Compare B Match */ |
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481 | #define TIMER1_COMPB_vect _VECTOR(9) |
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482 | |
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483 | /* Timer/Counter 1 Overflow */ |
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484 | #define TIMER1_OVF_vect _VECTOR(10) |
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485 | |
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486 | /* Timer/Counter 0 Input Capture */ |
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487 | #define TIMER0_IC_vect _VECTOR(11) |
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488 | |
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489 | /* Timer/Counter0 Compare A Match */ |
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490 | #define TIMER0_COMPA_vect _VECTOR(12) |
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491 | |
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492 | /* Timer/Counter0 Compare B Match */ |
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493 | #define TIMER0_COMPB_vect _VECTOR(13) |
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494 | |
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495 | /* Timer/Counter0 Overflow */ |
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496 | #define TIMER0_OVF_vect _VECTOR(14) |
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497 | |
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498 | /* SPI Serial Transfer Complete */ |
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499 | #define SPI_STC_vect _VECTOR(15) |
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500 | |
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501 | /* Voltage ADC Conversion Complete */ |
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502 | #define VADC_vect _VECTOR(16) |
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503 | |
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504 | /* Coulomb Counter ADC Conversion Complete */ |
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505 | #define CCADC_CONV_vect _VECTOR(17) |
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506 | |
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507 | /* Coloumb Counter ADC Regular Current */ |
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508 | #define CCADC_REG_CUR_vect _VECTOR(18) |
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509 | |
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510 | /* Coloumb Counter ADC Accumulator */ |
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511 | #define CCADC_ACC_vect _VECTOR(19) |
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512 | |
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513 | /* EEPROM Ready */ |
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514 | #define EE_READY_vect _VECTOR(20) |
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515 | |
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516 | #if defined (__AVR_ATmega16HVA__) |
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517 | # define _VECTORS_SIZE 84 |
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518 | #else |
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519 | # define _VECTORS_SIZE 42 |
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520 | #endif |
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521 | |
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522 | |
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523 | #endif /* _AVR_IOMXXHVA_H_ */ |
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