source: rtems/cpukit/score/cpu/avr/avr/iomxx4.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 16.5 KB
Line 
1/* Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* avr/iomXX4.h - definitions for ATmega164P/324P/644P and ATmega644 */
32
33/* $Id$ */
34
35#ifndef _AVR_IOMXX4_H_
36#define _AVR_IOMXX4_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom164.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Registers and associated bit numbers */
51
52#define PINA    _SFR_IO8(0X00)
53#define PINA7   7
54#define PINA6   6
55#define PINA5   5
56#define PINA4   4
57#define PINA3   3
58#define PINA2   2
59#define PINA1   1
60#define PINA0   0
61
62#define DDRA    _SFR_IO8(0X01)
63#define DDA7    7
64#define DDA6    6
65#define DDA5    5
66#define DDA4    4
67#define DDA3    3
68#define DDA2    2
69#define DDA1    1
70#define DDA0    0
71
72#define PORTA   _SFR_IO8(0X02)
73#define PA7     7
74#define PA6     6
75#define PA5     5
76#define PA4     4
77#define PA3     3
78#define PA2     2
79#define PA1     1
80#define PA0     0
81
82#define PINB    _SFR_IO8(0X03)
83#define PINB7   7
84#define PINB6   6
85#define PINB5   5
86#define PINB4   4
87#define PINB3   3
88#define PINB2   2
89#define PINB1   1
90#define PINB0   0
91
92#define DDRB    _SFR_IO8(0x04)
93#define DDB7    7
94#define DDB6    6
95#define DDB5    5
96#define DDB4    4
97#define DDB3    3
98#define DDB2    2
99#define DDB1    1
100#define DDB0    0
101
102#define PORTB   _SFR_IO8(0x05)
103#define PB7     7
104#define PB6     6
105#define PB5     5
106#define PB4     4
107#define PB3     3
108#define PB2     2
109#define PB1     1
110#define PB0     0
111
112#define PINC    _SFR_IO8(0x06)
113#define PINC7   7
114#define PINC6   6
115#define PINC5   5
116#define PINC4   4
117#define PINC3   3
118#define PINC2   2
119#define PINC1   1
120#define PINC0   0
121
122#define DDRC    _SFR_IO8(0x07)
123#define DDC7    7
124#define DDC6    6
125#define DDC5    5
126#define DDC4    4
127#define DDC3    3
128#define DDC2    2
129#define DDC1    1
130#define DDC0    0
131
132#define PORTC   _SFR_IO8(0x08)
133#define PC7     7
134#define PC6     6
135#define PC5     5
136#define PC4     4
137#define PC3     3
138#define PC2     2
139#define PC1     1
140#define PC0     0
141
142#define PIND    _SFR_IO8(0x09)
143#define PIND7   7
144#define PIND6   6
145#define PIND5   5
146#define PIND4   4
147#define PIND3   3
148#define PIND2   2
149#define PIND1   1
150#define PIND0   0
151
152#define DDRD    _SFR_IO8(0x0A)
153#define DDD7    7
154#define DDD6    6
155#define DDD5    5
156#define DDD4    4
157#define DDD3    3
158#define DDD2    2
159#define DDD1    1
160#define DDD0    0
161
162#define PORTD   _SFR_IO8(0x0B)
163#define PD7     7
164#define PD6     6
165#define PD5     5
166#define PD4     4
167#define PD3     3
168#define PD2     2
169#define PD1     1
170#define PD0     0
171
172/* Reserved [0x0C..0x14] */
173
174#define TIFR0   _SFR_IO8(0x15)
175#define OCF0B   2
176#define OCF0A   1
177#define TOV0    0
178
179#define TIFR1   _SFR_IO8(0x16)
180#define ICF1    5
181#define OCF1B   2
182#define OCF1A   1
183#define TOV1    0
184
185#define TIFR2   _SFR_IO8(0x17)
186#define OCF2B   2
187#define OCF2A   1
188#define TOV2    0
189
190/* Reserved [0x18..0x1A] */
191
192#define PCIFR   _SFR_IO8(0x1B)
193#define PCIF3   3
194#define PCIF2   2
195#define PCIF1   1
196#define PCIF0   0
197
198#define EIFR   _SFR_IO8(0x1C)
199#define INTF2   2
200#define INTF1   1
201#define INTF0   0
202
203#define EIMSK   _SFR_IO8(0x1D)
204#define INT2    2
205#define INT1    1
206#define INT0    0
207
208#define GPIOR0  _SFR_IO8(0x1E)
209
210#define EECR   _SFR_IO8(0x1F)
211/* EECR - EEPROM Control Register */
212#define EEPM1   5
213#define EEPM0   4
214#define EERIE   3
215#define EEMPE   2
216#define EEPE    1
217#define EERE    0
218
219#define EEDR   _SFR_IO8(0X20)
220
221/* Combine EEARL and EEARH */
222#define EEAR   _SFR_IO16(0x21)
223#define EEARL  _SFR_IO8(0x21)
224#define EEARH  _SFR_IO8(0X22)
225
226/* 6-char sequence denoting where to find the EEPROM registers in memory space.
227   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
228   subroutines.
229   First two letters:  EECR address.
230   Second two letters: EEDR address.
231   Last two letters:   EEAR address.  */
232#define __EEPROM_REG_LOCATIONS__ 1F2021
233
234#define GTCCR   _SFR_IO8(0x23)
235#define TSM     7
236#define PSRASY  1
237#define PSRSYNC 0
238
239#define TCCR0A  _SFR_IO8(0x24)
240#define COM0A1  7
241#define COM0A0  6
242#define COM0B1  5
243#define COM0B0  4
244#define WGM01   1
245#define WGM00   0
246
247#define TCCR0B  _SFR_IO8(0x25)
248#define FOC0A   7
249#define FOC0B   6
250#define WGM02   3
251#define CS02    2
252#define CS01    1
253#define CS00    0
254
255#define TCNT0   _SFR_IO8(0X26)
256
257#define OCR0A   _SFR_IO8(0X27)
258
259#define OCR0B   _SFR_IO8(0X28)
260
261/* Reserved [0x29] */
262
263#define GPIOR1  _SFR_IO8(0x2A)
264
265#define GPIOR2  _SFR_IO8(0x2B)
266
267#define SPCR    _SFR_IO8(0x2C)
268#define SPIE    7
269#define SPE     6
270#define DORD    5
271#define MSTR    4
272#define CPOL    3
273#define CPHA    2
274#define SPR1    1
275#define SPR0    0
276
277#define SPSR    _SFR_IO8(0x2D)
278#define SPIF    7
279#define WCOL    6
280#define SPI2X   0
281
282#define SPDR    _SFR_IO8(0x2E)
283
284/* Reserved [0x2F] */
285
286#define ACSR    _SFR_IO8(0x30)
287#define ACD     7
288#define ACBG    6
289#define ACO     5
290#define ACI     4
291#define ACIE    3
292#define ACIC    2
293#define ACIS1   1
294#define ACIS0   0
295
296#define MONDR   _SFR_IO8(0x31)
297#define OCDR    _SFR_IO8(0x31)
298#define IDRD    7
299#define OCDR7   7
300#define OCDR6   6
301#define OCDR5   5
302#define OCDR4   4
303#define OCDR3   3
304#define OCDR2   2
305#define OCDR1   1
306#define OCDR0   0
307
308/* Reserved [0x32] */
309
310#define SMCR    _SFR_IO8(0x33)
311#define SM2     3
312#define SM1     2
313#define SM0     1
314#define SE      0
315
316#define MCUSR   _SFR_IO8(0x34)
317#define JTRF    4
318#define WDRF    3
319#define BORF    2
320#define EXTRF   1
321#define PORF    0
322
323#define MCUCR   _SFR_IO8(0X35)
324#define JTD     7
325#if !defined(__AVR_ATmega644__)
326#define BODS    6
327#define BODSE   5
328#endif
329#define PUD     4
330#define IVSEL   1
331#define IVCE    0
332
333/* Reserved [0x36] */
334
335#define SPMCSR  _SFR_IO8(0x37)
336#define SPMIE   7
337#define RWWSB   6
338#define SIGRD   5
339#define RWWSRE  4
340#define BLBSET  3
341#define PGWRT   2
342#define PGERS   1
343#define SPMEN   0
344
345/* Reserved [0x38..0x3C] */
346
347/* SP [0x3D..0x3E] */
348/* SREG [0x3F] */
349
350#define WDTCSR  _SFR_MEM8(0x60)
351#define WDIF    7
352#define WDIE    6
353#define WDP3    5
354#define WDCE    4
355#define WDE     3
356#define WDP2    2
357#define WDP1    1
358#define WDP0    0
359
360#define CLKPR   _SFR_MEM8(0x61)
361#define CLKPCE  7
362#define CLKPS3  3
363#define CLKPS2  2
364#define CLKPS1  1
365#define CLKPS0  0
366
367/* Reserved [0x62..0x63] */
368
369#define PRR     _SFR_MEM8(0x64)  /* Datasheets: ATmega164P/324P/644P 8011D–AVR–02/07
370                                   and ATmega644 2593L–AVR–02/07.  */
371#define PRR0    _SFR_MEM8(0x64)  /* AVR Studio 4.13, build 524.  */
372#define PRTWI           7
373#define PRTIM2          6
374#define PRTIM0          5
375#if !defined(__AVR_ATmega644__)
376# define PRUSART1       4
377#endif
378#define PRTIM1          3
379#define PRSPI           2
380#define PRUSART0        1
381#define PRADC           0
382
383/* Reserved [0x65] */
384
385#define OSCCAL  _SFR_MEM8(0x66)
386
387/* Reserved [0x67] */
388
389#define PCICR   _SFR_MEM8(0x68)
390#define PCIE3   3
391#define PCIE2   2
392#define PCIE1   1
393#define PCIE0   0
394
395#define EICRA   _SFR_MEM8(0x69)
396#define ISC21   5
397#define ISC20   4
398#define ISC11   3
399#define ISC10   2
400#define ISC01   1
401#define ISC00   0
402
403/* Reserved [0x6A] */
404
405#define PCMSK0  _SFR_MEM8(0x6B)
406#define PCINT7  7
407#define PCINT6  6
408#define PCINT5  5
409#define PCINT4  4
410#define PCINT3  3
411#define PCINT2  2
412#define PCINT1  1
413#define PCINT0  0
414
415#define PCMSK1  _SFR_MEM8(0x6C)
416#define PCINT15 7
417#define PCINT14 6
418#define PCINT13 5
419#define PCINT12 4
420#define PCINT11 3
421#define PCINT10 2
422#define PCINT9  1
423#define PCINT8  0
424
425#define PCMSK2  _SFR_MEM8(0x6D)
426#define PCINT23 7
427#define PCINT22 6
428#define PCINT21 5
429#define PCINT20 4
430#define PCINT19 3
431#define PCINT18 2
432#define PCINT17 1
433#define PCINT16 0
434
435#define TIMSK0  _SFR_MEM8(0x6E)
436#define OCIE0B  2
437#define OCIE0A  1
438#define TOIE0   0
439
440#define TIMSK1  _SFR_MEM8(0x6F)
441#define ICIE1   5
442#define OCIE1B  2
443#define OCIE1A  1
444#define TOIE1   0
445
446#define TIMSK2  _SFR_MEM8(0x70)
447#define OCIE2B  2
448#define OCIE2A  1
449#define TOIE2   0
450
451/* Reserved [0x71..0x72] */
452
453#define PCMSK3  _SFR_MEM8(0x73)
454#define PCINT31 7
455#define PCINT30 6
456#define PCINT29 5
457#define PCINT28 4
458#define PCINT27 3
459#define PCINT26 2
460#define PCINT25 1
461#define PCINT24 0
462
463/* Reserved [0x74..0x77] */
464
465/* Combine ADCL and ADCH */
466#ifndef __ASSEMBLER__
467#define ADC     _SFR_MEM16(0x78)
468#endif
469#define ADCW    _SFR_MEM16(0x78)
470#define ADCL    _SFR_MEM8(0x78)
471#define ADCH    _SFR_MEM8(0x79)
472
473#define ADCSRA  _SFR_MEM8(0x7A)
474#define ADEN    7
475#define ADSC    6
476#define ADATE   5
477#define ADIF    4
478#define ADIE    3
479#define ADPS2   2
480#define ADPS1   1
481#define ADPS0   0
482
483#define ADCSRB  _SFR_MEM8(0x7B)
484#define ACME    6
485#define ADTS2   2
486#define ADTS1   1
487#define ADTS0   0
488
489#define ADMUX   _SFR_MEM8(0x7C)
490#define REFS1   7
491#define REFS0   6
492#define ADLAR   5
493#define MUX4    4
494#define MUX3    3
495#define MUX2    2
496#define MUX1    1
497#define MUX0    0
498
499/* Reserved [0x7D] */
500
501#define DIDR0   _SFR_MEM8(0x7E)
502#define ADC7D   7
503#define ADC6D   6
504#define ADC5D   5
505#define ADC4D   4
506#define ADC3D   3
507#define ADC2D   2
508#define ADC1D   1
509#define ADC0D   0
510
511#define DIDR1   _SFR_MEM8(0x7F)
512#define AIN1D   1
513#define AIN0D   0
514
515#define TCCR1A  _SFR_MEM8(0x80)
516#define COM1A1  7
517#define COM1A0  6
518#define COM1B1  5
519#define COM1B0  4
520#define WGM11   1
521#define WGM10   0
522
523#define TCCR1B  _SFR_MEM8(0x81)
524#define ICNC1   7
525#define ICES1   6
526#define WGM13   4
527#define WGM12   3
528#define CS12    2
529#define CS11    1
530#define CS10    0
531
532#define TCCR1C  _SFR_MEM8(0x82)
533#define FOC1A   7
534#define FOC1B   6
535
536/* Reserved [0x83] */
537
538/* Combine TCNT1L and TCNT1H */
539#define TCNT1   _SFR_MEM16(0x84)
540
541#define TCNT1L  _SFR_MEM8(0x84)
542#define TCNT1H  _SFR_MEM8(0x85)
543
544/* Combine ICR1L and ICR1H */
545#define ICR1    _SFR_MEM16(0x86)
546
547#define ICR1L   _SFR_MEM8(0x86)
548#define ICR1H   _SFR_MEM8(0x87)
549
550/* Combine OCR1AL and OCR1AH */
551#define OCR1A   _SFR_MEM16(0x88)
552
553#define OCR1AL  _SFR_MEM8(0x88)
554#define OCR1AH  _SFR_MEM8(0x89)
555
556/* Combine OCR1BL and OCR1BH */
557#define OCR1B   _SFR_MEM16(0x8A)
558
559#define OCR1BL  _SFR_MEM8(0x8A)
560#define OCR1BH  _SFR_MEM8(0x8B)
561
562/* Reserved [0x8C..0xAF] */
563
564#define TCCR2A  _SFR_MEM8(0xB0)
565#define COM2A1  7
566#define COM2A0  6
567#define COM2B1  5
568#define COM2B0  4
569#define WGM21   1
570#define WGM20   0
571
572#define TCCR2B  _SFR_MEM8(0xB1)
573#define FOC2A   7
574#define FOC2B   6
575#define WGM22   3
576#define CS22    2
577#define CS21    1
578#define CS20    0
579
580#define TCNT2   _SFR_MEM8(0xB2)
581
582#define OCR2A   _SFR_MEM8(0xB3)
583
584#define OCR2B   _SFR_MEM8(0xB4)
585
586/* Reserved [0xB5] */
587
588#define ASSR    _SFR_MEM8(0xB6)
589#define EXCLK   6
590#define AS2     5
591#define TCN2UB  4
592#define OCR2AUB 3
593#define OCR2BUB 2
594#define TCR2AUB 1
595#define TCR2BUB 0
596
597/* Reserved [0xB7] */
598
599#define TWBR    _SFR_MEM8(0xB8)
600
601#define TWSR    _SFR_MEM8(0xB9)
602#define TWS7    7
603#define TWS6    6
604#define TWS5    5
605#define TWS4    4
606#define TWS3    3
607#define TWPS1   1
608#define TWPS0   0
609
610#define TWAR    _SFR_MEM8(0xBA)
611#define TWA6    7
612#define TWA5    6
613#define TWA4    5
614#define TWA3    4
615#define TWA2    3
616#define TWA1    2
617#define TWA0    1
618#define TWGCE   0
619
620#define TWDR    _SFR_MEM8(0xBB)
621
622#define TWCR    _SFR_MEM8(0xBC)
623#define TWINT   7
624#define TWEA    6
625#define TWSTA   5
626#define TWSTO   4
627#define TWWC    3
628#define TWEN    2
629#define TWIE    0
630
631#define TWAMR   _SFR_MEM8(0xBD)
632#define TWAM6   7
633#define TWAM5   6
634#define TWAM4   5
635#define TWAM3   4
636#define TWAM2   3
637#define TWAM1   2
638#define TWAM0   1
639
640/* Reserved [0xBE..0xBF] */
641
642#define UCSR0A  _SFR_MEM8(0xC0)
643#define RXC0    7
644#define TXC0    6
645#define UDRE0   5
646#define FE0     4
647#define DOR0    3
648#define UPE0    2
649#define U2X0    1
650#define MPCM0   0
651
652#define UCSR0B  _SFR_MEM8(0XC1)
653#define RXCIE0  7
654#define TXCIE0  6
655#define UDRIE0  5
656#define RXEN0   4
657#define TXEN0   3
658#define UCSZ02  2
659#define RXB80   1
660#define TXB80   0
661
662#define UCSR0C  _SFR_MEM8(0xC2)
663#define UMSEL01 7
664#define UMSEL00 6
665#define UPM01   5
666#define UPM00   4
667#define USBS0   3
668#define UCSZ01  2
669#define UCSZ00  1
670#define UCPHA0  1
671#define UCPOL0  0
672
673/* Reserved [0xC3] */
674
675/* Combine UBRR0L and UBRR0H */
676#define UBRR0   _SFR_MEM16(0xC4)
677
678#define UBRR0L  _SFR_MEM8(0xC4)
679#define UBRR0H  _SFR_MEM8(0xC5)
680
681#define UDR0    _SFR_MEM8(0XC6)
682
683#if !defined(__AVR_ATmega644__)
684/*
685 * Only ATmega164P/324P/644P have a second USART.
686 */
687/* Reserved [0xC7] */
688
689#define UCSR1A  _SFR_MEM8(0xC8)
690#define RXC1    7
691#define TXC1    6
692#define UDRE1   5
693#define FE1     4
694#define DOR1    3
695#define UPE1    2
696#define U2X1    1
697#define MPCM1   0
698
699#define UCSR1B  _SFR_MEM8(0XC9)
700#define RXCIE1  7
701#define TXCIE1  6
702#define UDRIE1  5
703#define RXEN1   4
704#define TXEN1   3
705#define UCSZ12  2
706#define RXB81   1
707#define TXB81   0
708
709#define UCSR1C  _SFR_MEM8(0xCA)
710#define UMSEL11 7
711#define UMSEL10 6
712#define UPM11   5
713#define UPM10   4
714#define USBS1   3
715#define UCSZ11  2
716#define UCSZ10  1
717#define UCPHA1  1
718#define UCPOL1  0
719
720/* Reserved [0xCB] */
721
722/* Combine UBRR1L and UBRR1H */
723#define UBRR1   _SFR_MEM16(0xCC)
724
725#define UBRR1L  _SFR_MEM8(0xCC)
726#define UBRR1H  _SFR_MEM8(0xCD)
727
728#define UDR1    _SFR_MEM8(0XCE)
729#endif /* !defined(__AVR_ATmega644) */
730
731/* Reserved [0xCF..0xFF] */
732
733/* Interrupt vectors */
734/* Vector 0 is the reset vector */
735/* External Interrupt Request 0 */
736#define INT0_vect                       _VECTOR(1)
737#define SIG_INTERRUPT0                  _VECTOR(1)
738
739/* External Interrupt Request 1 */
740#define INT1_vect                       _VECTOR(2)
741#define SIG_INTERRUPT1                  _VECTOR(2)
742
743/* External Interrupt Request 2 */
744#define INT2_vect                       _VECTOR(3)
745#define SIG_INTERRUPT2                  _VECTOR(3)
746
747/* Pin Change Interrupt Request 0 */
748#define PCINT0_vect                     _VECTOR(4)
749#define SIG_PIN_CHANGE0                 _VECTOR(4)
750
751/* Pin Change Interrupt Request 1 */
752#define PCINT1_vect                     _VECTOR(5)
753#define SIG_PIN_CHANGE1                 _VECTOR(5)
754
755/* Pin Change Interrupt Request 2 */
756#define PCINT2_vect                     _VECTOR(6)
757#define SIG_PIN_CHANGE2                 _VECTOR(6)
758
759/* Pin Change Interrupt Request 3 */
760#define PCINT3_vect                     _VECTOR(7)
761#define SIG_PIN_CHANGE3                 _VECTOR(7)
762
763/* Watchdog Time-out Interrupt */
764#define WDT_vect                        _VECTOR(8)
765#define SIG_WATCHDOG_TIMEOUT            _VECTOR(8)
766
767/* Timer/Counter2 Compare Match A */
768#define TIMER2_COMPA_vect               _VECTOR(9)
769#define SIG_OUTPUT_COMPARE2A            _VECTOR(9)
770
771/* Timer/Counter2 Compare Match B */
772#define TIMER2_COMPB_vect               _VECTOR(10)
773#define SIG_OUTPUT_COMPARE2B            _VECTOR(10)
774
775/* Timer/Counter2 Overflow */
776#define TIMER2_OVF_vect                 _VECTOR(11)
777#define SIG_OVERFLOW2                   _VECTOR(11)
778
779/* Timer/Counter1 Capture Event */
780#define TIMER1_CAPT_vect                _VECTOR(12)
781#define SIG_INPUT_CAPTURE1              _VECTOR(12)
782
783/* Timer/Counter1 Compare Match A */
784#define TIMER1_COMPA_vect               _VECTOR(13)
785#define SIG_OUTPUT_COMPARE1A            _VECTOR(13)
786
787/* Timer/Counter1 Compare Match B */
788#define TIMER1_COMPB_vect               _VECTOR(14)
789#define SIG_OUTPUT_COMPARE1B            _VECTOR(14)
790
791/* Timer/Counter1 Overflow */
792#define TIMER1_OVF_vect                 _VECTOR(15)
793#define SIG_OVERFLOW1                   _VECTOR(15)
794
795/* Timer/Counter0 Compare Match A */
796#define TIMER0_COMPA_vect               _VECTOR(16)
797#define SIG_OUTPUT_COMPARE0A            _VECTOR(16)
798
799/* Timer/Counter0 Compare Match B */
800#define TIMER0_COMPB_vect               _VECTOR(17)
801#define SIG_OUTPUT_COMPARE0B            _VECTOR(17)
802
803/* Timer/Counter0 Overflow */
804#define TIMER0_OVF_vect                 _VECTOR(18)
805#define SIG_OVERFLOW0                   _VECTOR(18)
806
807/* SPI Serial Transfer Complete */
808#define SPI_STC_vect                    _VECTOR(19)
809#define SIG_SPI                         _VECTOR(19)
810
811/* USART0, Rx Complete */
812#define USART0_RX_vect                  _VECTOR(20)
813#define SIG_USART_RECV                  _VECTOR(20)
814
815/* USART0 Data register Empty */
816#define USART0_UDRE_vect                _VECTOR(21)
817#define SIG_USART_DATA                  _VECTOR(21)
818
819/* USART0, Tx Complete */
820#define USART0_TX_vect                  _VECTOR(22)
821#define SIG_USART_TRANS                 _VECTOR(22)
822
823/* Analog Comparator */
824#define ANALOG_COMP_vect                _VECTOR(23)
825#define SIG_COMPARATOR                  _VECTOR(23)
826
827/* ADC Conversion Complete */
828#define ADC_vect                        _VECTOR(24)
829#define SIG_ADC                         _VECTOR(24)
830
831/* EEPROM Ready */
832#define EE_READY_vect                   _VECTOR(25)
833#define SIG_EEPROM_READY                _VECTOR(25)
834
835/* 2-wire Serial Interface */
836#define TWI_vect                        _VECTOR(26)
837#define SIG_2WIRE_SERIAL                _VECTOR(26)
838
839/* Store Program Memory Read */
840#define SPM_READY_vect                  _VECTOR(27)
841#define SIG_SPM_READY                   _VECTOR(27)
842
843#if defined(__AVR_ATmega644__)
844
845# define _VECTORS_SIZE 112
846
847#else /* !defined(__AVR_ATmega644__) */
848
849/* USART1, Rx Complete */
850/* USART1 RX complete */
851#define USART1_RX_vect                  _VECTOR(28)
852#define SIG_USART1_RECV                 _VECTOR(28)
853
854/* USART1 Data register Empty */
855/* USART1 Data Register Empty */
856#define USART1_UDRE_vect                _VECTOR(29)
857#define SIG_USART1_DATA                 _VECTOR(29)
858
859/* USART1, Tx Complete */
860/* USART1 TX complete */
861#define USART1_TX_vect                  _VECTOR(30)
862#define SIG_USART1_TRANS                _VECTOR(30)
863
864# define _VECTORS_SIZE 124
865
866#endif /* defined(__AVR_ATmega644__) */
867
868
869#endif /* _AVR_IOMXX4_H_ */
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