1 | /* Copyright (c) 2005 Anatoly Sokolov |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* avr/iomxx0_1.h - definitions for ATmega640, Atmega1280, ATmega1281, |
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34 | ATmega2560 and ATmega2561. */ |
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35 | |
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36 | #ifndef _AVR_IOMXX0_1_H_ |
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37 | #define _AVR_IOMXX0_1_H_ 1 |
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38 | |
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39 | /* This file should only be included from <avr/io.h>, never directly. */ |
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40 | |
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41 | #ifndef _AVR_IO_H_ |
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42 | # error "Include <avr/io.h> instead of this file." |
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43 | #endif |
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44 | |
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45 | #ifndef _AVR_IOXXX_H_ |
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46 | # define _AVR_IOXXX_H_ "iomxx0_1.h" |
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47 | #else |
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48 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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49 | #endif |
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50 | |
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51 | #if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) |
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52 | # define __ATmegaxx0__ |
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53 | #elif defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) |
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54 | # define __ATmegaxx1__ |
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55 | #endif |
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56 | |
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57 | /* Registers and associated bit numbers */ |
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58 | |
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59 | #define PINA _SFR_IO8(0X00) |
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60 | #define PINA7 7 |
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61 | #define PINA6 6 |
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62 | #define PINA5 5 |
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63 | #define PINA4 4 |
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64 | #define PINA3 3 |
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65 | #define PINA2 2 |
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66 | #define PINA1 1 |
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67 | #define PINA0 0 |
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68 | |
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69 | #define DDRA _SFR_IO8(0X01) |
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70 | #define DDA7 7 |
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71 | #define DDA6 6 |
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72 | #define DDA5 5 |
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73 | #define DDA4 4 |
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74 | #define DDA3 3 |
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75 | #define DDA2 2 |
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76 | #define DDA1 1 |
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77 | #define DDA0 0 |
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78 | |
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79 | #define PORTA _SFR_IO8(0X02) |
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80 | #define PA7 7 |
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81 | #define PA6 6 |
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82 | #define PA5 5 |
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83 | #define PA4 4 |
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84 | #define PA3 3 |
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85 | #define PA2 2 |
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86 | #define PA1 1 |
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87 | #define PA0 0 |
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88 | |
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89 | #define PINB _SFR_IO8(0X03) |
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90 | #define PINB7 7 |
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91 | #define PINB6 6 |
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92 | #define PINB5 5 |
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93 | #define PINB4 4 |
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94 | #define PINB3 3 |
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95 | #define PINB2 2 |
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96 | #define PINB1 1 |
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97 | #define PINB0 0 |
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98 | |
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99 | #define DDRB _SFR_IO8(0x04) |
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100 | #define DDB7 7 |
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101 | #define DDB6 6 |
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102 | #define DDB5 5 |
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103 | #define DDB4 4 |
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104 | #define DDB3 3 |
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105 | #define DDB2 2 |
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106 | #define DDB1 1 |
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107 | #define DDB0 0 |
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108 | |
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109 | #define PORTB _SFR_IO8(0x05) |
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110 | #define PB7 7 |
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111 | #define PB6 6 |
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112 | #define PB5 5 |
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113 | #define PB4 4 |
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114 | #define PB3 3 |
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115 | #define PB2 2 |
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116 | #define PB1 1 |
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117 | #define PB0 0 |
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118 | |
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119 | #define PINC _SFR_IO8(0x06) |
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120 | #define PINC7 7 |
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121 | #define PINC6 6 |
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122 | #define PINC5 5 |
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123 | #define PINC4 4 |
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124 | #define PINC3 3 |
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125 | #define PINC2 2 |
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126 | #define PINC1 1 |
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127 | #define PINC0 0 |
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128 | |
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129 | #define DDRC _SFR_IO8(0x07) |
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130 | #define DDC7 7 |
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131 | #define DDC6 6 |
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132 | #define DDC5 5 |
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133 | #define DDC4 4 |
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134 | #define DDC3 3 |
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135 | #define DDC2 2 |
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136 | #define DDC1 1 |
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137 | #define DDC0 0 |
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138 | |
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139 | #define PORTC _SFR_IO8(0x08) |
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140 | #define PC7 7 |
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141 | #define PC6 6 |
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142 | #define PC5 5 |
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143 | #define PC4 4 |
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144 | #define PC3 3 |
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145 | #define PC2 2 |
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146 | #define PC1 1 |
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147 | #define PC0 0 |
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148 | |
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149 | #define PIND _SFR_IO8(0x09) |
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150 | #define PIND7 7 |
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151 | #define PIND6 6 |
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152 | #define PIND5 5 |
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153 | #define PIND4 4 |
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154 | #define PIND3 3 |
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155 | #define PIND2 2 |
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156 | #define PIND1 1 |
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157 | #define PIND0 0 |
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158 | |
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159 | #define DDRD _SFR_IO8(0x0A) |
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160 | #define DDD7 7 |
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161 | #define DDD6 6 |
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162 | #define DDD5 5 |
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163 | #define DDD4 4 |
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164 | #define DDD3 3 |
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165 | #define DDD2 2 |
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166 | #define DDD1 1 |
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167 | #define DDD0 0 |
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168 | |
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169 | #define PORTD _SFR_IO8(0x0B) |
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170 | #define PD7 7 |
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171 | #define PD6 6 |
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172 | #define PD5 5 |
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173 | #define PD4 4 |
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174 | #define PD3 3 |
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175 | #define PD2 2 |
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176 | #define PD1 1 |
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177 | #define PD0 0 |
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178 | |
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179 | #define PINE _SFR_IO8(0x0C) |
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180 | #define PINE7 7 |
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181 | #define PINE6 6 |
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182 | #define PINE5 5 |
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183 | #define PINE4 4 |
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184 | #define PINE3 3 |
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185 | #define PINE2 2 |
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186 | #define PINE1 1 |
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187 | #define PINE0 0 |
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188 | |
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189 | #define DDRE _SFR_IO8(0x0D) |
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190 | #define DDE7 7 |
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191 | #define DDE6 6 |
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192 | #define DDE5 5 |
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193 | #define DDE4 4 |
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194 | #define DDE3 3 |
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195 | #define DDE2 2 |
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196 | #define DDE1 1 |
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197 | #define DDE0 0 |
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198 | |
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199 | #define PORTE _SFR_IO8(0x0E) |
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200 | #define PE7 7 |
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201 | #define PE6 6 |
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202 | #define PE5 5 |
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203 | #define PE4 4 |
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204 | #define PE3 3 |
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205 | #define PE2 2 |
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206 | #define PE1 1 |
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207 | #define PE0 0 |
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208 | |
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209 | #define PINF _SFR_IO8(0x0F) |
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210 | #define PINF7 7 |
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211 | #define PINF6 6 |
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212 | #define PINF5 5 |
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213 | #define PINF4 4 |
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214 | #define PINF3 3 |
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215 | #define PINF2 2 |
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216 | #define PINF1 1 |
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217 | #define PINF0 0 |
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218 | |
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219 | #define DDRF _SFR_IO8(0x10) |
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220 | #define DDF7 7 |
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221 | #define DDF6 6 |
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222 | #define DDF5 5 |
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223 | #define DDF4 4 |
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224 | #define DDF3 3 |
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225 | #define DDF2 2 |
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226 | #define DDF1 1 |
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227 | #define DDF0 0 |
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228 | |
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229 | #define PORTF _SFR_IO8(0x11) |
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230 | #define PF7 7 |
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231 | #define PF6 6 |
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232 | #define PF5 5 |
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233 | #define PF4 4 |
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234 | #define PF3 3 |
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235 | #define PF2 2 |
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236 | #define PF1 1 |
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237 | #define PF0 0 |
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238 | |
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239 | #define PING _SFR_IO8(0x12) |
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240 | #define PING5 5 |
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241 | #define PING4 4 |
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242 | #define PING3 3 |
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243 | #define PING2 2 |
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244 | #define PING1 1 |
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245 | #define PING0 0 |
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246 | |
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247 | #define DDRG _SFR_IO8(0x13) |
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248 | #define DDG5 5 |
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249 | #define DDG4 4 |
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250 | #define DDG3 3 |
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251 | #define DDG2 2 |
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252 | #define DDG1 1 |
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253 | #define DDG0 0 |
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254 | |
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255 | #define PORTG _SFR_IO8(0x14) |
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256 | #define PG5 5 |
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257 | #define PG4 4 |
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258 | #define PG3 3 |
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259 | #define PG2 2 |
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260 | #define PG1 1 |
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261 | #define PG0 0 |
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262 | |
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263 | #define TIFR0 _SFR_IO8(0x15) |
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264 | #define OCF0B 2 |
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265 | #define OCF0A 1 |
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266 | #define TOV0 0 |
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267 | |
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268 | #define TIFR1 _SFR_IO8(0x16) |
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269 | #define ICF1 5 |
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270 | #define OCF1C 3 |
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271 | #define OCF1B 2 |
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272 | #define OCF1A 1 |
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273 | #define TOV1 0 |
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274 | |
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275 | #define TIFR2 _SFR_IO8(0x17) |
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276 | #define OCF2B 2 |
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277 | #define OCF2A 1 |
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278 | #define TOV2 0 |
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279 | |
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280 | #define TIFR3 _SFR_IO8(0x18) |
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281 | #define ICF3 5 |
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282 | #define OCF3C 3 |
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283 | #define OCF3B 2 |
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284 | #define OCF3A 1 |
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285 | #define TOV3 0 |
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286 | |
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287 | #define TIFR4 _SFR_IO8(0x19) |
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288 | #define ICF4 5 |
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289 | #define OCF4C 3 |
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290 | #define OCF4B 2 |
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291 | #define OCF4A 1 |
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292 | #define TOV4 0 |
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293 | |
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294 | #define TIFR5 _SFR_IO8(0x1A) |
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295 | #define ICF5 5 |
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296 | #define OCF5C 3 |
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297 | #define OCF5B 2 |
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298 | #define OCF5A 1 |
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299 | #define TOV5 0 |
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300 | |
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301 | #define PCIFR _SFR_IO8(0x1B) |
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302 | #if defined(__ATmegaxx0__) |
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303 | # define PCIF2 2 |
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304 | #endif /* __ATmegaxx0__ */ |
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305 | #define PCIF1 1 |
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306 | #define PCIF0 0 |
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307 | |
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308 | #define EIFR _SFR_IO8(0x1C) |
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309 | #define INTF7 7 |
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310 | #define INTF6 6 |
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311 | #define INTF5 5 |
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312 | #define INTF4 4 |
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313 | #define INTF3 3 |
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314 | #define INTF2 2 |
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315 | #define INTF1 1 |
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316 | #define INTF0 0 |
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317 | |
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318 | #define EIMSK _SFR_IO8(0x1D) |
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319 | #define INT7 7 |
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320 | #define INT6 6 |
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321 | #define INT5 5 |
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322 | #define INT4 4 |
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323 | #define INT3 3 |
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324 | #define INT2 2 |
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325 | #define INT1 1 |
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326 | #define INT0 0 |
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327 | |
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328 | #define GPIOR0 _SFR_IO8(0x1E) |
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329 | |
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330 | #define EECR _SFR_IO8(0x1F) |
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331 | #define EEPM1 5 |
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332 | #define EEPM0 4 |
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333 | #define EERIE 3 |
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334 | #define EEMPE 2 |
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335 | #define EEPE 1 |
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336 | #define EERE 0 |
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337 | |
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338 | #define EEDR _SFR_IO8(0X20) |
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339 | |
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340 | /* Combine EEARL and EEARH */ |
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341 | #define EEAR _SFR_IO16(0x21) |
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342 | |
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343 | #define EEARL _SFR_IO8(0x21) |
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344 | #define EEARH _SFR_IO8(0X22) |
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345 | |
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346 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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347 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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348 | subroutines. |
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349 | First two letters: EECR address. |
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350 | Second two letters: EEDR address. |
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351 | Last two letters: EEAR address. */ |
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352 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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353 | |
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354 | #define GTCCR _SFR_IO8(0x23) |
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355 | #define TSM 7 |
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356 | #define PSRASY 1 |
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357 | #define PSRSYNC 0 |
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358 | |
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359 | #define TCCR0A _SFR_IO8(0x24) |
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360 | #define COM0A1 7 |
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361 | #define COM0A0 6 |
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362 | #define COM0B1 5 |
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363 | #define COM0B0 4 |
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364 | #define WGM01 1 |
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365 | #define WGM00 0 |
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366 | |
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367 | #define TCCR0B _SFR_IO8(0x25) |
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368 | #define FOC0A 7 |
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369 | #define FOC0B 6 |
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370 | #define WGM02 3 |
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371 | #define CS02 2 |
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372 | #define CS01 1 |
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373 | #define CS00 0 |
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374 | |
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375 | #define TCNT0 _SFR_IO8(0X26) |
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376 | |
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377 | #define OCR0A _SFR_IO8(0X27) |
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378 | |
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379 | #define OCR0B _SFR_IO8(0X28) |
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380 | |
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381 | /* Reserved [0x29] */ |
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382 | |
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383 | #define GPIOR1 _SFR_IO8(0x2A) |
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384 | |
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385 | #define GPIOR2 _SFR_IO8(0x2B) |
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386 | |
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387 | #define SPCR _SFR_IO8(0x2C) |
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388 | #define SPIE 7 |
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389 | #define SPE 6 |
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390 | #define DORD 5 |
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391 | #define MSTR 4 |
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392 | #define CPOL 3 |
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393 | #define CPHA 2 |
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394 | #define SPR1 1 |
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395 | #define SPR0 0 |
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396 | |
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397 | #define SPSR _SFR_IO8(0x2D) |
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398 | #define SPIF 7 |
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399 | #define WCOL 6 |
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400 | #define SPI2X 0 |
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401 | |
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402 | #define SPDR _SFR_IO8(0X2E) |
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403 | |
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404 | /* Reserved [0x2F] */ |
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405 | |
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406 | #define ACSR _SFR_IO8(0x30) |
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407 | #define ACD 7 |
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408 | #define ACBG 6 |
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409 | #define ACO 5 |
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410 | #define ACI 4 |
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411 | #define ACIE 3 |
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412 | #define ACIC 2 |
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413 | #define ACIS1 1 |
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414 | #define ACIS0 0 |
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415 | |
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416 | #define MONDR _SFR_IO8(0x31) |
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417 | #define OCDR _SFR_IO8(0x31) |
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418 | #define IDRD 7 |
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419 | #define OCDR7 7 |
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420 | #define OCDR6 6 |
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421 | #define OCDR5 5 |
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422 | #define OCDR4 4 |
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423 | #define OCDR3 3 |
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424 | #define OCDR2 2 |
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425 | #define OCDR1 1 |
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426 | #define OCDR0 0 |
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427 | |
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428 | /* Reserved [0x32] */ |
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429 | |
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430 | #define SMCR _SFR_IO8(0x33) |
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431 | #define SM2 3 |
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432 | #define SM1 2 |
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433 | #define SM0 1 |
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434 | #define SE 0 |
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435 | |
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436 | #define MCUSR _SFR_IO8(0x34) |
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437 | #define JTRF 4 |
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438 | #define WDRF 3 |
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439 | #define BORF 2 |
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440 | #define EXTRF 1 |
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441 | #define PORF 0 |
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442 | |
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443 | #define MCUCR _SFR_IO8(0X35) |
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444 | #define JTD 7 |
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445 | #define PUD 4 |
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446 | #define IVSEL 1 |
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447 | #define IVCE 0 |
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448 | |
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449 | /* Reserved [0x36] */ |
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450 | |
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451 | #define SPMCSR _SFR_IO8(0x37) |
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452 | #define SPMIE 7 |
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453 | #define RWWSB 6 |
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454 | #define SIGRD 5 |
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455 | #define RWWSRE 4 |
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456 | #define BLBSET 3 |
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457 | #define PGWRT 2 |
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458 | #define PGERS 1 |
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459 | #define SPMEN 0 |
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460 | |
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461 | /* Reserved [0x38..0x3A] */ |
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462 | |
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463 | #define RAMPZ _SFR_IO8(0X3B) |
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464 | #define RAMPZ0 0 |
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465 | |
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466 | #define EIND _SFR_IO8(0X3C) |
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467 | #define EIND0 0 |
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468 | |
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469 | /* SP [0x3D..0x3E] */ |
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470 | /* SREG [0x3F] */ |
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471 | |
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472 | #define WDTCSR _SFR_MEM8(0x60) |
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473 | #define WDIF 7 |
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474 | #define WDIE 6 |
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475 | #define WDP3 5 |
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476 | #define WDCE 4 |
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477 | #define WDE 3 |
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478 | #define WDP2 2 |
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479 | #define WDP1 1 |
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480 | #define WDP0 0 |
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481 | |
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482 | #define CLKPR _SFR_MEM8(0x61) |
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483 | #define CLKPCE 7 |
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484 | #define CLKPS3 3 |
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485 | #define CLKPS2 2 |
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486 | #define CLKPS1 1 |
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487 | #define CLKPS0 0 |
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488 | |
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489 | /* Reserved [0x62..0x63] */ |
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490 | |
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491 | #define PRR0 _SFR_MEM8(0x64) |
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492 | #define PRTWI 7 |
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493 | #define PRTIM2 6 |
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494 | #define PRTIM0 5 |
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495 | #define PRTIM1 3 |
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496 | #define PRSPI 2 |
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497 | #define PRUSART0 1 |
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498 | #define PRADC 0 |
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499 | |
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500 | #define PRR1 _SFR_MEM8(0x65) |
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501 | #define PRTIM5 5 |
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502 | #define PRTIM4 4 |
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503 | #define PRTIM3 3 |
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504 | #define PRUSART3 2 |
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505 | #define PRUSART2 1 |
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506 | #define PRUSART1 0 |
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507 | |
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508 | #define OSCCAL _SFR_MEM8(0x66) |
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509 | |
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510 | /* Reserved [0x67] */ |
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511 | |
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512 | #define PCICR _SFR_MEM8(0x68) |
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513 | #if defined(__ATmegaxx0__) |
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514 | # define PCIE2 2 |
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515 | #endif /* __ATmegaxx0__ */ |
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516 | #define PCIE1 1 |
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517 | #define PCIE0 0 |
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518 | |
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519 | #define EICRA _SFR_MEM8(0x69) |
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520 | #define ISC31 7 |
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521 | #define ISC30 6 |
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522 | #define ISC21 5 |
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523 | #define ISC20 4 |
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524 | #define ISC11 3 |
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525 | #define ISC10 2 |
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526 | #define ISC01 1 |
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527 | #define ISC00 0 |
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528 | |
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529 | #define EICRB _SFR_MEM8(0x6A) |
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530 | #define ISC71 7 |
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531 | #define ISC70 6 |
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532 | #define ISC61 5 |
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533 | #define ISC60 4 |
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534 | #define ISC51 3 |
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535 | #define ISC50 2 |
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536 | #define ISC41 1 |
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537 | #define ISC40 0 |
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538 | |
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539 | #define PCMSK0 _SFR_MEM8(0x6B) |
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540 | #define PCINT7 7 |
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541 | #define PCINT6 6 |
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542 | #define PCINT5 5 |
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543 | #define PCINT4 4 |
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544 | #define PCINT3 3 |
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545 | #define PCINT2 2 |
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546 | #define PCINT1 1 |
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547 | #define PCINT0 0 |
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548 | |
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549 | #define PCMSK1 _SFR_MEM8(0x6C) |
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550 | #define PCINT15 7 |
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551 | #define PCINT14 6 |
---|
552 | #define PCINT13 5 |
---|
553 | #define PCINT12 4 |
---|
554 | #define PCINT11 3 |
---|
555 | #define PCINT10 2 |
---|
556 | #define PCINT9 1 |
---|
557 | #define PCINT8 0 |
---|
558 | |
---|
559 | #if defined(__ATmegaxx0__) |
---|
560 | # define PCMSK2 _SFR_MEM8(0x6D) |
---|
561 | # define PCINT23 7 |
---|
562 | # define PCINT22 6 |
---|
563 | # define PCINT21 5 |
---|
564 | # define PCINT20 4 |
---|
565 | # define PCINT19 3 |
---|
566 | # define PCINT18 2 |
---|
567 | # define PCINT17 1 |
---|
568 | # define PCINT16 0 |
---|
569 | #endif /* __ATmegaxx0__ */ |
---|
570 | |
---|
571 | #define TIMSK0 _SFR_MEM8(0x6E) |
---|
572 | #define OCIE0B 2 |
---|
573 | #define OCIE0A 1 |
---|
574 | #define TOIE0 0 |
---|
575 | |
---|
576 | #define TIMSK1 _SFR_MEM8(0x6F) |
---|
577 | #define ICIE1 5 |
---|
578 | #define OCIE1C 3 |
---|
579 | #define OCIE1B 2 |
---|
580 | #define OCIE1A 1 |
---|
581 | #define TOIE1 0 |
---|
582 | |
---|
583 | #define TIMSK2 _SFR_MEM8(0x70) |
---|
584 | #define OCIE2B 2 |
---|
585 | #define OCIE2A 1 |
---|
586 | #define TOIE2 0 |
---|
587 | |
---|
588 | #define TIMSK3 _SFR_MEM8(0x71) |
---|
589 | #define ICIE3 5 |
---|
590 | #define OCIE3C 3 |
---|
591 | #define OCIE3B 2 |
---|
592 | #define OCIE3A 1 |
---|
593 | #define TOIE3 0 |
---|
594 | |
---|
595 | #define TIMSK4 _SFR_MEM8(0x72) |
---|
596 | #define ICIE4 5 |
---|
597 | #define OCIE4C 3 |
---|
598 | #define OCIE4B 2 |
---|
599 | #define OCIE4A 1 |
---|
600 | #define TOIE4 0 |
---|
601 | |
---|
602 | #define TIMSK5 _SFR_MEM8(0x73) |
---|
603 | #define ICIE5 5 |
---|
604 | #define OCIE5C 3 |
---|
605 | #define OCIE5B 2 |
---|
606 | #define OCIE5A 1 |
---|
607 | #define TOIE5 0 |
---|
608 | |
---|
609 | #define XMCRA _SFR_MEM8(0x74) |
---|
610 | #define SRE 7 |
---|
611 | #define SRL2 6 |
---|
612 | #define SRL1 5 |
---|
613 | #define SRL0 4 |
---|
614 | #define SRW11 3 |
---|
615 | #define SRW10 2 |
---|
616 | #define SRW01 1 |
---|
617 | #define SRW00 0 |
---|
618 | |
---|
619 | #define XMCRB _SFR_MEM8(0x75) |
---|
620 | #define XMBK 7 |
---|
621 | #define XMM2 2 |
---|
622 | #define XMM1 1 |
---|
623 | #define XMM0 0 |
---|
624 | |
---|
625 | /* Reserved [0x76..0x77] */ |
---|
626 | |
---|
627 | /* Combine ADCL and ADCH */ |
---|
628 | #ifndef __ASSEMBLER__ |
---|
629 | #define ADC _SFR_MEM16(0x78) |
---|
630 | #endif |
---|
631 | #define ADCW _SFR_MEM16(0x78) |
---|
632 | #define ADCL _SFR_MEM8(0x78) |
---|
633 | #define ADCH _SFR_MEM8(0x79) |
---|
634 | |
---|
635 | #define ADCSRA _SFR_MEM8(0x7A) |
---|
636 | #define ADEN 7 |
---|
637 | #define ADSC 6 |
---|
638 | #define ADATE 5 |
---|
639 | #define ADIF 4 |
---|
640 | #define ADIE 3 |
---|
641 | #define ADPS2 2 |
---|
642 | #define ADPS1 1 |
---|
643 | #define ADPS0 0 |
---|
644 | |
---|
645 | #define ADCSRB _SFR_MEM8(0x7B) |
---|
646 | #define ACME 6 |
---|
647 | #if defined(__ATmegaxx0__) |
---|
648 | # define MUX5 3 |
---|
649 | #endif /* __ATmegaxx0__ */ |
---|
650 | #define ADTS2 2 |
---|
651 | #define ADTS1 1 |
---|
652 | #define ADTS0 0 |
---|
653 | |
---|
654 | #define ADMUX _SFR_MEM8(0x7C) |
---|
655 | #define REFS1 7 |
---|
656 | #define REFS0 6 |
---|
657 | #define ADLAR 5 |
---|
658 | #define MUX4 4 |
---|
659 | #define MUX3 3 |
---|
660 | #define MUX2 2 |
---|
661 | #define MUX1 1 |
---|
662 | #define MUX0 0 |
---|
663 | |
---|
664 | #define DIDR2 _SFR_MEM8(0x7D) |
---|
665 | #define ADC15D 7 |
---|
666 | #define ADC14D 6 |
---|
667 | #define ADC13D 5 |
---|
668 | #define ADC12D 4 |
---|
669 | #define ADC11D 3 |
---|
670 | #define ADC10D 2 |
---|
671 | #define ADC9D 1 |
---|
672 | #define ADC8D 0 |
---|
673 | |
---|
674 | #define DIDR0 _SFR_MEM8(0x7E) |
---|
675 | #define ADC7D 7 |
---|
676 | #define ADC6D 6 |
---|
677 | #define ADC5D 5 |
---|
678 | #define ADC4D 4 |
---|
679 | #define ADC3D 3 |
---|
680 | #define ADC2D 2 |
---|
681 | #define ADC1D 1 |
---|
682 | #define ADC0D 0 |
---|
683 | |
---|
684 | #define DIDR1 _SFR_MEM8(0x7F) |
---|
685 | #define AIN1D 1 |
---|
686 | #define AIN0D 0 |
---|
687 | |
---|
688 | #define TCCR1A _SFR_MEM8(0x80) |
---|
689 | #define COM1A1 7 |
---|
690 | #define COM1A0 6 |
---|
691 | #define COM1B1 5 |
---|
692 | #define COM1B0 4 |
---|
693 | #define COM1C1 3 |
---|
694 | #define COM1C0 2 |
---|
695 | #define WGM11 1 |
---|
696 | #define WGM10 0 |
---|
697 | |
---|
698 | #define TCCR1B _SFR_MEM8(0x81) |
---|
699 | #define ICNC1 7 |
---|
700 | #define ICES1 6 |
---|
701 | #define WGM13 4 |
---|
702 | #define WGM12 3 |
---|
703 | #define CS12 2 |
---|
704 | #define CS11 1 |
---|
705 | #define CS10 0 |
---|
706 | |
---|
707 | #define TCCR1C _SFR_MEM8(0x82) |
---|
708 | #define FOC1A 7 |
---|
709 | #define FOC1B 6 |
---|
710 | #define FOC1C 5 |
---|
711 | |
---|
712 | /* Reserved [0x83] */ |
---|
713 | |
---|
714 | /* Combine TCNT1L and TCNT1H */ |
---|
715 | #define TCNT1 _SFR_MEM16(0x84) |
---|
716 | |
---|
717 | #define TCNT1L _SFR_MEM8(0x84) |
---|
718 | #define TCNT1H _SFR_MEM8(0x85) |
---|
719 | |
---|
720 | /* Combine ICR1L and ICR1H */ |
---|
721 | #define ICR1 _SFR_MEM16(0x86) |
---|
722 | |
---|
723 | #define ICR1L _SFR_MEM8(0x86) |
---|
724 | #define ICR1H _SFR_MEM8(0x87) |
---|
725 | |
---|
726 | /* Combine OCR1AL and OCR1AH */ |
---|
727 | #define OCR1A _SFR_MEM16(0x88) |
---|
728 | |
---|
729 | #define OCR1AL _SFR_MEM8(0x88) |
---|
730 | #define OCR1AH _SFR_MEM8(0x89) |
---|
731 | |
---|
732 | /* Combine OCR1BL and OCR1BH */ |
---|
733 | #define OCR1B _SFR_MEM16(0x8A) |
---|
734 | |
---|
735 | #define OCR1BL _SFR_MEM8(0x8A) |
---|
736 | #define OCR1BH _SFR_MEM8(0x8B) |
---|
737 | |
---|
738 | /* Combine OCR1CL and OCR1CH */ |
---|
739 | #define OCR1C _SFR_MEM16(0x8C) |
---|
740 | |
---|
741 | #define OCR1CL _SFR_MEM8(0x8C) |
---|
742 | #define OCR1CH _SFR_MEM8(0x8D) |
---|
743 | |
---|
744 | /* Reserved [0x8E..0x8F] */ |
---|
745 | |
---|
746 | #define TCCR3A _SFR_MEM8(0x90) |
---|
747 | #define COM3A1 7 |
---|
748 | #define COM3A0 6 |
---|
749 | #define COM3B1 5 |
---|
750 | #define COM3B0 4 |
---|
751 | #define COM3C1 3 |
---|
752 | #define COM3C0 2 |
---|
753 | #define WGM31 1 |
---|
754 | #define WGM30 0 |
---|
755 | |
---|
756 | #define TCCR3B _SFR_MEM8(0x91) |
---|
757 | #define ICNC3 7 |
---|
758 | #define ICES3 6 |
---|
759 | #define WGM33 4 |
---|
760 | #define WGM32 3 |
---|
761 | #define CS32 2 |
---|
762 | #define CS31 1 |
---|
763 | #define CS30 0 |
---|
764 | |
---|
765 | #define TCCR3C _SFR_MEM8(0x92) |
---|
766 | #define FOC3A 7 |
---|
767 | #define FOC3B 6 |
---|
768 | #define FOC3C 5 |
---|
769 | |
---|
770 | /* Reserved [0x93] */ |
---|
771 | |
---|
772 | /* Combine TCNT3L and TCNT3H */ |
---|
773 | #define TCNT3 _SFR_MEM16(0x94) |
---|
774 | |
---|
775 | #define TCNT3L _SFR_MEM8(0x94) |
---|
776 | #define TCNT3H _SFR_MEM8(0x95) |
---|
777 | |
---|
778 | /* Combine ICR3L and ICR3H */ |
---|
779 | #define ICR3 _SFR_MEM16(0x96) |
---|
780 | |
---|
781 | #define ICR3L _SFR_MEM8(0x96) |
---|
782 | #define ICR3H _SFR_MEM8(0x97) |
---|
783 | |
---|
784 | /* Combine OCR3AL and OCR3AH */ |
---|
785 | #define OCR3A _SFR_MEM16(0x98) |
---|
786 | |
---|
787 | #define OCR3AL _SFR_MEM8(0x98) |
---|
788 | #define OCR3AH _SFR_MEM8(0x99) |
---|
789 | |
---|
790 | /* Combine OCR3BL and OCR3BH */ |
---|
791 | #define OCR3B _SFR_MEM16(0x9A) |
---|
792 | |
---|
793 | #define OCR3BL _SFR_MEM8(0x9A) |
---|
794 | #define OCR3BH _SFR_MEM8(0x9B) |
---|
795 | |
---|
796 | /* Combine OCR3CL and OCR3CH */ |
---|
797 | #define OCR3C _SFR_MEM16(0x9C) |
---|
798 | |
---|
799 | #define OCR3CL _SFR_MEM8(0x9C) |
---|
800 | #define OCR3CH _SFR_MEM8(0x9D) |
---|
801 | |
---|
802 | /* Reserved [0x9E..0x9F] */ |
---|
803 | |
---|
804 | #define TCCR4A _SFR_MEM8(0xA0) |
---|
805 | #define COM4A1 7 |
---|
806 | #define COM4A0 6 |
---|
807 | #define COM4B1 5 |
---|
808 | #define COM4B0 4 |
---|
809 | #define COM4C1 3 |
---|
810 | #define COM4C0 2 |
---|
811 | #define WGM41 1 |
---|
812 | #define WGM40 0 |
---|
813 | |
---|
814 | #define TCCR4B _SFR_MEM8(0xA1) |
---|
815 | #define ICNC4 7 |
---|
816 | #define ICES4 6 |
---|
817 | #define WGM43 4 |
---|
818 | #define WGM42 3 |
---|
819 | #define CS42 2 |
---|
820 | #define CS41 1 |
---|
821 | #define CS40 0 |
---|
822 | |
---|
823 | #define TCCR4C _SFR_MEM8(0xA2) |
---|
824 | #define FOC4A 7 |
---|
825 | #define FOC4B 6 |
---|
826 | #define FOC4C 5 |
---|
827 | |
---|
828 | /* Reserved [0xA3] */ |
---|
829 | |
---|
830 | /* Combine TCNT4L and TCNT4H */ |
---|
831 | #define TCNT4 _SFR_MEM16(0xA4) |
---|
832 | |
---|
833 | #define TCNT4L _SFR_MEM8(0xA4) |
---|
834 | #define TCNT4H _SFR_MEM8(0xA5) |
---|
835 | |
---|
836 | /* Combine ICR4L and ICR4H */ |
---|
837 | #define ICR4 _SFR_MEM16(0xA6) |
---|
838 | |
---|
839 | #define ICR4L _SFR_MEM8(0xA6) |
---|
840 | #define ICR4H _SFR_MEM8(0xA7) |
---|
841 | |
---|
842 | /* Combine OCR4AL and OCR4AH */ |
---|
843 | #define OCR4A _SFR_MEM16(0xA8) |
---|
844 | |
---|
845 | #define OCR4AL _SFR_MEM8(0xA8) |
---|
846 | #define OCR4AH _SFR_MEM8(0xA9) |
---|
847 | |
---|
848 | /* Combine OCR4BL and OCR4BH */ |
---|
849 | #define OCR4B _SFR_MEM16(0xAA) |
---|
850 | |
---|
851 | #define OCR4BL _SFR_MEM8(0xAA) |
---|
852 | #define OCR4BH _SFR_MEM8(0xAB) |
---|
853 | |
---|
854 | /* Combine OCR4CL and OCR4CH */ |
---|
855 | #define OCR4C _SFR_MEM16(0xAC) |
---|
856 | |
---|
857 | #define OCR4CL _SFR_MEM8(0xAC) |
---|
858 | #define OCR4CH _SFR_MEM8(0xAD) |
---|
859 | |
---|
860 | /* Reserved [0xAE..0xAF] */ |
---|
861 | |
---|
862 | #define TCCR2A _SFR_MEM8(0xB0) |
---|
863 | #define COM2A1 7 |
---|
864 | #define COM2A0 6 |
---|
865 | #define COM2B1 5 |
---|
866 | #define COM2B0 4 |
---|
867 | #define WGM21 1 |
---|
868 | #define WGM20 0 |
---|
869 | |
---|
870 | #define TCCR2B _SFR_MEM8(0xB1) |
---|
871 | #define FOC2A 7 |
---|
872 | #define FOC2B 6 |
---|
873 | #define WGM22 3 |
---|
874 | #define CS22 2 |
---|
875 | #define CS21 1 |
---|
876 | #define CS20 0 |
---|
877 | |
---|
878 | #define TCNT2 _SFR_MEM8(0xB2) |
---|
879 | |
---|
880 | #define OCR2A _SFR_MEM8(0xB3) |
---|
881 | |
---|
882 | #define OCR2B _SFR_MEM8(0xB4) |
---|
883 | |
---|
884 | /* Reserved [0xB5] */ |
---|
885 | |
---|
886 | #define ASSR _SFR_MEM8(0xB6) |
---|
887 | #define EXCLK 6 |
---|
888 | #define AS2 5 |
---|
889 | #define TCN2UB 4 |
---|
890 | #define OCR2AUB 3 |
---|
891 | #define OCR2BUB 2 |
---|
892 | #define TCR2AUB 1 |
---|
893 | #define TCR2BUB 0 |
---|
894 | |
---|
895 | /* Reserved [0xB7] */ |
---|
896 | |
---|
897 | #define TWBR _SFR_MEM8(0xB8) |
---|
898 | |
---|
899 | #define TWSR _SFR_MEM8(0xB9) |
---|
900 | #define TWS7 7 |
---|
901 | #define TWS6 6 |
---|
902 | #define TWS5 5 |
---|
903 | #define TWS4 4 |
---|
904 | #define TWS3 3 |
---|
905 | #define TWPS1 1 |
---|
906 | #define TWPS0 0 |
---|
907 | |
---|
908 | #define TWAR _SFR_MEM8(0xBA) |
---|
909 | #define TWA6 7 |
---|
910 | #define TWA5 6 |
---|
911 | #define TWA4 5 |
---|
912 | #define TWA3 4 |
---|
913 | #define TWA2 3 |
---|
914 | #define TWA1 2 |
---|
915 | #define TWA0 1 |
---|
916 | #define TWGCE 0 |
---|
917 | |
---|
918 | #define TWDR _SFR_MEM8(0xBB) |
---|
919 | |
---|
920 | #define TWCR _SFR_MEM8(0xBC) |
---|
921 | #define TWINT 7 |
---|
922 | #define TWEA 6 |
---|
923 | #define TWSTA 5 |
---|
924 | #define TWSTO 4 |
---|
925 | #define TWWC 3 |
---|
926 | #define TWEN 2 |
---|
927 | #define TWIE 0 |
---|
928 | |
---|
929 | #define TWAMR _SFR_MEM8(0xBD) |
---|
930 | #define TWAM6 7 |
---|
931 | #define TWAM5 6 |
---|
932 | #define TWAM4 5 |
---|
933 | #define TWAM3 4 |
---|
934 | #define TWAM2 3 |
---|
935 | #define TWAM1 2 |
---|
936 | #define TWAM0 1 |
---|
937 | |
---|
938 | /* Reserved [0xBE..0xBF] */ |
---|
939 | |
---|
940 | #define UCSR0A _SFR_MEM8(0xC0) |
---|
941 | #define RXC0 7 |
---|
942 | #define TXC0 6 |
---|
943 | #define UDRE0 5 |
---|
944 | #define FE0 4 |
---|
945 | #define DOR0 3 |
---|
946 | #define UPE0 2 |
---|
947 | #define U2X0 1 |
---|
948 | #define MPCM0 0 |
---|
949 | |
---|
950 | #define UCSR0B _SFR_MEM8(0XC1) |
---|
951 | #define RXCIE0 7 |
---|
952 | #define TXCIE0 6 |
---|
953 | #define UDRIE0 5 |
---|
954 | #define RXEN0 4 |
---|
955 | #define TXEN0 3 |
---|
956 | #define UCSZ02 2 |
---|
957 | #define RXB80 1 |
---|
958 | #define TXB80 0 |
---|
959 | |
---|
960 | #define UCSR0C _SFR_MEM8(0xC2) |
---|
961 | #define UMSEL01 7 |
---|
962 | #define UMSEL00 6 |
---|
963 | #define UPM01 5 |
---|
964 | #define UPM00 4 |
---|
965 | #define USBS0 3 |
---|
966 | #define UCSZ01 2 |
---|
967 | #define UCSZ00 1 |
---|
968 | #define UCPOL0 0 |
---|
969 | |
---|
970 | /* Reserved [0xC3] */ |
---|
971 | |
---|
972 | /* Combine UBRR0L and UBRR0H */ |
---|
973 | #define UBRR0 _SFR_MEM16(0xC4) |
---|
974 | |
---|
975 | #define UBRR0L _SFR_MEM8(0xC4) |
---|
976 | #define UBRR0H _SFR_MEM8(0xC5) |
---|
977 | |
---|
978 | #define UDR0 _SFR_MEM8(0XC6) |
---|
979 | |
---|
980 | /* Reserved [0xC7] */ |
---|
981 | |
---|
982 | #define UCSR1A _SFR_MEM8(0xC8) |
---|
983 | #define RXC1 7 |
---|
984 | #define TXC1 6 |
---|
985 | #define UDRE1 5 |
---|
986 | #define FE1 4 |
---|
987 | #define DOR1 3 |
---|
988 | #define UPE1 2 |
---|
989 | #define U2X1 1 |
---|
990 | #define MPCM1 0 |
---|
991 | |
---|
992 | #define UCSR1B _SFR_MEM8(0XC9) |
---|
993 | #define RXCIE1 7 |
---|
994 | #define TXCIE1 6 |
---|
995 | #define UDRIE1 5 |
---|
996 | #define RXEN1 4 |
---|
997 | #define TXEN1 3 |
---|
998 | #define UCSZ12 2 |
---|
999 | #define RXB81 1 |
---|
1000 | #define TXB81 0 |
---|
1001 | |
---|
1002 | #define UCSR1C _SFR_MEM8(0xCA) |
---|
1003 | #define UMSEL11 7 |
---|
1004 | #define UMSEL10 6 |
---|
1005 | #define UPM11 5 |
---|
1006 | #define UPM10 4 |
---|
1007 | #define USBS1 3 |
---|
1008 | #define UCSZ11 2 |
---|
1009 | #define UCSZ10 1 |
---|
1010 | #define UCPOL1 0 |
---|
1011 | |
---|
1012 | /* Reserved [0xCB] */ |
---|
1013 | |
---|
1014 | /* Combine UBRR1L and UBRR1H */ |
---|
1015 | #define UBRR1 _SFR_MEM16(0xCC) |
---|
1016 | |
---|
1017 | #define UBRR1L _SFR_MEM8(0xCC) |
---|
1018 | #define UBRR1H _SFR_MEM8(0xCD) |
---|
1019 | |
---|
1020 | #define UDR1 _SFR_MEM8(0XCE) |
---|
1021 | |
---|
1022 | /* Reserved [0xCF] */ |
---|
1023 | |
---|
1024 | #if defined(__ATmegaxx0__) |
---|
1025 | |
---|
1026 | # define UCSR2A _SFR_MEM8(0xD0) |
---|
1027 | # define RXC2 7 |
---|
1028 | # define TXC2 6 |
---|
1029 | # define UDRE2 5 |
---|
1030 | # define FE2 4 |
---|
1031 | # define DOR2 3 |
---|
1032 | # define UPE2 2 |
---|
1033 | # define U2X2 1 |
---|
1034 | # define MPCM2 0 |
---|
1035 | |
---|
1036 | # define UCSR2B _SFR_MEM8(0XD1) |
---|
1037 | # define RXCIE2 7 |
---|
1038 | # define TXCIE2 6 |
---|
1039 | # define UDRIE2 5 |
---|
1040 | # define RXEN2 4 |
---|
1041 | # define TXEN2 3 |
---|
1042 | # define UCSZ22 2 |
---|
1043 | # define RXB82 1 |
---|
1044 | # define TXB82 0 |
---|
1045 | |
---|
1046 | # define UCSR2C _SFR_MEM8(0xD2) |
---|
1047 | # define UMSEL21 7 |
---|
1048 | # define UMSEL20 6 |
---|
1049 | # define UPM21 5 |
---|
1050 | # define UPM20 4 |
---|
1051 | # define USBS2 3 |
---|
1052 | # define UCSZ21 2 |
---|
1053 | # define UCSZ20 1 |
---|
1054 | # define UCPOL2 0 |
---|
1055 | |
---|
1056 | /* Reserved [0xD3] */ |
---|
1057 | |
---|
1058 | /* Combine UBRR2L and UBRR2H */ |
---|
1059 | # define UBRR2 _SFR_MEM16(0xD4) |
---|
1060 | |
---|
1061 | # define UBRR2L _SFR_MEM8(0xD4) |
---|
1062 | # define UBRR2H _SFR_MEM8(0xD5) |
---|
1063 | |
---|
1064 | # define UDR2 _SFR_MEM8(0XD6) |
---|
1065 | |
---|
1066 | #endif /* __ATmegaxx0__ */ |
---|
1067 | |
---|
1068 | /* Reserved [0xD7..0xFF] */ |
---|
1069 | |
---|
1070 | #if defined(__ATmegaxx0__) |
---|
1071 | |
---|
1072 | # define PINH _SFR_MEM8(0x100) |
---|
1073 | # define PINH7 7 |
---|
1074 | # define PINH6 6 |
---|
1075 | # define PINH5 5 |
---|
1076 | # define PINH4 4 |
---|
1077 | # define PINH3 3 |
---|
1078 | # define PINH2 2 |
---|
1079 | # define PINH1 1 |
---|
1080 | # define PINH0 0 |
---|
1081 | |
---|
1082 | # define DDRH _SFR_MEM8(0x101) |
---|
1083 | # define DDH7 7 |
---|
1084 | # define DDH6 6 |
---|
1085 | # define DDH5 5 |
---|
1086 | # define DDH4 4 |
---|
1087 | # define DDH3 3 |
---|
1088 | # define DDH2 2 |
---|
1089 | # define DDH1 1 |
---|
1090 | # define DDH0 0 |
---|
1091 | |
---|
1092 | # define PORTH _SFR_MEM8(0x102) |
---|
1093 | # define PH7 7 |
---|
1094 | # define PH6 6 |
---|
1095 | # define PH5 5 |
---|
1096 | # define PH4 4 |
---|
1097 | # define PH3 3 |
---|
1098 | # define PH2 2 |
---|
1099 | # define PH1 1 |
---|
1100 | # define PH0 0 |
---|
1101 | |
---|
1102 | # define PINJ _SFR_MEM8(0x103) |
---|
1103 | # define PINJ7 7 |
---|
1104 | # define PINJ6 6 |
---|
1105 | # define PINJ5 5 |
---|
1106 | # define PINJ4 4 |
---|
1107 | # define PINJ3 3 |
---|
1108 | # define PINJ2 2 |
---|
1109 | # define PINJ1 1 |
---|
1110 | # define PINJ0 0 |
---|
1111 | |
---|
1112 | # define DDRJ _SFR_MEM8(0x104) |
---|
1113 | # define DDJ7 7 |
---|
1114 | # define DDJ6 6 |
---|
1115 | # define DDJ5 5 |
---|
1116 | # define DDJ4 4 |
---|
1117 | # define DDJ3 3 |
---|
1118 | # define DDJ2 2 |
---|
1119 | # define DDJ1 1 |
---|
1120 | # define DDJ0 0 |
---|
1121 | |
---|
1122 | # define PORTJ _SFR_MEM8(0x105) |
---|
1123 | # define PJ7 7 |
---|
1124 | # define PJ6 6 |
---|
1125 | # define PJ5 5 |
---|
1126 | # define PJ4 4 |
---|
1127 | # define PJ3 3 |
---|
1128 | # define PJ2 2 |
---|
1129 | # define PJ1 1 |
---|
1130 | # define PJ0 0 |
---|
1131 | |
---|
1132 | # define PINK _SFR_MEM8(0x106) |
---|
1133 | # define PINK7 7 |
---|
1134 | # define PINK6 6 |
---|
1135 | # define PINK5 5 |
---|
1136 | # define PINK4 4 |
---|
1137 | # define PINK3 3 |
---|
1138 | # define PINK2 2 |
---|
1139 | # define PINK1 1 |
---|
1140 | # define PINK0 0 |
---|
1141 | |
---|
1142 | # define DDRK _SFR_MEM8(0x107) |
---|
1143 | # define DDK7 7 |
---|
1144 | # define DDK6 6 |
---|
1145 | # define DDK5 5 |
---|
1146 | # define DDK4 4 |
---|
1147 | # define DDK3 3 |
---|
1148 | # define DDK2 2 |
---|
1149 | # define DDK1 1 |
---|
1150 | # define DDK0 0 |
---|
1151 | |
---|
1152 | # define PORTK _SFR_MEM8(0x108) |
---|
1153 | # define PK7 7 |
---|
1154 | # define PK6 6 |
---|
1155 | # define PK5 5 |
---|
1156 | # define PK4 4 |
---|
1157 | # define PK3 3 |
---|
1158 | # define PK2 2 |
---|
1159 | # define PK1 1 |
---|
1160 | # define PK0 0 |
---|
1161 | |
---|
1162 | # define PINL _SFR_MEM8(0x109) |
---|
1163 | # define PINL7 7 |
---|
1164 | # define PINL6 6 |
---|
1165 | # define PINL5 5 |
---|
1166 | # define PINL4 4 |
---|
1167 | # define PINL3 3 |
---|
1168 | # define PINL2 2 |
---|
1169 | # define PINL1 1 |
---|
1170 | # define PINL0 0 |
---|
1171 | |
---|
1172 | # define DDRL _SFR_MEM8(0x10A) |
---|
1173 | # define DDL7 7 |
---|
1174 | # define DDL6 6 |
---|
1175 | # define DDL5 5 |
---|
1176 | # define DDL4 4 |
---|
1177 | # define DDL3 3 |
---|
1178 | # define DDL2 2 |
---|
1179 | # define DDL1 1 |
---|
1180 | # define DDL0 0 |
---|
1181 | |
---|
1182 | # define PORTL _SFR_MEM8(0x10B) |
---|
1183 | # define PL7 7 |
---|
1184 | # define PL6 6 |
---|
1185 | # define PL5 5 |
---|
1186 | # define PL4 4 |
---|
1187 | # define PL3 3 |
---|
1188 | # define PL2 2 |
---|
1189 | # define PL1 1 |
---|
1190 | # define PL0 0 |
---|
1191 | |
---|
1192 | #endif /* __ATmegaxx0__ */ |
---|
1193 | |
---|
1194 | /* Reserved [0x10C..0x11F] */ |
---|
1195 | |
---|
1196 | #define TCCR5A _SFR_MEM8(0x120) |
---|
1197 | #define COM5A1 7 |
---|
1198 | #define COM5A0 6 |
---|
1199 | #define COM5B1 5 |
---|
1200 | #define COM5B0 4 |
---|
1201 | #define COM5C1 3 |
---|
1202 | #define COM5C0 2 |
---|
1203 | #define WGM51 1 |
---|
1204 | #define WGM50 0 |
---|
1205 | |
---|
1206 | #define TCCR5B _SFR_MEM8(0x121) |
---|
1207 | #define ICNC5 7 |
---|
1208 | #define ICES5 6 |
---|
1209 | #define WGM53 4 |
---|
1210 | #define WGM52 3 |
---|
1211 | #define CS52 2 |
---|
1212 | #define CS51 1 |
---|
1213 | #define CS50 0 |
---|
1214 | |
---|
1215 | #define TCCR5C _SFR_MEM8(0x122) |
---|
1216 | #define FOC5A 7 |
---|
1217 | #define FOC5B 6 |
---|
1218 | #define FOC5C 5 |
---|
1219 | |
---|
1220 | /* Reserved [0x123] */ |
---|
1221 | |
---|
1222 | /* Combine TCNT5L and TCNT5H */ |
---|
1223 | #define TCNT5 _SFR_MEM16(0x124) |
---|
1224 | |
---|
1225 | #define TCNT5L _SFR_MEM8(0x124) |
---|
1226 | #define TCNT5H _SFR_MEM8(0x125) |
---|
1227 | |
---|
1228 | /* Combine ICR5L and ICR5H */ |
---|
1229 | #define ICR5 _SFR_MEM16(0x126) |
---|
1230 | |
---|
1231 | #define ICR5L _SFR_MEM8(0x126) |
---|
1232 | #define ICR5H _SFR_MEM8(0x127) |
---|
1233 | |
---|
1234 | /* Combine OCR5AL and OCR5AH */ |
---|
1235 | #define OCR5A _SFR_MEM16(0x128) |
---|
1236 | |
---|
1237 | #define OCR5AL _SFR_MEM8(0x128) |
---|
1238 | #define OCR5AH _SFR_MEM8(0x129) |
---|
1239 | |
---|
1240 | /* Combine OCR5BL and OCR5BH */ |
---|
1241 | #define OCR5B _SFR_MEM16(0x12A) |
---|
1242 | |
---|
1243 | #define OCR5BL _SFR_MEM8(0x12A) |
---|
1244 | #define OCR5BH _SFR_MEM8(0x12B) |
---|
1245 | |
---|
1246 | /* Combine OCR5CL and OCR5CH */ |
---|
1247 | #define OCR5C _SFR_MEM16(0x12C) |
---|
1248 | |
---|
1249 | #define OCR5CL _SFR_MEM8(0x12C) |
---|
1250 | #define OCR5CH _SFR_MEM8(0x12D) |
---|
1251 | |
---|
1252 | /* Reserved [0x12E..0x12F] */ |
---|
1253 | |
---|
1254 | #if defined(__ATmegaxx0__) |
---|
1255 | |
---|
1256 | # define UCSR3A _SFR_MEM8(0x130) |
---|
1257 | # define RXC3 7 |
---|
1258 | # define TXC3 6 |
---|
1259 | # define UDRE3 5 |
---|
1260 | # define FE3 4 |
---|
1261 | # define DOR3 3 |
---|
1262 | # define UPE3 2 |
---|
1263 | # define U2X3 1 |
---|
1264 | # define MPCM3 0 |
---|
1265 | |
---|
1266 | # define UCSR3B _SFR_MEM8(0X131) |
---|
1267 | # define RXCIE3 7 |
---|
1268 | # define TXCIE3 6 |
---|
1269 | # define UDRIE3 5 |
---|
1270 | # define RXEN3 4 |
---|
1271 | # define TXEN3 3 |
---|
1272 | # define UCSZ32 2 |
---|
1273 | # define RXB83 1 |
---|
1274 | # define TXB83 0 |
---|
1275 | |
---|
1276 | # define UCSR3C _SFR_MEM8(0x132) |
---|
1277 | # define UMSEL31 7 |
---|
1278 | # define UMSEL30 6 |
---|
1279 | # define UPM31 5 |
---|
1280 | # define UPM30 4 |
---|
1281 | # define USBS3 3 |
---|
1282 | # define UCSZ31 2 |
---|
1283 | # define UCSZ30 1 |
---|
1284 | # define UCPOL3 0 |
---|
1285 | |
---|
1286 | /* Reserved [0x133] */ |
---|
1287 | |
---|
1288 | /* Combine UBRR3L and UBRR3H */ |
---|
1289 | # define UBRR3 _SFR_MEM16(0x134) |
---|
1290 | |
---|
1291 | # define UBRR3L _SFR_MEM8(0x134) |
---|
1292 | # define UBRR3H _SFR_MEM8(0x135) |
---|
1293 | |
---|
1294 | # define UDR3 _SFR_MEM8(0X136) |
---|
1295 | |
---|
1296 | #endif /* __ATmegaxx0__ */ |
---|
1297 | |
---|
1298 | /* Reserved [0x137..1FF] */ |
---|
1299 | |
---|
1300 | /* Interrupt vectors */ |
---|
1301 | /* Vector 0 is the reset vector */ |
---|
1302 | /* External Interrupt Request 0 */ |
---|
1303 | #define INT0_vect _VECTOR(1) |
---|
1304 | #define SIG_INTERRUPT0 _VECTOR(1) |
---|
1305 | |
---|
1306 | /* External Interrupt Request 1 */ |
---|
1307 | #define INT1_vect _VECTOR(2) |
---|
1308 | #define SIG_INTERRUPT1 _VECTOR(2) |
---|
1309 | |
---|
1310 | /* External Interrupt Request 2 */ |
---|
1311 | #define INT2_vect _VECTOR(3) |
---|
1312 | #define SIG_INTERRUPT2 _VECTOR(3) |
---|
1313 | |
---|
1314 | /* External Interrupt Request 3 */ |
---|
1315 | #define INT3_vect _VECTOR(4) |
---|
1316 | #define SIG_INTERRUPT3 _VECTOR(4) |
---|
1317 | |
---|
1318 | /* External Interrupt Request 4 */ |
---|
1319 | #define INT4_vect _VECTOR(5) |
---|
1320 | #define SIG_INTERRUPT4 _VECTOR(5) |
---|
1321 | |
---|
1322 | /* External Interrupt Request 5 */ |
---|
1323 | #define INT5_vect _VECTOR(6) |
---|
1324 | #define SIG_INTERRUPT5 _VECTOR(6) |
---|
1325 | |
---|
1326 | /* External Interrupt Request 6 */ |
---|
1327 | #define INT6_vect _VECTOR(7) |
---|
1328 | #define SIG_INTERRUPT6 _VECTOR(7) |
---|
1329 | |
---|
1330 | /* External Interrupt Request 7 */ |
---|
1331 | #define INT7_vect _VECTOR(8) |
---|
1332 | #define SIG_INTERRUPT7 _VECTOR(8) |
---|
1333 | |
---|
1334 | /* Pin Change Interrupt Request 0 */ |
---|
1335 | #define PCINT0_vect _VECTOR(9) |
---|
1336 | #define SIG_PIN_CHANGE0 _VECTOR(9) |
---|
1337 | |
---|
1338 | /* Pin Change Interrupt Request 1 */ |
---|
1339 | #define PCINT1_vect _VECTOR(10) |
---|
1340 | #define SIG_PIN_CHANGE1 _VECTOR(10) |
---|
1341 | |
---|
1342 | #if defined(__ATmegaxx0__) |
---|
1343 | /* Pin Change Interrupt Request 2 */ |
---|
1344 | #define PCINT2_vect _VECTOR(11) |
---|
1345 | #define SIG_PIN_CHANGE2 _VECTOR(11) |
---|
1346 | |
---|
1347 | #endif /* __ATmegaxx0__ */ |
---|
1348 | |
---|
1349 | /* Watchdog Time-out Interrupt */ |
---|
1350 | #define WDT_vect _VECTOR(12) |
---|
1351 | #define SIG_WATCHDOG_TIMEOUT _VECTOR(12) |
---|
1352 | |
---|
1353 | /* Timer/Counter2 Compare Match A */ |
---|
1354 | #define TIMER2_COMPA_vect _VECTOR(13) |
---|
1355 | #define SIG_OUTPUT_COMPARE2A _VECTOR(13) |
---|
1356 | |
---|
1357 | /* Timer/Counter2 Compare Match B */ |
---|
1358 | #define TIMER2_COMPB_vect _VECTOR(14) |
---|
1359 | #define SIG_OUTPUT_COMPARE2B _VECTOR(14) |
---|
1360 | |
---|
1361 | /* Timer/Counter2 Overflow */ |
---|
1362 | #define TIMER2_OVF_vect _VECTOR(15) |
---|
1363 | #define SIG_OVERFLOW2 _VECTOR(15) |
---|
1364 | |
---|
1365 | /* Timer/Counter1 Capture Event */ |
---|
1366 | #define TIMER1_CAPT_vect _VECTOR(16) |
---|
1367 | #define SIG_INPUT_CAPTURE1 _VECTOR(16) |
---|
1368 | |
---|
1369 | /* Timer/Counter1 Compare Match A */ |
---|
1370 | #define TIMER1_COMPA_vect _VECTOR(17) |
---|
1371 | #define SIG_OUTPUT_COMPARE1A _VECTOR(17) |
---|
1372 | |
---|
1373 | /* Timer/Counter1 Compare Match B */ |
---|
1374 | #define TIMER1_COMPB_vect _VECTOR(18) |
---|
1375 | #define SIG_OUTPUT_COMPARE1B _VECTOR(18) |
---|
1376 | |
---|
1377 | /* Timer/Counter1 Compare Match C */ |
---|
1378 | #define TIMER1_COMPC_vect _VECTOR(19) |
---|
1379 | #define SIG_OUTPUT_COMPARE1C _VECTOR(19) |
---|
1380 | |
---|
1381 | /* Timer/Counter1 Overflow */ |
---|
1382 | #define TIMER1_OVF_vect _VECTOR(20) |
---|
1383 | #define SIG_OVERFLOW1 _VECTOR(20) |
---|
1384 | |
---|
1385 | /* Timer/Counter0 Compare Match A */ |
---|
1386 | #define TIMER0_COMPA_vect _VECTOR(21) |
---|
1387 | #define SIG_OUTPUT_COMPARE0A _VECTOR(21) |
---|
1388 | |
---|
1389 | /* Timer/Counter0 Compare Match B */ |
---|
1390 | #define TIMER0_COMPB_vect _VECTOR(22) |
---|
1391 | #define SIG_OUTPUT_COMPARE0B _VECTOR(22) |
---|
1392 | |
---|
1393 | /* Timer/Counter0 Overflow */ |
---|
1394 | #define TIMER0_OVF_vect _VECTOR(23) |
---|
1395 | #define SIG_OVERFLOW0 _VECTOR(23) |
---|
1396 | |
---|
1397 | /* SPI Serial Transfer Complete */ |
---|
1398 | #define SPI_STC_vect _VECTOR(24) |
---|
1399 | #define SIG_SPI _VECTOR(24) |
---|
1400 | |
---|
1401 | /* USART0, Rx Complete */ |
---|
1402 | #define USART0_RX_vect _VECTOR(25) |
---|
1403 | #define SIG_USART0_RECV _VECTOR(25) |
---|
1404 | |
---|
1405 | /* USART0 Data register Empty */ |
---|
1406 | #define USART0_UDRE_vect _VECTOR(26) |
---|
1407 | #define SIG_USART0_DATA _VECTOR(26) |
---|
1408 | |
---|
1409 | /* USART0, Tx Complete */ |
---|
1410 | #define USART0_TX_vect _VECTOR(27) |
---|
1411 | #define SIG_USART0_TRANS _VECTOR(27) |
---|
1412 | |
---|
1413 | /* Analog Comparator */ |
---|
1414 | #define ANALOG_COMP_vect _VECTOR(28) |
---|
1415 | #define SIG_COMPARATOR _VECTOR(28) |
---|
1416 | |
---|
1417 | /* ADC Conversion Complete */ |
---|
1418 | #define ADC_vect _VECTOR(29) |
---|
1419 | #define SIG_ADC _VECTOR(29) |
---|
1420 | |
---|
1421 | /* EEPROM Ready */ |
---|
1422 | #define EE_READY_vect _VECTOR(30) |
---|
1423 | #define SIG_EEPROM_READY _VECTOR(30) |
---|
1424 | |
---|
1425 | /* Timer/Counter3 Capture Event */ |
---|
1426 | #define TIMER3_CAPT_vect _VECTOR(31) |
---|
1427 | #define SIG_INPUT_CAPTURE3 _VECTOR(31) |
---|
1428 | |
---|
1429 | /* Timer/Counter3 Compare Match A */ |
---|
1430 | #define TIMER3_COMPA_vect _VECTOR(32) |
---|
1431 | #define SIG_OUTPUT_COMPARE3A _VECTOR(32) |
---|
1432 | |
---|
1433 | /* Timer/Counter3 Compare Match B */ |
---|
1434 | #define TIMER3_COMPB_vect _VECTOR(33) |
---|
1435 | #define SIG_OUTPUT_COMPARE3B _VECTOR(33) |
---|
1436 | |
---|
1437 | /* Timer/Counter3 Compare Match C */ |
---|
1438 | #define TIMER3_COMPC_vect _VECTOR(34) |
---|
1439 | #define SIG_OUTPUT_COMPARE3C _VECTOR(34) |
---|
1440 | |
---|
1441 | /* Timer/Counter3 Overflow */ |
---|
1442 | #define TIMER3_OVF_vect _VECTOR(35) |
---|
1443 | #define SIG_OVERFLOW3 _VECTOR(35) |
---|
1444 | |
---|
1445 | /* USART1, Rx Complete */ |
---|
1446 | #define USART1_RX_vect _VECTOR(36) |
---|
1447 | #define SIG_USART1_RECV _VECTOR(36) |
---|
1448 | |
---|
1449 | /* USART1 Data register Empty */ |
---|
1450 | #define USART1_UDRE_vect _VECTOR(37) |
---|
1451 | #define SIG_USART1_DATA _VECTOR(37) |
---|
1452 | |
---|
1453 | /* USART1, Tx Complete */ |
---|
1454 | #define USART1_TX_vect _VECTOR(38) |
---|
1455 | #define SIG_USART1_TRANS _VECTOR(38) |
---|
1456 | |
---|
1457 | /* 2-wire Serial Interface */ |
---|
1458 | #define TWI_vect _VECTOR(39) |
---|
1459 | #define SIG_2WIRE_SERIAL _VECTOR(39) |
---|
1460 | |
---|
1461 | /* Store Program Memory Read */ |
---|
1462 | #define SPM_READY_vect _VECTOR(40) |
---|
1463 | #define SIG_SPM_READY _VECTOR(40) |
---|
1464 | |
---|
1465 | #if defined(__ATmegaxx0__) |
---|
1466 | /* Timer/Counter4 Capture Event */ |
---|
1467 | #define TIMER4_CAPT_vect _VECTOR(41) |
---|
1468 | #define SIG_INPUT_CAPTURE4 _VECTOR(41) |
---|
1469 | |
---|
1470 | #endif /* __ATmegaxx0__ */ |
---|
1471 | |
---|
1472 | /* Timer/Counter4 Compare Match A */ |
---|
1473 | #define TIMER4_COMPA_vect _VECTOR(42) |
---|
1474 | #define SIG_OUTPUT_COMPARE4A _VECTOR(42) |
---|
1475 | |
---|
1476 | /* Timer/Counter4 Compare Match B */ |
---|
1477 | #define TIMER4_COMPB_vect _VECTOR(43) |
---|
1478 | #define SIG_OUTPUT_COMPARE4B _VECTOR(43) |
---|
1479 | |
---|
1480 | /* Timer/Counter4 Compare Match C */ |
---|
1481 | #define TIMER4_COMPC_vect _VECTOR(44) |
---|
1482 | #define SIG_OUTPUT_COMPARE4C _VECTOR(44) |
---|
1483 | |
---|
1484 | /* Timer/Counter4 Overflow */ |
---|
1485 | #define TIMER4_OVF_vect _VECTOR(45) |
---|
1486 | #define SIG_OVERFLOW4 _VECTOR(45) |
---|
1487 | |
---|
1488 | #if defined(__ATmegaxx0__) |
---|
1489 | /* Timer/Counter5 Capture Event */ |
---|
1490 | #define TIMER5_CAPT_vect _VECTOR(46) |
---|
1491 | #define SIG_INPUT_CAPTURE5 _VECTOR(46) |
---|
1492 | |
---|
1493 | #endif /* __ATmegaxx0__ */ |
---|
1494 | |
---|
1495 | /* Timer/Counter5 Compare Match A */ |
---|
1496 | #define TIMER5_COMPA_vect _VECTOR(47) |
---|
1497 | #define SIG_OUTPUT_COMPARE5A _VECTOR(47) |
---|
1498 | |
---|
1499 | /* Timer/Counter5 Compare Match B */ |
---|
1500 | #define TIMER5_COMPB_vect _VECTOR(48) |
---|
1501 | #define SIG_OUTPUT_COMPARE5B _VECTOR(48) |
---|
1502 | |
---|
1503 | /* Timer/Counter5 Compare Match C */ |
---|
1504 | #define TIMER5_COMPC_vect _VECTOR(49) |
---|
1505 | #define SIG_OUTPUT_COMPARE5C _VECTOR(49) |
---|
1506 | |
---|
1507 | /* Timer/Counter5 Overflow */ |
---|
1508 | #define TIMER5_OVF_vect _VECTOR(50) |
---|
1509 | #define SIG_OVERFLOW5 _VECTOR(50) |
---|
1510 | |
---|
1511 | #if defined(__ATmegaxx1__) |
---|
1512 | |
---|
1513 | # define _VECTORS_SIZE 204 |
---|
1514 | |
---|
1515 | #else |
---|
1516 | |
---|
1517 | /* USART2, Rx Complete */ |
---|
1518 | #define USART2_RX_vect _VECTOR(51) |
---|
1519 | #define SIG_USART2_RECV _VECTOR(51) |
---|
1520 | |
---|
1521 | /* USART2 Data register Empty */ |
---|
1522 | #define USART2_UDRE_vect _VECTOR(52) |
---|
1523 | #define SIG_USART2_DATA _VECTOR(52) |
---|
1524 | |
---|
1525 | /* USART2, Tx Complete */ |
---|
1526 | #define USART2_TX_vect _VECTOR(53) |
---|
1527 | #define SIG_USART2_TRANS _VECTOR(53) |
---|
1528 | |
---|
1529 | /* USART3, Rx Complete */ |
---|
1530 | #define USART3_RX_vect _VECTOR(54) |
---|
1531 | #define SIG_USART3_RECV _VECTOR(54) |
---|
1532 | |
---|
1533 | /* USART3 Data register Empty */ |
---|
1534 | #define USART3_UDRE_vect _VECTOR(55) |
---|
1535 | #define SIG_USART3_DATA _VECTOR(55) |
---|
1536 | |
---|
1537 | /* USART3, Tx Complete */ |
---|
1538 | #define USART3_TX_vect _VECTOR(56) |
---|
1539 | #define SIG_USART3_TRANS _VECTOR(56) |
---|
1540 | |
---|
1541 | # define _VECTORS_SIZE 228 |
---|
1542 | |
---|
1543 | #endif /* __ATmegaxx1__ */ |
---|
1544 | |
---|
1545 | #if defined(__ATmegaxx0__) |
---|
1546 | # undef __ATmegaxx0__ |
---|
1547 | #endif |
---|
1548 | |
---|
1549 | #if defined(__ATmegaxx1__) |
---|
1550 | # undef __ATmegaxx1__ |
---|
1551 | #endif |
---|
1552 | |
---|
1553 | #endif /* _AVR_IOMXX0_1_H_ */ |
---|