1 | /* Copyright (c) 2007 Atmel Corporation |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. |
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30 | */ |
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31 | |
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32 | /* $Id$ */ |
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33 | |
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34 | /* avr/iom88p.h - definitions for ATmega88P. */ |
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35 | |
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36 | /* This file should only be included from <avr/io.h>, never directly. */ |
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37 | |
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38 | #ifndef _AVR_IO_H_ |
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39 | # error "Include <avr/io.h> instead of this file." |
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40 | #endif |
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41 | |
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42 | #ifndef _AVR_IOXXX_H_ |
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43 | # define _AVR_IOXXX_H_ "iom88p.h" |
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44 | #else |
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45 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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46 | #endif |
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47 | |
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48 | |
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49 | #ifndef _AVR_IOM88P_H_ |
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50 | #define _AVR_IOM88P_H_ 1 |
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51 | |
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52 | /* Registers and associated bit numbers */ |
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53 | |
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54 | #define PINB _SFR_IO8(0x03) |
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55 | #define PINB0 0 |
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56 | #define PINB1 1 |
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57 | #define PINB2 2 |
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58 | #define PINB3 3 |
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59 | #define PINB4 4 |
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60 | #define PINB5 5 |
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61 | #define PINB6 6 |
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62 | #define PINB7 7 |
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63 | |
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64 | #define DDRB _SFR_IO8(0x04) |
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65 | #define DDB0 0 |
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66 | #define DDB1 1 |
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67 | #define DDB2 2 |
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68 | #define DDB3 3 |
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69 | #define DDB4 4 |
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70 | #define DDB5 5 |
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71 | #define DDB6 6 |
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72 | #define DDB7 7 |
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73 | |
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74 | #define PORTB _SFR_IO8(0x05) |
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75 | #define PORTB0 0 |
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76 | #define PORTB1 1 |
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77 | #define PORTB2 2 |
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78 | #define PORTB3 3 |
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79 | #define PORTB4 4 |
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80 | #define PORTB5 5 |
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81 | #define PORTB6 6 |
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82 | #define PORTB7 7 |
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83 | |
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84 | #define PINC _SFR_IO8(0x06) |
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85 | #define PINC0 0 |
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86 | #define PINC1 1 |
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87 | #define PINC2 2 |
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88 | #define PINC3 3 |
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89 | #define PINC4 4 |
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90 | #define PINC5 5 |
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91 | #define PINC6 6 |
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92 | |
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93 | #define DDRC _SFR_IO8(0x07) |
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94 | #define DDC0 0 |
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95 | #define DDC1 1 |
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96 | #define DDC2 2 |
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97 | #define DDC3 3 |
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98 | #define DDC4 4 |
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99 | #define DDC5 5 |
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100 | #define DDC6 6 |
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101 | |
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102 | #define PORTC _SFR_IO8(0x08) |
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103 | #define PORTC0 0 |
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104 | #define PORTC1 1 |
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105 | #define PORTC2 2 |
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106 | #define PORTC3 3 |
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107 | #define PORTC4 4 |
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108 | #define PORTC5 5 |
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109 | #define PORTC6 6 |
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110 | |
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111 | #define PIND _SFR_IO8(0x09) |
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112 | #define PIND0 0 |
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113 | #define PIND1 1 |
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114 | #define PIND2 2 |
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115 | #define PIND3 3 |
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116 | #define PIND4 4 |
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117 | #define PIND5 5 |
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118 | #define PIND6 6 |
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119 | #define PIND7 7 |
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120 | |
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121 | #define DDRD _SFR_IO8(0x0A) |
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122 | #define DDD0 0 |
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123 | #define DDD1 1 |
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124 | #define DDD2 2 |
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125 | #define DDD3 3 |
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126 | #define DDD4 4 |
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127 | #define DDD5 5 |
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128 | #define DDD6 6 |
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129 | #define DDD7 7 |
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130 | |
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131 | #define PORTD _SFR_IO8(0x0B) |
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132 | #define PORTD0 0 |
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133 | #define PORTD1 1 |
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134 | #define PORTD2 2 |
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135 | #define PORTD3 3 |
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136 | #define PORTD4 4 |
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137 | #define PORTD5 5 |
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138 | #define PORTD6 6 |
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139 | #define PORTD7 7 |
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140 | |
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141 | #define TIFR0 _SFR_IO8(0x15) |
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142 | #define TOV0 0 |
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143 | #define OCF0A 1 |
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144 | #define OCF0B 2 |
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145 | |
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146 | #define TIFR1 _SFR_IO8(0x16) |
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147 | #define TOV1 0 |
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148 | #define OCF1A 1 |
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149 | #define OCF1B 2 |
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150 | #define ICF1 5 |
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151 | |
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152 | #define TIFR2 _SFR_IO8(0x17) |
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153 | #define TOV2 0 |
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154 | #define OCF2A 1 |
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155 | #define OCF2B 2 |
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156 | |
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157 | #define PCIFR _SFR_IO8(0x1B) |
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158 | #define PCIF0 0 |
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159 | #define PCIF1 1 |
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160 | #define PCIF2 2 |
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161 | |
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162 | #define EIFR _SFR_IO8(0x1C) |
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163 | #define INTF0 0 |
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164 | #define INTF1 1 |
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165 | |
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166 | #define EIMSK _SFR_IO8(0x1D) |
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167 | #define INT0 0 |
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168 | #define INT1 1 |
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169 | |
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170 | #define GPIOR0 _SFR_IO8(0x1E) |
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171 | #define GPIOR00 0 |
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172 | #define GPIOR01 1 |
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173 | #define GPIOR02 2 |
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174 | #define GPIOR03 3 |
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175 | #define GPIOR04 4 |
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176 | #define GPIOR05 5 |
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177 | #define GPIOR06 6 |
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178 | #define GPIOR07 7 |
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179 | |
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180 | #define EECR _SFR_IO8(0x1F) |
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181 | #define EERE 0 |
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182 | #define EEPE 1 |
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183 | #define EEMPE 2 |
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184 | #define EERIE 3 |
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185 | #define EEPM0 4 |
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186 | #define EEPM1 5 |
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187 | |
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188 | #define EEDR _SFR_IO8(0x20) |
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189 | #define EEDR0 0 |
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190 | #define EEDR1 1 |
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191 | #define EEDR2 2 |
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192 | #define EEDR3 3 |
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193 | #define EEDR4 4 |
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194 | #define EEDR5 5 |
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195 | #define EEDR6 6 |
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196 | #define EEDR7 7 |
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197 | |
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198 | #define EEAR _SFR_IO16(0x21) |
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199 | |
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200 | #define EEARL _SFR_IO8(0x21) |
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201 | #define EEAR0 0 |
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202 | #define EEAR1 1 |
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203 | #define EEAR2 2 |
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204 | #define EEAR3 3 |
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205 | #define EEAR4 4 |
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206 | #define EEAR5 5 |
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207 | #define EEAR6 6 |
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208 | #define EEAR7 7 |
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209 | |
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210 | #define EEARH _SFR_IO8(0x22) |
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211 | #define EEAR8 0 |
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212 | |
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213 | #define EEPROM_REG_LOCATIONS 1F2021 |
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214 | |
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215 | #define GTCCR _SFR_IO8(0x23) |
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216 | #define PSRSYNC 0 |
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217 | #define PSRASY 1 |
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218 | #define TSM 7 |
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219 | |
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220 | #define TCCR0A _SFR_IO8(0x24) |
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221 | #define WGM00 0 |
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222 | #define WGM01 1 |
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223 | #define COM0B0 4 |
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224 | #define COM0B1 5 |
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225 | #define COM0A0 6 |
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226 | #define COM0A1 7 |
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227 | |
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228 | #define TCCR0B _SFR_IO8(0x25) |
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229 | #define CS00 0 |
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230 | #define CS01 1 |
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231 | #define CS02 2 |
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232 | #define WGM02 3 |
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233 | #define FOC0B 6 |
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234 | #define FOC0A 7 |
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235 | |
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236 | #define TCNT0 _SFR_IO8(0x26) |
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237 | #define TCNT0_0 0 |
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238 | #define TCNT0_1 1 |
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239 | #define TCNT0_2 2 |
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240 | #define TCNT0_3 3 |
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241 | #define TCNT0_4 4 |
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242 | #define TCNT0_5 5 |
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243 | #define TCNT0_6 6 |
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244 | #define TCNT0_7 7 |
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245 | |
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246 | #define OCR0A _SFR_IO8(0x27) |
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247 | #define OCR0A_0 0 |
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248 | #define OCR0A_1 1 |
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249 | #define OCR0A_2 2 |
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250 | #define OCR0A_3 3 |
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251 | #define OCR0A_4 4 |
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252 | #define OCR0A_5 5 |
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253 | #define OCR0A_6 6 |
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254 | #define OCR0A_7 7 |
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255 | |
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256 | #define OCR0B _SFR_IO8(0x28) |
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257 | #define OCR0B_0 0 |
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258 | #define OCR0B_1 1 |
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259 | #define OCR0B_2 2 |
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260 | #define OCR0B_3 3 |
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261 | #define OCR0B_4 4 |
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262 | #define OCR0B_5 5 |
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263 | #define OCR0B_6 6 |
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264 | #define OCR0B_7 7 |
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265 | |
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266 | #define GPIOR1 _SFR_IO8(0x2A) |
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267 | #define GPIOR10 0 |
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268 | #define GPIOR11 1 |
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269 | #define GPIOR12 2 |
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270 | #define GPIOR13 3 |
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271 | #define GPIOR14 4 |
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272 | #define GPIOR15 5 |
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273 | #define GPIOR16 6 |
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274 | #define GPIOR17 7 |
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275 | |
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276 | #define GPIOR2 _SFR_IO8(0x2B) |
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277 | #define GPIOR20 0 |
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278 | #define GPIOR21 1 |
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279 | #define GPIOR22 2 |
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280 | #define GPIOR23 3 |
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281 | #define GPIOR24 4 |
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282 | #define GPIOR25 5 |
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283 | #define GPIOR26 6 |
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284 | #define GPIOR27 7 |
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285 | |
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286 | #define SPCR _SFR_IO8(0x2C) |
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287 | #define SPR0 0 |
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288 | #define SPR1 1 |
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289 | #define CPHA 2 |
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290 | #define CPOL 3 |
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291 | #define MSTR 4 |
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292 | #define DORD 5 |
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293 | #define SPE 6 |
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294 | #define SPIE 7 |
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295 | |
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296 | #define SPSR _SFR_IO8(0x2D) |
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297 | #define SPI2X 0 |
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298 | #define WCOL 6 |
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299 | #define SPIF 7 |
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300 | |
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301 | #define SPDR _SFR_IO8(0x2E) |
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302 | #define SPDR0 0 |
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303 | #define SPDR1 1 |
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304 | #define SPDR2 2 |
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305 | #define SPDR3 3 |
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306 | #define SPDR4 4 |
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307 | #define SPDR5 5 |
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308 | #define SPDR6 6 |
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309 | #define SPDR7 7 |
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310 | |
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311 | #define ACSR _SFR_IO8(0x30) |
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312 | #define ACIS0 0 |
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313 | #define ACIS1 1 |
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314 | #define ACIC 2 |
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315 | #define ACIE 3 |
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316 | #define ACI 4 |
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317 | #define ACO 5 |
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318 | #define ACBG 6 |
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319 | #define ACD 7 |
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320 | |
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321 | #define SMCR _SFR_IO8(0x33) |
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322 | #define SE 0 |
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323 | #define SM0 1 |
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324 | #define SM1 2 |
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325 | #define SM2 3 |
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326 | |
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327 | #define MCUSR _SFR_IO8(0x34) |
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328 | #define PORF 0 |
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329 | #define EXTRF 1 |
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330 | #define BORF 2 |
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331 | #define WDRF 3 |
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332 | |
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333 | #define MCUCR _SFR_IO8(0x35) |
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334 | #define IVCE 0 |
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335 | #define IVSEL 1 |
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336 | #define PUD 4 |
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337 | #define BODSE 5 |
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338 | #define BODS 6 |
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339 | |
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340 | #define SPMCSR _SFR_IO8(0x37) |
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341 | #define SELFPRGEN 0 |
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342 | #define PGERS 1 |
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343 | #define PGWRT 2 |
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344 | #define BLBSET 3 |
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345 | #define RWWSRE 4 |
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346 | #define RWWSB 6 |
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347 | #define SPMIE 7 |
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348 | |
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349 | #define WDTCSR _SFR_MEM8(0x60) |
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350 | #define WDP0 0 |
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351 | #define WDP1 1 |
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352 | #define WDP2 2 |
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353 | #define WDE 3 |
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354 | #define WDCE 4 |
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355 | #define WDP3 5 |
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356 | #define WDIE 6 |
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357 | #define WDIF 7 |
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358 | |
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359 | #define CLKPR _SFR_MEM8(0x61) |
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360 | #define CLKPS0 0 |
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361 | #define CLKPS1 1 |
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362 | #define CLKPS2 2 |
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363 | #define CLKPS3 3 |
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364 | #define CLKPCE 7 |
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365 | |
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366 | #define PRR _SFR_MEM8(0x64) |
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367 | #define PRADC 0 |
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368 | #define PRUSART0 1 |
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369 | #define PRSPI 2 |
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370 | #define PRTIM1 3 |
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371 | #define PRTIM0 5 |
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372 | #define PRTIM2 6 |
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373 | #define PRTWI 7 |
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374 | |
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375 | #define OSCCAL _SFR_MEM8(0x66) |
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376 | #define CAL0 0 |
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377 | #define CAL1 1 |
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378 | #define CAL2 2 |
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379 | #define CAL3 3 |
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380 | #define CAL4 4 |
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381 | #define CAL5 5 |
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382 | #define CAL6 6 |
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383 | #define CAL7 7 |
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384 | |
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385 | #define PCICR _SFR_MEM8(0x68) |
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386 | #define PCIE0 0 |
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387 | #define PCIE1 1 |
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388 | #define PCIE2 2 |
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389 | |
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390 | #define EICRA _SFR_MEM8(0x69) |
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391 | #define ISC00 0 |
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392 | #define ISC01 1 |
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393 | #define ISC10 2 |
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394 | #define ISC11 3 |
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395 | |
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396 | #define PCMSK0 _SFR_MEM8(0x6B) |
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397 | #define PCINT0 0 |
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398 | #define PCINT1 1 |
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399 | #define PCINT2 2 |
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400 | #define PCINT3 3 |
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401 | #define PCINT4 4 |
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402 | #define PCINT5 5 |
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403 | #define PCINT6 6 |
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404 | #define PCINT7 7 |
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405 | |
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406 | #define PCMSK1 _SFR_MEM8(0x6C) |
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407 | #define PCINT8 0 |
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408 | #define PCINT9 1 |
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409 | #define PCINT10 2 |
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410 | #define PCINT11 3 |
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411 | #define PCINT12 4 |
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412 | #define PCINT13 5 |
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413 | #define PCINT14 6 |
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414 | |
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415 | #define PCMSK2 _SFR_MEM8(0x6D) |
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416 | #define PCINT16 0 |
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417 | #define PCINT17 1 |
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418 | #define PCINT18 2 |
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419 | #define PCINT19 3 |
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420 | #define PCINT20 4 |
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421 | #define PCINT21 5 |
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422 | #define PCINT22 6 |
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423 | #define PCINT23 7 |
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424 | |
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425 | #define TIMSK0 _SFR_MEM8(0x6E) |
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426 | #define TOIE0 0 |
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427 | #define OCIE0A 1 |
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428 | #define OCIE0B 2 |
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429 | |
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430 | #define TIMSK1 _SFR_MEM8(0x6F) |
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431 | #define TOIE1 0 |
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432 | #define OCIE1A 1 |
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433 | #define OCIE1B 2 |
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434 | #define ICIE1 5 |
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435 | |
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436 | #define TIMSK2 _SFR_MEM8(0x70) |
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437 | #define TOIE2 0 |
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438 | #define OCIE2A 1 |
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439 | #define OCIE2B 2 |
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440 | |
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441 | #ifndef __ASSEMBLER__ |
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442 | #define ADC _SFR_MEM16(0x78) |
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443 | #endif |
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444 | #define ADCW _SFR_MEM16(0x78) |
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445 | |
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446 | #define ADCL _SFR_MEM8(0x78) |
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447 | #define ADCL0 0 |
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448 | #define ADCL1 1 |
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449 | #define ADCL2 2 |
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450 | #define ADCL3 3 |
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451 | #define ADCL4 4 |
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452 | #define ADCL5 5 |
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453 | #define ADCL6 6 |
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454 | #define ADCL7 7 |
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455 | |
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456 | #define ADCH _SFR_MEM8(0x79) |
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457 | #define ADCH0 0 |
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458 | #define ADCH1 1 |
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459 | #define ADCH2 2 |
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460 | #define ADCH3 3 |
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461 | #define ADCH4 4 |
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462 | #define ADCH5 5 |
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463 | #define ADCH6 6 |
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464 | #define ADCH7 7 |
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465 | |
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466 | #define ADCSRA _SFR_MEM8(0x7A) |
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467 | #define ADPS0 0 |
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468 | #define ADPS1 1 |
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469 | #define ADPS2 2 |
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470 | #define ADIE 3 |
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471 | #define ADIF 4 |
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472 | #define ADATE 5 |
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473 | #define ADSC 6 |
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474 | #define ADEN 7 |
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475 | |
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476 | #define ADCSRB _SFR_MEM8(0x7B) |
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477 | #define ADTS0 0 |
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478 | #define ADTS1 1 |
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479 | #define ADTS2 2 |
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480 | #define ACME 6 |
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481 | |
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482 | #define ADMUX _SFR_MEM8(0x7C) |
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483 | #define MUX0 0 |
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484 | #define MUX1 1 |
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485 | #define MUX2 2 |
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486 | #define MUX3 3 |
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487 | #define ADLAR 5 |
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488 | #define REFS0 6 |
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489 | #define REFS1 7 |
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490 | |
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491 | #define DIDR0 _SFR_MEM8(0x7E) |
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492 | #define ADC0D 0 |
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493 | #define ADC1D 1 |
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494 | #define ADC2D 2 |
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495 | #define ADC3D 3 |
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496 | #define ADC4D 4 |
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497 | #define ADC5D 5 |
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498 | |
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499 | #define DIDR1 _SFR_MEM8(0x7F) |
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500 | #define AIN0D 0 |
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501 | #define AIN1D 1 |
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502 | |
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503 | #define TCCR1A _SFR_MEM8(0x80) |
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504 | #define WGM10 0 |
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505 | #define WGM11 1 |
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506 | #define COM1B0 4 |
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507 | #define COM1B1 5 |
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508 | #define COM1A0 6 |
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509 | #define COM1A1 7 |
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510 | |
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511 | #define TCCR1B _SFR_MEM8(0x81) |
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512 | #define CS10 0 |
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513 | #define CS11 1 |
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514 | #define CS12 2 |
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515 | #define WGM12 3 |
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516 | #define WGM13 4 |
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517 | #define ICES1 6 |
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518 | #define ICNC1 7 |
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519 | |
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520 | #define TCCR1C _SFR_MEM8(0x82) |
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521 | #define FOC1B 6 |
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522 | #define FOC1A 7 |
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523 | |
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524 | #define TCNT1 _SFR_MEM16(0x84) |
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525 | |
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526 | #define TCNT1L _SFR_MEM8(0x84) |
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527 | #define TCNT1L0 0 |
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528 | #define TCNT1L1 1 |
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529 | #define TCNT1L2 2 |
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530 | #define TCNT1L3 3 |
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531 | #define TCNT1L4 4 |
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532 | #define TCNT1L5 5 |
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533 | #define TCNT1L6 6 |
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534 | #define TCNT1L7 7 |
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535 | |
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536 | #define TCNT1H _SFR_MEM8(0x85) |
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537 | #define TCNT1H0 0 |
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538 | #define TCNT1H1 1 |
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539 | #define TCNT1H2 2 |
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540 | #define TCNT1H3 3 |
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541 | #define TCNT1H4 4 |
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542 | #define TCNT1H5 5 |
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543 | #define TCNT1H6 6 |
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544 | #define TCNT1H7 7 |
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545 | |
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546 | #define ICR1 _SFR_MEM16(0x86) |
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547 | |
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548 | #define ICR1L _SFR_MEM8(0x86) |
---|
549 | #define ICR1L0 0 |
---|
550 | #define ICR1L1 1 |
---|
551 | #define ICR1L2 2 |
---|
552 | #define ICR1L3 3 |
---|
553 | #define ICR1L4 4 |
---|
554 | #define ICR1L5 5 |
---|
555 | #define ICR1L6 6 |
---|
556 | #define ICR1L7 7 |
---|
557 | |
---|
558 | #define ICR1H _SFR_MEM8(0x87) |
---|
559 | #define ICR1H0 0 |
---|
560 | #define ICR1H1 1 |
---|
561 | #define ICR1H2 2 |
---|
562 | #define ICR1H3 3 |
---|
563 | #define ICR1H4 4 |
---|
564 | #define ICR1H5 5 |
---|
565 | #define ICR1H6 6 |
---|
566 | #define ICR1H7 7 |
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567 | |
---|
568 | #define OCR1A _SFR_MEM16(0x88) |
---|
569 | |
---|
570 | #define OCR1AL _SFR_MEM8(0x88) |
---|
571 | #define OCR1AL0 0 |
---|
572 | #define OCR1AL1 1 |
---|
573 | #define OCR1AL2 2 |
---|
574 | #define OCR1AL3 3 |
---|
575 | #define OCR1AL4 4 |
---|
576 | #define OCR1AL5 5 |
---|
577 | #define OCR1AL6 6 |
---|
578 | #define OCR1AL7 7 |
---|
579 | |
---|
580 | #define OCR1AH _SFR_MEM8(0x89) |
---|
581 | #define OCR1AH0 0 |
---|
582 | #define OCR1AH1 1 |
---|
583 | #define OCR1AH2 2 |
---|
584 | #define OCR1AH3 3 |
---|
585 | #define OCR1AH4 4 |
---|
586 | #define OCR1AH5 5 |
---|
587 | #define OCR1AH6 6 |
---|
588 | #define OCR1AH7 7 |
---|
589 | |
---|
590 | #define OCR1B _SFR_MEM16(0x8A) |
---|
591 | |
---|
592 | #define OCR1BL _SFR_MEM8(0x8A) |
---|
593 | #define OCR1BL0 0 |
---|
594 | #define OCR1BL1 1 |
---|
595 | #define OCR1BL2 2 |
---|
596 | #define OCR1BL3 3 |
---|
597 | #define OCR1BL4 4 |
---|
598 | #define OCR1BL5 5 |
---|
599 | #define OCR1BL6 6 |
---|
600 | #define OCR1BL7 7 |
---|
601 | |
---|
602 | #define OCR1BH _SFR_MEM8(0x8B) |
---|
603 | #define OCR1BH0 0 |
---|
604 | #define OCR1BH1 1 |
---|
605 | #define OCR1BH2 2 |
---|
606 | #define OCR1BH3 3 |
---|
607 | #define OCR1BH4 4 |
---|
608 | #define OCR1BH5 5 |
---|
609 | #define OCR1BH6 6 |
---|
610 | #define OCR1BH7 7 |
---|
611 | |
---|
612 | #define TCCR2A _SFR_MEM8(0xB0) |
---|
613 | #define WGM20 0 |
---|
614 | #define WGM21 1 |
---|
615 | #define COM2B0 4 |
---|
616 | #define COM2B1 5 |
---|
617 | #define COM2A0 6 |
---|
618 | #define COM2A1 7 |
---|
619 | |
---|
620 | #define TCCR2B _SFR_MEM8(0xB1) |
---|
621 | #define CS20 0 |
---|
622 | #define CS21 1 |
---|
623 | #define CS22 2 |
---|
624 | #define WGM22 3 |
---|
625 | #define FOC2B 6 |
---|
626 | #define FOC2A 7 |
---|
627 | |
---|
628 | #define TCNT2 _SFR_MEM8(0xB2) |
---|
629 | #define TCNT2_0 0 |
---|
630 | #define TCNT2_1 1 |
---|
631 | #define TCNT2_2 2 |
---|
632 | #define TCNT2_3 3 |
---|
633 | #define TCNT2_4 4 |
---|
634 | #define TCNT2_5 5 |
---|
635 | #define TCNT2_6 6 |
---|
636 | #define TCNT2_7 7 |
---|
637 | |
---|
638 | #define OCR2A _SFR_MEM8(0xB3) |
---|
639 | #define OCR2_0 0 |
---|
640 | #define OCR2_1 1 |
---|
641 | #define OCR2_2 2 |
---|
642 | #define OCR2_3 3 |
---|
643 | #define OCR2_4 4 |
---|
644 | #define OCR2_5 5 |
---|
645 | #define OCR2_6 6 |
---|
646 | #define OCR2_7 7 |
---|
647 | |
---|
648 | #define OCR2B _SFR_MEM8(0xB4) |
---|
649 | #define OCR2_0 0 |
---|
650 | #define OCR2_1 1 |
---|
651 | #define OCR2_2 2 |
---|
652 | #define OCR2_3 3 |
---|
653 | #define OCR2_4 4 |
---|
654 | #define OCR2_5 5 |
---|
655 | #define OCR2_6 6 |
---|
656 | #define OCR2_7 7 |
---|
657 | |
---|
658 | #define ASSR _SFR_MEM8(0xB6) |
---|
659 | #define TCR2BUB 0 |
---|
660 | #define TCR2AUB 1 |
---|
661 | #define OCR2BUB 2 |
---|
662 | #define OCR2AUB 3 |
---|
663 | #define TCN2UB 4 |
---|
664 | #define AS2 5 |
---|
665 | #define EXCLK 6 |
---|
666 | |
---|
667 | #define TWBR _SFR_MEM8(0xB8) |
---|
668 | #define TWBR0 0 |
---|
669 | #define TWBR1 1 |
---|
670 | #define TWBR2 2 |
---|
671 | #define TWBR3 3 |
---|
672 | #define TWBR4 4 |
---|
673 | #define TWBR5 5 |
---|
674 | #define TWBR6 6 |
---|
675 | #define TWBR7 7 |
---|
676 | |
---|
677 | #define TWSR _SFR_MEM8(0xB9) |
---|
678 | #define TWPS0 0 |
---|
679 | #define TWPS1 1 |
---|
680 | #define TWS3 3 |
---|
681 | #define TWS4 4 |
---|
682 | #define TWS5 5 |
---|
683 | #define TWS6 6 |
---|
684 | #define TWS7 7 |
---|
685 | |
---|
686 | #define TWAR _SFR_MEM8(0xBA) |
---|
687 | #define TWGCE 0 |
---|
688 | #define TWA0 1 |
---|
689 | #define TWA1 2 |
---|
690 | #define TWA2 3 |
---|
691 | #define TWA3 4 |
---|
692 | #define TWA4 5 |
---|
693 | #define TWA5 6 |
---|
694 | #define TWA6 7 |
---|
695 | |
---|
696 | #define TWDR _SFR_MEM8(0xBB) |
---|
697 | #define TWD0 0 |
---|
698 | #define TWD1 1 |
---|
699 | #define TWD2 2 |
---|
700 | #define TWD3 3 |
---|
701 | #define TWD4 4 |
---|
702 | #define TWD5 5 |
---|
703 | #define TWD6 6 |
---|
704 | #define TWD7 7 |
---|
705 | |
---|
706 | #define TWCR _SFR_MEM8(0xBC) |
---|
707 | #define TWIE 0 |
---|
708 | #define TWEN 2 |
---|
709 | #define TWWC 3 |
---|
710 | #define TWSTO 4 |
---|
711 | #define TWSTA 5 |
---|
712 | #define TWEA 6 |
---|
713 | #define TWINT 7 |
---|
714 | |
---|
715 | #define TWAMR _SFR_MEM8(0xBD) |
---|
716 | #define TWAM0 0 |
---|
717 | #define TWAM1 1 |
---|
718 | #define TWAM2 2 |
---|
719 | #define TWAM3 3 |
---|
720 | #define TWAM4 4 |
---|
721 | #define TWAM5 5 |
---|
722 | #define TWAM6 6 |
---|
723 | |
---|
724 | #define UCSR0A _SFR_MEM8(0xC0) |
---|
725 | #define MPCM0 0 |
---|
726 | #define U2X0 1 |
---|
727 | #define UPE0 2 |
---|
728 | #define DOR0 3 |
---|
729 | #define FE0 4 |
---|
730 | #define UDRE0 5 |
---|
731 | #define TXC0 6 |
---|
732 | #define RXC0 7 |
---|
733 | |
---|
734 | #define UCSR0B _SFR_MEM8(0xC1) |
---|
735 | #define TXB80 0 |
---|
736 | #define RXB80 1 |
---|
737 | #define UCSZ02 2 |
---|
738 | #define TXEN0 3 |
---|
739 | #define RXEN0 4 |
---|
740 | #define UDRIE0 5 |
---|
741 | #define TXCIE0 6 |
---|
742 | #define RXCIE0 7 |
---|
743 | |
---|
744 | #define UCSR0C _SFR_MEM8(0xC2) |
---|
745 | #define UCPOL0 0 |
---|
746 | #define UCSZ00 1 |
---|
747 | #define UCPHA0 1 |
---|
748 | #define UCSZ01 2 |
---|
749 | #define UDORD0 2 |
---|
750 | #define USBS0 3 |
---|
751 | #define UPM00 4 |
---|
752 | #define UPM01 5 |
---|
753 | #define UMSEL00 6 |
---|
754 | #define UMSEL01 7 |
---|
755 | |
---|
756 | #define UBRR0 _SFR_MEM16(0xC4) |
---|
757 | |
---|
758 | #define UBRR0L _SFR_MEM8(0xC4) |
---|
759 | #define UBRR0_0 0 |
---|
760 | #define UBRR0_1 1 |
---|
761 | #define UBRR0_2 2 |
---|
762 | #define UBRR0_3 3 |
---|
763 | #define UBRR0_4 4 |
---|
764 | #define UBRR0_5 5 |
---|
765 | #define UBRR0_6 6 |
---|
766 | #define UBRR0_7 7 |
---|
767 | |
---|
768 | #define UBRR0H _SFR_MEM8(0xC5) |
---|
769 | #define UBRR0_8 0 |
---|
770 | #define UBRR0_9 1 |
---|
771 | #define UBRR0_10 2 |
---|
772 | #define UBRR0_11 3 |
---|
773 | |
---|
774 | #define UDR0 _SFR_MEM8(0xC6) |
---|
775 | #define UDR0_0 0 |
---|
776 | #define UDR0_1 1 |
---|
777 | #define UDR0_2 2 |
---|
778 | #define UDR0_3 3 |
---|
779 | #define UDR0_4 4 |
---|
780 | #define UDR0_5 5 |
---|
781 | #define UDR0_6 6 |
---|
782 | #define UDR0_7 7 |
---|
783 | |
---|
784 | |
---|
785 | |
---|
786 | /* Interrupt Vectors */ |
---|
787 | /* Interrupt Vector 0 is the reset vector. */ |
---|
788 | #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ |
---|
789 | #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ |
---|
790 | #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ |
---|
791 | #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ |
---|
792 | #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ |
---|
793 | #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ |
---|
794 | #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ |
---|
795 | #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ |
---|
796 | #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ |
---|
797 | #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ |
---|
798 | #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ |
---|
799 | #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ |
---|
800 | #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ |
---|
801 | #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ |
---|
802 | #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ |
---|
803 | #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ |
---|
804 | #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ |
---|
805 | #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ |
---|
806 | #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ |
---|
807 | #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ |
---|
808 | #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ |
---|
809 | #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ |
---|
810 | #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ |
---|
811 | #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ |
---|
812 | #define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ |
---|
813 | |
---|
814 | #define _VECTORS_SIZE (26 * 2) |
---|
815 | |
---|
816 | |
---|
817 | |
---|
818 | /* Constants */ |
---|
819 | #define SPM_PAGESIZE 64 |
---|
820 | #define RAMEND 0x4FF /* Last On-Chip SRAM Location */ |
---|
821 | #define XRAMSIZE 0 |
---|
822 | #define XRAMEND RAMEND |
---|
823 | #define E2END 0x1FF |
---|
824 | #define E2PAGESIZE 4 |
---|
825 | #define FLASHEND 0x1FFF |
---|
826 | |
---|
827 | |
---|
828 | |
---|
829 | /* Fuses */ |
---|
830 | #define FUSE_MEMORY_SIZE 3 |
---|
831 | |
---|
832 | /* Low Fuse Byte */ |
---|
833 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ |
---|
834 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ |
---|
835 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ |
---|
836 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ |
---|
837 | #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ |
---|
838 | #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ |
---|
839 | #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ |
---|
840 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ |
---|
841 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
---|
842 | |
---|
843 | /* High Fuse Byte */ |
---|
844 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ |
---|
845 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ |
---|
846 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ |
---|
847 | #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ |
---|
848 | #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ |
---|
849 | #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ |
---|
850 | #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ |
---|
851 | #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ |
---|
852 | #define HFUSE_DEFAULT (FUSE_SPIEN) |
---|
853 | |
---|
854 | /* Extended Fuse Byte */ |
---|
855 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
---|
856 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
---|
857 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
---|
858 | #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) |
---|
859 | |
---|
860 | |
---|
861 | |
---|
862 | /* Lock Bits */ |
---|
863 | #define __LOCK_BITS_EXIST |
---|
864 | #define __BOOT_LOCK_BITS_0_EXIST |
---|
865 | #define __BOOT_LOCK_BITS_1_EXIST |
---|
866 | |
---|
867 | |
---|
868 | /* Signature */ |
---|
869 | #define SIGNATURE_0 0x1E |
---|
870 | #define SIGNATURE_1 0x93 |
---|
871 | #define SIGNATURE_2 0x0F |
---|
872 | |
---|
873 | |
---|
874 | #endif /* _AVR_IOM88P_H_ */ |
---|