1 | /* Copyright (c) 2002, Steinar Haugen |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* avr/iom8535.h - definitions for ATmega8535 */ |
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34 | |
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35 | #ifndef _AVR_IOM8535_H_ |
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36 | #define _AVR_IOM8535_H_ 1 |
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37 | |
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38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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39 | |
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40 | #ifndef _AVR_IO_H_ |
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41 | # error "Include <avr/io.h> instead of this file." |
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42 | #endif |
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43 | |
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44 | #ifndef _AVR_IOXXX_H_ |
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45 | # define _AVR_IOXXX_H_ "iom8535.h" |
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46 | #else |
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47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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48 | #endif |
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49 | |
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50 | /* I/O registers */ |
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51 | |
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52 | /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ |
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53 | #define TWBR _SFR_IO8(0x00) |
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54 | #define TWSR _SFR_IO8(0x01) |
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55 | #define TWAR _SFR_IO8(0x02) |
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56 | #define TWDR _SFR_IO8(0x03) |
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57 | |
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58 | /* ADC Data register */ |
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59 | #ifndef __ASSEMBLER__ |
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60 | #define ADC _SFR_IO16(0x04) |
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61 | #endif |
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62 | #define ADCW _SFR_IO16(0x04) |
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63 | #define ADCL _SFR_IO8(0x04) |
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64 | #define ADCH _SFR_IO8(0x05) |
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65 | |
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66 | /* ADC Control and Status Register */ |
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67 | #define ADCSRA _SFR_IO8(0x06) |
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68 | |
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69 | /* ADC MUX */ |
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70 | #define ADMUX _SFR_IO8(0x07) |
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71 | |
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72 | /* Analog Comparator Control and Status Register */ |
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73 | #define ACSR _SFR_IO8(0x08) |
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74 | |
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75 | /* USART Baud Rate Register */ |
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76 | #define UBRRL _SFR_IO8(0x09) |
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77 | |
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78 | /* USART Control and Status Register B */ |
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79 | #define UCSRB _SFR_IO8(0x0A) |
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80 | |
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81 | /* USART Control and Status Register A */ |
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82 | #define UCSRA _SFR_IO8(0x0B) |
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83 | |
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84 | /* USART I/O Data Register */ |
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85 | #define UDR _SFR_IO8(0x0C) |
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86 | |
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87 | /* SPI Control Register */ |
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88 | #define SPCR _SFR_IO8(0x0D) |
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89 | |
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90 | /* SPI Status Register */ |
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91 | #define SPSR _SFR_IO8(0x0E) |
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92 | |
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93 | /* SPI I/O Data Register */ |
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94 | #define SPDR _SFR_IO8(0x0F) |
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95 | |
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96 | /* Input Pins, Port D */ |
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97 | #define PIND _SFR_IO8(0x10) |
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98 | |
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99 | /* Data Direction Register, Port D */ |
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100 | #define DDRD _SFR_IO8(0x11) |
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101 | |
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102 | /* Data Register, Port D */ |
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103 | #define PORTD _SFR_IO8(0x12) |
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104 | |
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105 | /* Input Pins, Port C */ |
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106 | #define PINC _SFR_IO8(0x13) |
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107 | |
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108 | /* Data Direction Register, Port C */ |
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109 | #define DDRC _SFR_IO8(0x14) |
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110 | |
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111 | /* Data Register, Port C */ |
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112 | #define PORTC _SFR_IO8(0x15) |
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113 | |
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114 | /* Input Pins, Port B */ |
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115 | #define PINB _SFR_IO8(0x16) |
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116 | |
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117 | /* Data Direction Register, Port B */ |
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118 | #define DDRB _SFR_IO8(0x17) |
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119 | |
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120 | /* Data Register, Port B */ |
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121 | #define PORTB _SFR_IO8(0x18) |
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122 | |
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123 | /* Input Pins, Port A */ |
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124 | #define PINA _SFR_IO8(0x19) |
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125 | |
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126 | /* Data Direction Register, Port A */ |
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127 | #define DDRA _SFR_IO8(0x1A) |
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128 | |
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129 | /* Data Register, Port A */ |
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130 | #define PORTA _SFR_IO8(0x1B) |
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131 | |
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132 | /* EEPROM Control Register */ |
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133 | #define EECR _SFR_IO8(0x1C) |
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134 | |
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135 | /* EEPROM Data Register */ |
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136 | #define EEDR _SFR_IO8(0x1D) |
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137 | |
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138 | /* EEPROM Address Register */ |
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139 | #define EEAR _SFR_IO16(0x1E) |
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140 | #define EEARL _SFR_IO8(0x1E) |
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141 | #define EEARH _SFR_IO8(0x1F) |
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142 | |
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143 | /* USART Baud Rate Register HI */ |
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144 | /* USART Control and Status Register C */ |
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145 | #define UBRRH _SFR_IO8(0x20) |
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146 | #define UCSRC UBRRH |
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147 | |
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148 | /* Watchdog Timer Control Register */ |
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149 | #define WDTCR _SFR_IO8(0x21) |
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150 | |
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151 | /* Asynchronous mode Status Register */ |
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152 | #define ASSR _SFR_IO8(0x22) |
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153 | |
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154 | /* Timer/Counter2 Output Compare Register */ |
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155 | #define OCR2 _SFR_IO8(0x23) |
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156 | |
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157 | /* Timer/Counter 2 */ |
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158 | #define TCNT2 _SFR_IO8(0x24) |
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159 | |
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160 | /* Timer/Counter 2 Control Register */ |
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161 | #define TCCR2 _SFR_IO8(0x25) |
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162 | |
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163 | /* T/C 1 Input Capture Register */ |
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164 | #define ICR1 _SFR_IO16(0x26) |
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165 | #define ICR1L _SFR_IO8(0x26) |
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166 | #define ICR1H _SFR_IO8(0x27) |
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167 | |
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168 | /* Timer/Counter1 Output Compare Register B */ |
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169 | #define OCR1B _SFR_IO16(0x28) |
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170 | #define OCR1BL _SFR_IO8(0x28) |
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171 | #define OCR1BH _SFR_IO8(0x29) |
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172 | |
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173 | /* Timer/Counter1 Output Compare Register A */ |
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174 | #define OCR1A _SFR_IO16(0x2A) |
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175 | #define OCR1AL _SFR_IO8(0x2A) |
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176 | #define OCR1AH _SFR_IO8(0x2B) |
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177 | |
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178 | /* Timer/Counter 1 */ |
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179 | #define TCNT1 _SFR_IO16(0x2C) |
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180 | #define TCNT1L _SFR_IO8(0x2C) |
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181 | #define TCNT1H _SFR_IO8(0x2D) |
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182 | |
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183 | /* Timer/Counter 1 Control and Status Register */ |
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184 | #define TCCR1B _SFR_IO8(0x2E) |
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185 | |
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186 | /* Timer/Counter 1 Control Register */ |
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187 | #define TCCR1A _SFR_IO8(0x2F) |
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188 | |
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189 | /* Special Function IO Register */ |
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190 | #define SFIOR _SFR_IO8(0x30) |
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191 | |
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192 | /* Oscillator Calibration Register */ |
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193 | #define OSCCAL _SFR_IO8(0x31) |
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194 | |
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195 | /* Timer/Counter 0 */ |
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196 | #define TCNT0 _SFR_IO8(0x32) |
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197 | |
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198 | /* Timer/Counter 0 Control Register */ |
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199 | #define TCCR0 _SFR_IO8(0x33) |
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200 | |
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201 | /* MCU Control and Status Register */ |
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202 | #define MCUCSR _SFR_IO8(0x34) |
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203 | |
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204 | /* MCU Control Register */ |
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205 | #define MCUCR _SFR_IO8(0x35) |
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206 | |
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207 | /* TWI Control Register */ |
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208 | #define TWCR _SFR_IO8(0x36) |
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209 | |
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210 | /* Store Program Memory Control Register */ |
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211 | #define SPMCR _SFR_IO8(0x37) |
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212 | |
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213 | /* Timer/Counter Interrupt Flag register */ |
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214 | #define TIFR _SFR_IO8(0x38) |
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215 | |
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216 | /* Timer/Counter Interrupt MaSK register */ |
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217 | #define TIMSK _SFR_IO8(0x39) |
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218 | |
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219 | /* General Interrupt Flag Register */ |
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220 | #define GIFR _SFR_IO8(0x3A) |
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221 | |
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222 | /* General Interrupt MaSK register */ |
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223 | #define GICR _SFR_IO8(0x3B) |
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224 | |
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225 | /* Timer/Counter 0 Output Compare Register */ |
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226 | #define OCR0 _SFR_IO8(0x3C) |
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227 | |
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228 | /* 0x3D..0x3E SP */ |
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229 | |
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230 | /* 0x3F SREG */ |
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231 | |
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232 | /* Interrupt vectors */ |
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233 | |
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234 | /* External Interrupt 0 */ |
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235 | #define INT0_vect _VECTOR(1) |
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236 | #define SIG_INTERRUPT0 _VECTOR(1) |
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237 | |
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238 | /* External Interrupt 1 */ |
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239 | #define INT1_vect _VECTOR(2) |
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240 | #define SIG_INTERRUPT1 _VECTOR(2) |
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241 | |
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242 | /* Timer/Counter2 Compare Match */ |
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243 | #define TIMER2_COMP_vect _VECTOR(3) |
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244 | #define SIG_OUTPUT_COMPARE2 _VECTOR(3) |
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245 | |
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246 | /* Timer/Counter2 Overflow */ |
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247 | #define TIMER2_OVF_vect _VECTOR(4) |
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248 | #define SIG_OVERFLOW2 _VECTOR(4) |
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249 | |
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250 | /* Timer/Counter1 Capture Event */ |
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251 | #define TIMER1_CAPT_vect _VECTOR(5) |
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252 | #define SIG_INPUT_CAPTURE1 _VECTOR(5) |
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253 | |
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254 | /* Timer/Counter1 Compare Match A */ |
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255 | #define TIMER1_COMPA_vect _VECTOR(6) |
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256 | #define SIG_OUTPUT_COMPARE1A _VECTOR(6) |
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257 | |
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258 | /* Timer/Counter1 Compare Match B */ |
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259 | #define TIMER1_COMPB_vect _VECTOR(7) |
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260 | #define SIG_OUTPUT_COMPARE1B _VECTOR(7) |
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261 | |
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262 | /* Timer/Counter1 Overflow */ |
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263 | #define TIMER1_OVF_vect _VECTOR(8) |
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264 | #define SIG_OVERFLOW1 _VECTOR(8) |
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265 | |
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266 | /* Timer/Counter0 Overflow */ |
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267 | #define TIMER0_OVF_vect _VECTOR(9) |
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268 | #define SIG_OVERFLOW0 _VECTOR(9) |
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269 | |
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270 | /* SPI Serial Transfer Complete */ |
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271 | #define SPI_STC_vect _VECTOR(10) |
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272 | #define SIG_SPI _VECTOR(10) |
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273 | |
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274 | /* USART, RX Complete */ |
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275 | #define USART_RX_vect _VECTOR(11) |
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276 | #define SIG_UART_RECV _VECTOR(11) |
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277 | |
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278 | /* USART Data Register Empty */ |
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279 | #define USART_UDRE_vect _VECTOR(12) |
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280 | #define SIG_UART_DATA _VECTOR(12) |
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281 | |
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282 | /* USART, TX Complete */ |
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283 | #define USART_TX_vect _VECTOR(13) |
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284 | #define SIG_UART_TRANS _VECTOR(13) |
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285 | |
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286 | /* ADC Conversion Complete */ |
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287 | #define ADC_vect _VECTOR(14) |
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288 | #define SIG_ADC _VECTOR(14) |
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289 | |
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290 | /* EEPROM Ready */ |
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291 | #define EE_RDY_vect _VECTOR(15) |
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292 | #define SIG_EEPROM_READY _VECTOR(15) |
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293 | |
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294 | /* Analog Comparator */ |
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295 | #define ANA_COMP_vect _VECTOR(16) |
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296 | #define SIG_COMPARATOR _VECTOR(16) |
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297 | |
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298 | /* Two-wire Serial Interface */ |
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299 | #define TWI_vect _VECTOR(17) |
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300 | #define SIG_2WIRE_SERIAL _VECTOR(17) |
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301 | |
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302 | /* External Interrupt Request 2 */ |
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303 | #define INT2_vect _VECTOR(18) |
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304 | #define SIG_INTERRUPT2 _VECTOR(18) |
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305 | |
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306 | /* TimerCounter0 Compare Match */ |
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307 | #define TIMER0_COMP_vect _VECTOR(19) |
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308 | #define SIG_OUTPUT_COMPARE0 _VECTOR(19) |
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309 | |
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310 | /* Store Program Memory Read */ |
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311 | #define SPM_RDY_vect _VECTOR(20) |
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312 | #define SIG_SPM_READY _VECTOR(20) |
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313 | |
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314 | #define _VECTORS_SIZE 42 |
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315 | |
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316 | /* |
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317 | The Register Bit names are represented by their bit number (0-7). |
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318 | */ |
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319 | |
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320 | /* General Interrupt Control Register */ |
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321 | #define INT1 7 |
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322 | #define INT0 6 |
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323 | #define INT2 5 |
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324 | #define IVSEL 1 |
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325 | #define IVCE 0 |
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326 | |
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327 | /* General Interrupt Flag Register */ |
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328 | #define INTF1 7 |
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329 | #define INTF0 6 |
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330 | #define INTF2 5 |
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331 | |
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332 | /* Timer/Counter Interrupt MaSK register */ |
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333 | #define OCIE2 7 |
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334 | #define TOIE2 6 |
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335 | #define TICIE1 5 |
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336 | #define OCIE1A 4 |
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337 | #define OCIE1B 3 |
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338 | #define TOIE1 2 |
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339 | #define OCIE0 1 |
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340 | #define TOIE0 0 |
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341 | |
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342 | /* Timer/Counter Interrupt Flag register */ |
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343 | #define OCF2 7 |
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344 | #define TOV2 6 |
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345 | #define ICF1 5 |
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346 | #define OCF1A 4 |
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347 | #define OCF1B 3 |
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348 | #define TOV1 2 |
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349 | #define OCF0 1 |
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350 | #define TOV0 0 |
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351 | |
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352 | /* Store Program Memory Control Register */ |
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353 | #define SPMIE 7 |
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354 | #define RWWSB 6 |
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355 | #define RWWSRE 4 |
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356 | #define BLBSET 3 |
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357 | #define PGWRT 2 |
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358 | #define PGERS 1 |
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359 | #define SPMEN 0 |
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360 | |
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361 | /* TWI Control Register */ |
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362 | #define TWINT 7 |
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363 | #define TWEA 6 |
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364 | #define TWSTA 5 |
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365 | #define TWSTO 4 |
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366 | #define TWWC 3 |
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367 | #define TWEN 2 |
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368 | #define TWIE 0 |
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369 | |
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370 | /* MCU Control Register */ |
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371 | #define SM2 7 |
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372 | #define SE 6 |
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373 | #define SM1 5 |
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374 | #define SM0 4 |
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375 | #define ISC11 3 |
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376 | #define ISC10 2 |
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377 | #define ISC01 1 |
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378 | #define ISC00 0 |
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379 | |
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380 | /* MCU Control and Status Register */ |
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381 | #define ISC2 6 |
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382 | #define WDRF 3 |
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383 | #define BORF 2 |
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384 | #define EXTRF 1 |
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385 | #define PORF 0 |
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386 | |
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387 | /* Timer/Counter 0 Control Register */ |
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388 | #define FOC0 7 |
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389 | #define WGM00 6 |
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390 | #define COM01 5 |
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391 | #define COM00 4 |
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392 | #define WGM01 3 |
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393 | #define CS02 2 |
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394 | #define CS01 1 |
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395 | #define CS00 0 |
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396 | |
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397 | /* |
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398 | The ADHSM bit has been removed from all documentation, |
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399 | as being not needed at all since the comparator has proven |
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400 | to be fast enough even without feeding it more power. |
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401 | */ |
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402 | |
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403 | /* Special Function IO Register */ |
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404 | #define ADTS2 7 |
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405 | #define ADTS1 6 |
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406 | #define ADTS0 5 |
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407 | #define ACME 3 |
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408 | #define PUD 2 |
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409 | #define PSR2 1 |
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410 | #define PSR10 0 |
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411 | |
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412 | /* Timer/Counter 1 Control Register */ |
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413 | #define COM1A1 7 |
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414 | #define COM1A0 6 |
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415 | #define COM1B1 5 |
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416 | #define COM1B0 4 |
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417 | #define FOC1A 3 |
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418 | #define FOC1B 2 |
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419 | #define WGM11 1 |
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420 | #define WGM10 0 |
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421 | |
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422 | /* Timer/Counter 1 Control and Status Register */ |
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423 | #define ICNC1 7 |
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424 | #define ICES1 6 |
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425 | #define WGM13 4 |
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426 | #define WGM12 3 |
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427 | #define CS12 2 |
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428 | #define CS11 1 |
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429 | #define CS10 0 |
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430 | |
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431 | /* Timer/Counter 2 Control Register */ |
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432 | #define FOC2 7 |
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433 | #define WGM20 6 |
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434 | #define COM21 5 |
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435 | #define COM20 4 |
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436 | #define WGM21 3 |
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437 | #define CS22 2 |
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438 | #define CS21 1 |
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439 | #define CS20 0 |
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440 | |
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441 | /* Asynchronous mode Status Register */ |
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442 | #define AS2 3 |
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443 | #define TCN2UB 2 |
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444 | #define OCR2UB 1 |
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445 | #define TCR2UB 0 |
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446 | |
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447 | /* Watchdog Timer Control Register */ |
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448 | #define WDCE 4 |
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449 | #define WDE 3 |
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450 | #define WDP2 2 |
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451 | #define WDP1 1 |
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452 | #define WDP0 0 |
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453 | |
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454 | /* USART Control and Status Register C */ |
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455 | #define URSEL 7 |
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456 | #define UMSEL 6 |
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457 | #define UPM1 5 |
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458 | #define UPM0 4 |
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459 | #define USBS 3 |
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460 | #define UCSZ1 2 |
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461 | #define UCSZ0 1 |
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462 | #define UCPOL 0 |
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463 | |
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464 | /* Data Register, Port A */ |
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465 | #define PA7 7 |
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466 | #define PA6 6 |
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467 | #define PA5 5 |
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468 | #define PA4 4 |
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469 | #define PA3 3 |
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470 | #define PA2 2 |
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471 | #define PA1 1 |
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472 | #define PA0 0 |
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473 | |
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474 | /* Data Direction Register, Port A */ |
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475 | #define DDA7 7 |
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476 | #define DDA6 6 |
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477 | #define DDA5 5 |
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478 | #define DDA4 4 |
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479 | #define DDA3 3 |
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480 | #define DDA2 2 |
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481 | #define DDA1 1 |
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482 | #define DDA0 0 |
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483 | |
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484 | /* Input Pins, Port A */ |
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485 | #define PINA7 7 |
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486 | #define PINA6 6 |
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487 | #define PINA5 5 |
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488 | #define PINA4 4 |
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489 | #define PINA3 3 |
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490 | #define PINA2 2 |
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491 | #define PINA1 1 |
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492 | #define PINA0 0 |
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493 | |
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494 | /* Data Register, Port B */ |
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495 | #define PB7 7 |
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496 | #define PB6 6 |
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497 | #define PB5 5 |
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498 | #define PB4 4 |
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499 | #define PB3 3 |
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500 | #define PB2 2 |
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501 | #define PB1 1 |
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502 | #define PB0 0 |
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503 | |
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504 | /* Data Direction Register, Port B */ |
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505 | #define DDB7 7 |
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506 | #define DDB6 6 |
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507 | #define DDB5 5 |
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508 | #define DDB4 4 |
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509 | #define DDB3 3 |
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510 | #define DDB2 2 |
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511 | #define DDB1 1 |
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512 | #define DDB0 0 |
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513 | |
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514 | /* Input Pins, Port B */ |
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515 | #define PINB7 7 |
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516 | #define PINB6 6 |
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517 | #define PINB5 5 |
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518 | #define PINB4 4 |
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519 | #define PINB3 3 |
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520 | #define PINB2 2 |
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521 | #define PINB1 1 |
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522 | #define PINB0 0 |
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523 | |
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524 | /* Data Register, Port C */ |
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525 | #define PC7 7 |
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526 | #define PC6 6 |
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527 | #define PC5 5 |
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528 | #define PC4 4 |
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529 | #define PC3 3 |
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530 | #define PC2 2 |
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531 | #define PC1 1 |
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532 | #define PC0 0 |
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533 | |
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534 | /* Data Direction Register, Port C */ |
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535 | #define DDC7 7 |
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536 | #define DDC6 6 |
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537 | #define DDC5 5 |
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538 | #define DDC4 4 |
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539 | #define DDC3 3 |
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540 | #define DDC2 2 |
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541 | #define DDC1 1 |
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542 | #define DDC0 0 |
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543 | |
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544 | /* Input Pins, Port C */ |
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545 | #define PINC7 7 |
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546 | #define PINC6 6 |
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547 | #define PINC5 5 |
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548 | #define PINC4 4 |
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549 | #define PINC3 3 |
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550 | #define PINC2 2 |
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551 | #define PINC1 1 |
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552 | #define PINC0 0 |
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553 | |
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554 | /* Data Register, Port D */ |
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555 | #define PD7 7 |
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556 | #define PD6 6 |
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557 | #define PD5 5 |
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558 | #define PD4 4 |
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559 | #define PD3 3 |
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560 | #define PD2 2 |
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561 | #define PD1 1 |
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562 | #define PD0 0 |
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563 | |
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564 | /* Data Direction Register, Port D */ |
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565 | #define DDD7 7 |
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566 | #define DDD6 6 |
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567 | #define DDD5 5 |
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568 | #define DDD4 4 |
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569 | #define DDD3 3 |
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570 | #define DDD2 2 |
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571 | #define DDD1 1 |
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572 | #define DDD0 0 |
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573 | |
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574 | /* Input Pins, Port D */ |
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575 | #define PIND7 7 |
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576 | #define PIND6 6 |
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577 | #define PIND5 5 |
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578 | #define PIND4 4 |
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579 | #define PIND3 3 |
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580 | #define PIND2 2 |
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581 | #define PIND1 1 |
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582 | #define PIND0 0 |
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583 | |
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584 | /* SPI Status Register */ |
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585 | #define SPIF 7 |
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586 | #define WCOL 6 |
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587 | #define SPI2X 0 |
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588 | |
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589 | /* SPI Control Register */ |
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590 | #define SPIE 7 |
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591 | #define SPE 6 |
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592 | #define DORD 5 |
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593 | #define MSTR 4 |
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594 | #define CPOL 3 |
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595 | #define CPHA 2 |
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596 | #define SPR1 1 |
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597 | #define SPR0 0 |
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598 | |
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599 | /* USART Control and Status Register A */ |
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600 | #define RXC 7 |
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601 | #define TXC 6 |
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602 | #define UDRE 5 |
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603 | #define FE 4 |
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604 | #define DOR 3 |
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605 | #define PE 2 |
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606 | #define U2X 1 |
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607 | #define MPCM 0 |
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608 | |
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609 | /* USART Control and Status Register B */ |
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610 | #define RXCIE 7 |
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611 | #define TXCIE 6 |
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612 | #define UDRIE 5 |
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613 | #define RXEN 4 |
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614 | #define TXEN 3 |
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615 | #define UCSZ2 2 |
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616 | #define RXB8 1 |
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617 | #define TXB8 0 |
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618 | |
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619 | /* Analog Comparator Control and Status Register */ |
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620 | #define ACD 7 |
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621 | #define ACBG 6 |
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622 | #define ACO 5 |
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623 | #define ACI 4 |
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624 | #define ACIE 3 |
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625 | #define ACIC 2 |
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626 | #define ACIS1 1 |
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627 | #define ACIS0 0 |
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628 | |
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629 | /* ADC Multiplexer Selection Register */ |
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630 | #define REFS1 7 |
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631 | #define REFS0 6 |
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632 | #define ADLAR 5 |
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633 | #define MUX4 4 |
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634 | #define MUX3 3 |
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635 | #define MUX2 2 |
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636 | #define MUX1 1 |
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637 | #define MUX0 0 |
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638 | |
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639 | /* ADC Control and Status Register */ |
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640 | #define ADEN 7 |
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641 | #define ADSC 6 |
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642 | #define ADATE 5 |
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643 | #define ADIF 4 |
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644 | #define ADIE 3 |
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645 | #define ADPS2 2 |
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646 | #define ADPS1 1 |
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647 | #define ADPS0 0 |
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648 | |
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649 | /* TWI (Slave) Address Register */ |
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650 | #define TWGCE 0 |
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651 | |
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652 | /* TWI Status Register */ |
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653 | #define TWS7 7 |
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654 | #define TWS6 6 |
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655 | #define TWS5 5 |
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656 | #define TWS4 4 |
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657 | #define TWS3 3 |
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658 | #define TWPS1 1 |
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659 | #define TWPS0 0 |
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660 | |
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661 | /* EEPROM Control Register */ |
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662 | #define EERIE 3 |
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663 | #define EEMWE 2 |
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664 | #define EEWE 1 |
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665 | #define EERE 0 |
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666 | |
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667 | /* Constants */ |
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668 | #define SPM_PAGESIZE 64 |
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669 | #define RAMEND 0x25F /* Last On-Chip SRAM Location */ |
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670 | #define XRAMEND RAMEND |
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671 | #define E2END 0x1FF |
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672 | #define E2PAGESIZE 4 |
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673 | #define FLASHEND 0x1FFF |
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674 | |
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675 | |
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676 | /* Fuses */ |
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677 | |
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678 | #define FUSE_MEMORY_SIZE 2 |
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679 | |
---|
680 | /* Low Fuse Byte */ |
---|
681 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
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682 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
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683 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
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684 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
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685 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
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686 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
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687 | #define FUSE_BODEN (unsigned char)~_BV(6) |
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688 | #define FUSE_BODLEVEL (unsigned char)~_BV(7) |
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689 | #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1) |
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690 | |
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691 | /* High Fuse Byte */ |
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692 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
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693 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
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694 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
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695 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
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696 | #define FUSE_CKOPT (unsigned char)~_BV(4) |
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697 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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698 | #define FUSE_WDTON (unsigned char)~_BV(6) |
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699 | #define FUSE_S8535C (unsigned char)~_BV(7) |
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700 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) |
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701 | |
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702 | |
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703 | /* Lock Bits */ |
---|
704 | #define __LOCK_BITS_EXIST |
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705 | #define __BOOT_LOCK_BITS_0_EXIST |
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706 | #define __BOOT_LOCK_BITS_1_EXIST |
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707 | |
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708 | |
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709 | /* Signature */ |
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710 | #define SIGNATURE_0 0x1E |
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711 | #define SIGNATURE_1 0x93 |
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712 | #define SIGNATURE_2 0x08 |
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713 | |
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714 | |
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715 | #endif /* _AVR_IOM8535_H_ */ |
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