[04a62dce] | 1 | /* Copyright (c) 2002, Steinar Haugen |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/iom8515.h - definitions for ATmega8515 */ |
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| 34 | |
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| 35 | #ifndef _AVR_IOM8515_H_ |
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| 36 | #define _AVR_IOM8515_H_ 1 |
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| 37 | |
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| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 39 | |
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| 40 | #ifndef _AVR_IO_H_ |
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| 41 | # error "Include <avr/io.h> instead of this file." |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifndef _AVR_IOXXX_H_ |
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| 45 | # define _AVR_IOXXX_H_ "iom8515.h" |
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| 46 | #else |
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| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 48 | #endif |
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| 49 | |
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| 50 | /* I/O registers */ |
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| 51 | |
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| 52 | /* Oscillator Calibration Register */ |
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| 53 | #define OSCCAL _SFR_IO8(0x04) |
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| 54 | |
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| 55 | /* Input Pins, Port E */ |
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| 56 | #define PINE _SFR_IO8(0x05) |
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| 57 | |
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| 58 | /* Data Direction Register, Port E */ |
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| 59 | #define DDRE _SFR_IO8(0x06) |
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| 60 | |
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| 61 | /* Data Register, Port E */ |
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| 62 | #define PORTE _SFR_IO8(0x07) |
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| 63 | |
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| 64 | /* Analog Comparator Control and Status Register */ |
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| 65 | #define ACSR _SFR_IO8(0x08) |
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| 66 | |
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| 67 | /* USART Baud Rate Register */ |
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| 68 | #define UBRRL _SFR_IO8(0x09) |
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| 69 | |
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| 70 | /* USART Control and Status Register B */ |
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| 71 | #define UCSRB _SFR_IO8(0x0A) |
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| 72 | |
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| 73 | /* USART Control and Status Register A */ |
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| 74 | #define UCSRA _SFR_IO8(0x0B) |
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| 75 | |
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| 76 | /* USART I/O Data Register */ |
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| 77 | #define UDR _SFR_IO8(0x0C) |
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| 78 | |
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| 79 | /* SPI Control Register */ |
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| 80 | #define SPCR _SFR_IO8(0x0D) |
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| 81 | |
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| 82 | /* SPI Status Register */ |
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| 83 | #define SPSR _SFR_IO8(0x0E) |
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| 84 | |
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| 85 | /* SPI I/O Data Register */ |
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| 86 | #define SPDR _SFR_IO8(0x0F) |
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| 87 | |
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| 88 | /* Input Pins, Port D */ |
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| 89 | #define PIND _SFR_IO8(0x10) |
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| 90 | |
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| 91 | /* Data Direction Register, Port D */ |
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| 92 | #define DDRD _SFR_IO8(0x11) |
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| 93 | |
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| 94 | /* Data Register, Port D */ |
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| 95 | #define PORTD _SFR_IO8(0x12) |
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| 96 | |
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| 97 | /* Input Pins, Port C */ |
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| 98 | #define PINC _SFR_IO8(0x13) |
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| 99 | |
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| 100 | /* Data Direction Register, Port C */ |
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| 101 | #define DDRC _SFR_IO8(0x14) |
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| 102 | |
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| 103 | /* Data Register, Port C */ |
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| 104 | #define PORTC _SFR_IO8(0x15) |
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| 105 | |
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| 106 | /* Input Pins, Port B */ |
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| 107 | #define PINB _SFR_IO8(0x16) |
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| 108 | |
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| 109 | /* Data Direction Register, Port B */ |
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| 110 | #define DDRB _SFR_IO8(0x17) |
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| 111 | |
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| 112 | /* Data Register, Port B */ |
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| 113 | #define PORTB _SFR_IO8(0x18) |
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| 114 | |
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| 115 | /* Input Pins, Port A */ |
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| 116 | #define PINA _SFR_IO8(0x19) |
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| 117 | |
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| 118 | /* Data Direction Register, Port A */ |
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| 119 | #define DDRA _SFR_IO8(0x1A) |
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| 120 | |
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| 121 | /* Data Register, Port A */ |
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| 122 | #define PORTA _SFR_IO8(0x1B) |
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| 123 | |
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| 124 | /* EEPROM Control Register */ |
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| 125 | #define EECR _SFR_IO8(0x1C) |
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| 126 | |
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| 127 | /* EEPROM Data Register */ |
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| 128 | #define EEDR _SFR_IO8(0x1D) |
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| 129 | |
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| 130 | /* EEPROM Address Register */ |
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| 131 | #define EEAR _SFR_IO16(0x1E) |
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| 132 | #define EEARL _SFR_IO8(0x1E) |
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| 133 | #define EEARH _SFR_IO8(0x1F) |
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| 134 | |
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| 135 | /* USART Baud Rate Register HI */ |
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| 136 | /* USART Control and Status Register C */ |
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| 137 | #define UBRRH _SFR_IO8(0x20) |
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| 138 | #define UCSRC UBRRH |
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| 139 | |
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| 140 | /* Watchdog Timer Control Register */ |
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| 141 | #define WDTCR _SFR_IO8(0x21) |
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| 142 | |
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| 143 | /* T/C 1 Input Capture Register */ |
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| 144 | #define ICR1 _SFR_IO16(0x24) |
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| 145 | #define ICR1L _SFR_IO8(0x24) |
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| 146 | #define ICR1H _SFR_IO8(0x25) |
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| 147 | |
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| 148 | /* Timer/Counter1 Output Compare Register B */ |
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| 149 | #define OCR1B _SFR_IO16(0x28) |
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| 150 | #define OCR1BL _SFR_IO8(0x28) |
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| 151 | #define OCR1BH _SFR_IO8(0x29) |
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| 152 | |
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| 153 | /* Timer/Counter1 Output Compare Register A */ |
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| 154 | #define OCR1A _SFR_IO16(0x2A) |
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| 155 | #define OCR1AL _SFR_IO8(0x2A) |
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| 156 | #define OCR1AH _SFR_IO8(0x2B) |
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| 157 | |
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| 158 | /* Timer/Counter 1 */ |
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| 159 | #define TCNT1 _SFR_IO16(0x2C) |
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| 160 | #define TCNT1L _SFR_IO8(0x2C) |
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| 161 | #define TCNT1H _SFR_IO8(0x2D) |
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| 162 | |
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| 163 | /* Timer/Counter 1 Control and Status Register */ |
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| 164 | #define TCCR1B _SFR_IO8(0x2E) |
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| 165 | |
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| 166 | /* Timer/Counter 1 Control Register */ |
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| 167 | #define TCCR1A _SFR_IO8(0x2F) |
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| 168 | |
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| 169 | /* Special Function IO Register */ |
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| 170 | #define SFIOR _SFR_IO8(0x30) |
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| 171 | |
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| 172 | /* Timer/Counter 0 Output Compare Register */ |
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| 173 | #define OCR0 _SFR_IO8(0x31) |
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| 174 | |
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| 175 | /* Timer/Counter 0 */ |
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| 176 | #define TCNT0 _SFR_IO8(0x32) |
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| 177 | |
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| 178 | /* Timer/Counter 0 Control Register */ |
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| 179 | #define TCCR0 _SFR_IO8(0x33) |
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| 180 | |
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| 181 | /* MCU Control and Status Register */ |
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| 182 | #define MCUCSR _SFR_IO8(0x34) |
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| 183 | |
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| 184 | /* MCU Control Register */ |
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| 185 | #define MCUCR _SFR_IO8(0x35) |
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| 186 | |
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| 187 | /* Extended MCU Control Register */ |
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| 188 | #define EMCUCR _SFR_IO8(0x36) |
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| 189 | |
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| 190 | /* Store Program Memory Control Register */ |
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| 191 | #define SPMCR _SFR_IO8(0x37) |
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| 192 | |
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| 193 | /* Timer/Counter Interrupt Flag register */ |
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| 194 | #define TIFR _SFR_IO8(0x38) |
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| 195 | |
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| 196 | /* Timer/Counter Interrupt MaSK register */ |
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| 197 | #define TIMSK _SFR_IO8(0x39) |
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| 198 | |
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| 199 | /* General Interrupt Flag Register */ |
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| 200 | #define GIFR _SFR_IO8(0x3A) |
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| 201 | |
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| 202 | /* General Interrupt Control Register */ |
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| 203 | #define GICR _SFR_IO8(0x3B) |
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| 204 | |
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| 205 | /* 0x3D..0x3E SP */ |
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| 206 | |
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| 207 | /* 0x3F SREG */ |
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| 208 | |
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| 209 | /* Interrupt vectors */ |
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| 210 | |
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| 211 | /* External Interrupt Request 0 */ |
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| 212 | #define INT0_vect _VECTOR(1) |
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| 213 | #define SIG_INTERRUPT0 _VECTOR(1) |
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| 214 | |
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| 215 | /* External Interrupt Request 1 */ |
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| 216 | #define INT1_vect _VECTOR(2) |
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| 217 | #define SIG_INTERRUPT1 _VECTOR(2) |
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| 218 | |
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| 219 | /* Timer/Counter1 Capture Event */ |
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| 220 | #define TIMER1_CAPT_vect _VECTOR(3) |
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| 221 | #define SIG_INPUT_CAPTURE1 _VECTOR(3) |
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| 222 | |
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| 223 | /* Timer/Counter1 Compare Match A */ |
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| 224 | #define TIMER1_COMPA_vect _VECTOR(4) |
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| 225 | #define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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| 226 | |
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| 227 | /* Timer/Counter1 Compare MatchB */ |
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| 228 | #define TIMER1_COMPB_vect _VECTOR(5) |
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| 229 | #define SIG_OUTPUT_COMPARE1B _VECTOR(5) |
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| 230 | |
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| 231 | /* Timer/Counter1 Overflow */ |
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| 232 | #define TIMER1_OVF_vect _VECTOR(6) |
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| 233 | #define SIG_OVERFLOW1 _VECTOR(6) |
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| 234 | |
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| 235 | /* Timer/Counter0 Overflow */ |
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| 236 | #define TIMER0_OVF_vect _VECTOR(7) |
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| 237 | #define SIG_OVERFLOW0 _VECTOR(7) |
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| 238 | |
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| 239 | /* Serial Transfer Complete */ |
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| 240 | #define SPI_STC_vect _VECTOR(8) |
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| 241 | #define SIG_SPI _VECTOR(8) |
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| 242 | |
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| 243 | /* UART, Rx Complete */ |
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| 244 | #define USART_RX_vect _VECTOR(9) |
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| 245 | #define UART_RX_vect _VECTOR(9) /* For compatability only */ |
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| 246 | #define SIG_UART_RECV _VECTOR(9) /* For compatability only */ |
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| 247 | |
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| 248 | /* UART Data Register Empty */ |
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| 249 | #define USART_UDRE_vect _VECTOR(10) |
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| 250 | #define UART_UDRE_vect _VECTOR(10) /* For compatability only */ |
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| 251 | #define SIG_UART_DATA _VECTOR(10) /* For compatability only */ |
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| 252 | |
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| 253 | /* UART, Tx Complete */ |
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| 254 | #define USART_TX_vect _VECTOR(11) |
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| 255 | #define UART_TX_vect _VECTOR(11) /* For compatability only */ |
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| 256 | #define SIG_UART_TRANS _VECTOR(11) /* For compatability only */ |
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| 257 | |
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| 258 | /* Analog Comparator */ |
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| 259 | #define ANA_COMP_vect _VECTOR(12) |
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| 260 | #define SIG_COMPARATOR _VECTOR(12) |
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| 261 | |
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| 262 | /* External Interrupt Request 2 */ |
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| 263 | #define INT2_vect _VECTOR(13) |
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| 264 | #define SIG_INTERRUPT2 _VECTOR(13) |
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| 265 | |
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| 266 | /* Timer 0 Compare Match */ |
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| 267 | #define TIMER0_COMP_vect _VECTOR(14) |
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| 268 | #define SIG_OUTPUT_COMPARE0 _VECTOR(14) |
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| 269 | |
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| 270 | /* EEPROM Ready */ |
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| 271 | #define EE_RDY_vect _VECTOR(15) |
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| 272 | #define SIG_EEPROM_READY _VECTOR(15) |
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| 273 | |
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| 274 | /* Store Program Memory Ready */ |
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| 275 | #define SPM_RDY_vect _VECTOR(16) |
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| 276 | #define SIG_SPM_READY _VECTOR(16) |
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| 277 | |
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| 278 | #define _VECTORS_SIZE 34 |
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| 279 | |
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| 280 | /* |
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| 281 | The Register Bit names are represented by their bit number (0-7). |
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| 282 | */ |
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| 283 | |
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| 284 | /* General Interrupt Control Register */ |
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| 285 | #define INT1 7 |
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| 286 | #define INT0 6 |
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| 287 | #define INT2 5 |
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| 288 | #define IVSEL 1 |
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| 289 | #define IVCE 0 |
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| 290 | |
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| 291 | /* General Interrupt Flag Register */ |
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| 292 | #define INTF1 7 |
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| 293 | #define INTF0 6 |
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| 294 | #define INTF2 5 |
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| 295 | |
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| 296 | /* Timer/Counter Interrupt MaSK Register */ |
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| 297 | #define TOIE1 7 |
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| 298 | #define OCIE1A 6 |
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| 299 | #define OCIE1B 5 |
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| 300 | #define TICIE1 3 |
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| 301 | #define TOIE0 1 |
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| 302 | #define OCIE0 0 |
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| 303 | |
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| 304 | /* Timer/Counter Interrupt Flag Register */ |
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| 305 | #define TOV1 7 |
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| 306 | #define OCF1A 6 |
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| 307 | #define OCF1B 5 |
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| 308 | #define ICF1 3 |
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| 309 | #define TOV0 1 |
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| 310 | #define OCF0 0 |
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| 311 | |
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| 312 | /* Store Program Memory Control Register */ |
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| 313 | #define SPMIE 7 |
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| 314 | #define RWWSB 6 |
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| 315 | #define RWWSRE 4 |
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| 316 | #define BLBSET 3 |
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| 317 | #define PGWRT 2 |
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| 318 | #define PGERS 1 |
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| 319 | #define SPMEN 0 |
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| 320 | |
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| 321 | /* Extended MCU Control Register */ |
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| 322 | #define SM0 7 |
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| 323 | #define SRL2 6 |
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| 324 | #define SRL1 5 |
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| 325 | #define SRL0 4 |
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| 326 | #define SRW01 3 |
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| 327 | #define SRW00 2 |
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| 328 | #define SRW11 1 |
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| 329 | #define ISC2 0 |
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| 330 | |
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| 331 | /* MCU Control Register */ |
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| 332 | #define SRE 7 |
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| 333 | #define SRW10 6 |
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| 334 | #define SE 5 |
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| 335 | #define SM1 4 |
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| 336 | #define ISC11 3 |
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| 337 | #define ISC10 2 |
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| 338 | #define ISC01 1 |
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| 339 | #define ISC00 0 |
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| 340 | |
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| 341 | /* MCU Control and Status Register */ |
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| 342 | #define SM2 5 |
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| 343 | #define WDRF 3 |
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| 344 | #define BORF 2 |
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| 345 | #define EXTRF 1 |
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| 346 | #define PORF 0 |
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| 347 | |
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| 348 | /* Timer/Counter 0 Control Register */ |
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| 349 | #define FOC0 7 |
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| 350 | #define WGM00 6 |
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| 351 | #define COM01 5 |
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| 352 | #define COM00 4 |
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| 353 | #define WGM01 3 |
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| 354 | #define CS02 2 |
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| 355 | #define CS01 1 |
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| 356 | #define CS00 0 |
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| 357 | |
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| 358 | /* Special Function IO Register */ |
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| 359 | #define XMBK 6 |
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| 360 | #define XMM2 5 |
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| 361 | #define XMM1 4 |
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| 362 | #define XMM0 3 |
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| 363 | #define PUD 2 |
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| 364 | #define PSR10 0 |
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| 365 | |
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| 366 | /* Timer/Counter 1 Control Register */ |
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| 367 | #define COM1A1 7 |
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| 368 | #define COM1A0 6 |
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| 369 | #define COM1B1 5 |
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| 370 | #define COM1B0 4 |
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| 371 | #define FOC1A 3 |
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| 372 | #define FOC1B 2 |
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| 373 | #define WGM11 1 |
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| 374 | #define WGM10 0 |
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| 375 | |
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| 376 | /* Timer/Counter 1 Control and Status Register */ |
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| 377 | #define ICNC1 7 |
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| 378 | #define ICES1 6 |
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| 379 | #define WGM13 4 |
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| 380 | #define WGM12 3 |
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| 381 | #define CS12 2 |
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| 382 | #define CS11 1 |
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| 383 | #define CS10 0 |
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| 384 | |
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| 385 | /* Watchdog Timer Control Register */ |
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| 386 | #define WDCE 4 |
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| 387 | #define WDE 3 |
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| 388 | #define WDP2 2 |
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| 389 | #define WDP1 1 |
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| 390 | #define WDP0 0 |
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| 391 | |
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| 392 | /* USART Control and Status Register C */ |
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| 393 | #define URSEL 7 |
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| 394 | #define UMSEL 6 |
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| 395 | #define UPM1 5 |
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| 396 | #define UPM0 4 |
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| 397 | #define USBS 3 |
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| 398 | #define UCSZ1 2 |
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| 399 | #define UCSZ0 1 |
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| 400 | #define UCPOL 0 |
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| 401 | |
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| 402 | /* Data Register, Port A */ |
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| 403 | #define PA7 7 |
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| 404 | #define PA6 6 |
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| 405 | #define PA5 5 |
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| 406 | #define PA4 4 |
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| 407 | #define PA3 3 |
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| 408 | #define PA2 2 |
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| 409 | #define PA1 1 |
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| 410 | #define PA0 0 |
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| 411 | |
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| 412 | /* Data Direction Register, Port A */ |
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| 413 | #define DDA7 7 |
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| 414 | #define DDA6 6 |
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| 415 | #define DDA5 5 |
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| 416 | #define DDA4 4 |
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| 417 | #define DDA3 3 |
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| 418 | #define DDA2 2 |
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| 419 | #define DDA1 1 |
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| 420 | #define DDA0 0 |
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| 421 | |
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| 422 | /* Input Pins, Port A */ |
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| 423 | #define PINA7 7 |
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| 424 | #define PINA6 6 |
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| 425 | #define PINA5 5 |
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| 426 | #define PINA4 4 |
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| 427 | #define PINA3 3 |
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| 428 | #define PINA2 2 |
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| 429 | #define PINA1 1 |
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| 430 | #define PINA0 0 |
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| 431 | |
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| 432 | /* Data Register, Port B */ |
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| 433 | #define PB7 7 |
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| 434 | #define PB6 6 |
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| 435 | #define PB5 5 |
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| 436 | #define PB4 4 |
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| 437 | #define PB3 3 |
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| 438 | #define PB2 2 |
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| 439 | #define PB1 1 |
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| 440 | #define PB0 0 |
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| 441 | |
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| 442 | /* Data Direction Register, Port B */ |
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| 443 | #define DDB7 7 |
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| 444 | #define DDB6 6 |
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| 445 | #define DDB5 5 |
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| 446 | #define DDB4 4 |
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| 447 | #define DDB3 3 |
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| 448 | #define DDB2 2 |
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| 449 | #define DDB1 1 |
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| 450 | #define DDB0 0 |
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| 451 | |
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| 452 | /* Input Pins, Port B */ |
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| 453 | #define PINB7 7 |
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| 454 | #define PINB6 6 |
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| 455 | #define PINB5 5 |
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| 456 | #define PINB4 4 |
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| 457 | #define PINB3 3 |
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| 458 | #define PINB2 2 |
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| 459 | #define PINB1 1 |
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| 460 | #define PINB0 0 |
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| 461 | |
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| 462 | /* Data Register, Port C */ |
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| 463 | #define PC7 7 |
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| 464 | #define PC6 6 |
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| 465 | #define PC5 5 |
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| 466 | #define PC4 4 |
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| 467 | #define PC3 3 |
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| 468 | #define PC2 2 |
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| 469 | #define PC1 1 |
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| 470 | #define PC0 0 |
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| 471 | |
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| 472 | /* Data Direction Register, Port C */ |
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| 473 | #define DDC7 7 |
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| 474 | #define DDC6 6 |
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| 475 | #define DDC5 5 |
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| 476 | #define DDC4 4 |
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| 477 | #define DDC3 3 |
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| 478 | #define DDC2 2 |
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| 479 | #define DDC1 1 |
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| 480 | #define DDC0 0 |
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| 481 | |
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| 482 | /* Input Pins, Port C */ |
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| 483 | #define PINC7 7 |
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| 484 | #define PINC6 6 |
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| 485 | #define PINC5 5 |
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| 486 | #define PINC4 4 |
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| 487 | #define PINC3 3 |
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| 488 | #define PINC2 2 |
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| 489 | #define PINC1 1 |
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| 490 | #define PINC0 0 |
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| 491 | |
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| 492 | /* Data Register, Port D */ |
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| 493 | #define PD7 7 |
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| 494 | #define PD6 6 |
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| 495 | #define PD5 5 |
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| 496 | #define PD4 4 |
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| 497 | #define PD3 3 |
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| 498 | #define PD2 2 |
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| 499 | #define PD1 1 |
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| 500 | #define PD0 0 |
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| 501 | |
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| 502 | /* Data Direction Register, Port D */ |
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| 503 | #define DDD7 7 |
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| 504 | #define DDD6 6 |
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| 505 | #define DDD5 5 |
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| 506 | #define DDD4 4 |
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| 507 | #define DDD3 3 |
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| 508 | #define DDD2 2 |
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| 509 | #define DDD1 1 |
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| 510 | #define DDD0 0 |
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| 511 | |
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| 512 | /* Input Pins, Port D */ |
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| 513 | #define PIND7 7 |
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| 514 | #define PIND6 6 |
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| 515 | #define PIND5 5 |
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| 516 | #define PIND4 4 |
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| 517 | #define PIND3 3 |
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| 518 | #define PIND2 2 |
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| 519 | #define PIND1 1 |
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| 520 | #define PIND0 0 |
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| 521 | |
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| 522 | /* SPI Status Register */ |
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| 523 | #define SPIF 7 |
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| 524 | #define WCOL 6 |
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| 525 | #define SPI2X 0 |
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| 526 | |
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| 527 | /* SPI Control Register */ |
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| 528 | #define SPIE 7 |
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| 529 | #define SPE 6 |
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| 530 | #define DORD 5 |
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| 531 | #define MSTR 4 |
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| 532 | #define CPOL 3 |
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| 533 | #define CPHA 2 |
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| 534 | #define SPR1 1 |
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| 535 | #define SPR0 0 |
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| 536 | |
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| 537 | /* USART Control and Status Register A */ |
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| 538 | #define RXC 7 |
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| 539 | #define TXC 6 |
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| 540 | #define UDRE 5 |
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| 541 | #define FE 4 |
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| 542 | #define DOR 3 |
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| 543 | #define PE 2 |
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| 544 | #define U2X 1 |
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| 545 | #define MPCM 0 |
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| 546 | |
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| 547 | /* USART Control and Status Register B */ |
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| 548 | #define RXCIE 7 |
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| 549 | #define TXCIE 6 |
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| 550 | #define UDRIE 5 |
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| 551 | #define RXEN 4 |
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| 552 | #define TXEN 3 |
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| 553 | #define UCSZ2 2 |
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| 554 | #define RXB8 1 |
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| 555 | #define TXB8 0 |
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| 556 | |
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| 557 | /* Analog Comparator Control and Status Register */ |
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| 558 | #define ACD 7 |
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| 559 | #define ACBG 6 |
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| 560 | #define ACO 5 |
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| 561 | #define ACI 4 |
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| 562 | #define ACIE 3 |
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| 563 | #define ACIC 2 |
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| 564 | #define ACIS1 1 |
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| 565 | #define ACIS0 0 |
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| 566 | |
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| 567 | /* Data Register, Port E */ |
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| 568 | #define PE2 2 |
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| 569 | #define PE1 1 |
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| 570 | #define PE0 0 |
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| 571 | |
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| 572 | /* Data Direction Register, Port E */ |
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| 573 | #define DDE2 2 |
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| 574 | #define DDE1 1 |
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| 575 | #define DDE0 0 |
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| 576 | |
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| 577 | /* Input Pins, Port E */ |
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| 578 | #define PINE2 2 |
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| 579 | #define PINE1 1 |
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| 580 | #define PINE0 0 |
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| 581 | |
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| 582 | /* EEPROM Control Register */ |
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| 583 | #define EERIE 3 |
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| 584 | #define EEMWE 2 |
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| 585 | #define EEWE 1 |
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| 586 | #define EERE 0 |
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| 587 | |
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| 588 | /* Constants */ |
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| 589 | #define SPM_PAGESIZE 64 |
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| 590 | #define RAMEND 0x25F /* Last On-Chip SRAM Location */ |
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| 591 | #define XRAMEND 0xFFFF |
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| 592 | #define E2END 0x1FF |
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| 593 | #define E2PAGESIZE 4 |
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| 594 | #define FLASHEND 0x1FFF |
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| 595 | |
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| 596 | |
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| 597 | /* Fuses */ |
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| 598 | |
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| 599 | #define FUSE_MEMORY_SIZE 2 |
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| 600 | |
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| 601 | /* Low Fuse Byte */ |
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| 602 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
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| 603 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
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| 604 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
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| 605 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
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| 606 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
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| 607 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
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| 608 | #define FUSE_BODEN (unsigned char)~_BV(6) |
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| 609 | #define FUSE_BODLEVEL (unsigned char)~_BV(7) |
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| 610 | #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) |
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| 611 | |
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| 612 | /* High Fuse Byte */ |
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| 613 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
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| 614 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
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| 615 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
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| 616 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
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| 617 | #define FUSE_CKOPT (unsigned char)~_BV(4) |
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| 618 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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| 619 | #define FUSE_WDTON (unsigned char)~_BV(6) |
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| 620 | #define FUSE_S8515C (unsigned char)~_BV(7) |
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| 621 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) |
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| 622 | |
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| 623 | |
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| 624 | /* Lock Bits */ |
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| 625 | #define __LOCK_BITS_EXIST |
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| 626 | #define __BOOT_LOCK_BITS_0_EXIST |
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| 627 | #define __BOOT_LOCK_BITS_1_EXIST |
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| 628 | |
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| 629 | |
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| 630 | /* Signature */ |
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| 631 | #define SIGNATURE_0 0x1E |
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| 632 | #define SIGNATURE_1 0x93 |
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| 633 | #define SIGNATURE_2 0x06 |
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| 634 | |
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| 635 | |
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| 636 | #endif /* _AVR_IOM8515_H_ */ |
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