source: rtems/cpukit/score/cpu/avr/avr/iom8.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 12.0 KB
Line 
1/* Copyright (c) 2002, Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom8.h - definitions for ATmega8 */
34
35#ifndef _AVR_IOM8_H_
36#define _AVR_IOM8_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom8.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
53#define TWBR    _SFR_IO8(0x00)
54#define TWSR    _SFR_IO8(0x01)
55#define TWAR    _SFR_IO8(0x02)
56#define TWDR    _SFR_IO8(0x03)
57
58/* ADC */
59#define ADCW    _SFR_IO16(0x04)
60#ifndef __ASSEMBLER__
61#define ADC     _SFR_IO16(0x04)
62#endif
63#define ADCL    _SFR_IO8(0x04)
64#define ADCH    _SFR_IO8(0x05)
65#define ADCSR   _SFR_IO8(0x06)
66#define ADCSRA  _SFR_IO8(0x06)  /* Changed in 2486H-AVR-09/02 */
67#define ADMUX   _SFR_IO8(0x07)
68
69/* analog comparator */
70#define ACSR    _SFR_IO8(0x08)
71
72/* USART */
73#define UBRRL   _SFR_IO8(0x09)
74#define UCSRB   _SFR_IO8(0x0A)
75#define UCSRA   _SFR_IO8(0x0B)
76#define UDR     _SFR_IO8(0x0C)
77
78/* SPI */
79#define SPCR    _SFR_IO8(0x0D)
80#define SPSR    _SFR_IO8(0x0E)
81#define SPDR    _SFR_IO8(0x0F)
82
83/* Port D */
84#define PIND    _SFR_IO8(0x10)
85#define DDRD    _SFR_IO8(0x11)
86#define PORTD   _SFR_IO8(0x12)
87
88/* Port C */
89#define PINC    _SFR_IO8(0x13)
90#define DDRC    _SFR_IO8(0x14)
91#define PORTC   _SFR_IO8(0x15)
92
93/* Port B */
94#define PINB    _SFR_IO8(0x16)
95#define DDRB    _SFR_IO8(0x17)
96#define PORTB   _SFR_IO8(0x18)
97
98/* EEPROM Control Register */
99#define EECR    _SFR_IO8(0x1C)
100
101/* EEPROM Data Register */
102#define EEDR    _SFR_IO8(0x1D)
103
104/* EEPROM Address Register */
105#define EEAR    _SFR_IO16(0x1E)
106#define EEARL   _SFR_IO8(0x1E)
107#define EEARH   _SFR_IO8(0x1F)
108
109#define UCSRC   _SFR_IO8(0x20)
110#define UBRRH   _SFR_IO8(0x20)
111
112#define WDTCR   _SFR_IO8(0x21)
113#define ASSR    _SFR_IO8(0x22)
114
115/* Timer 2 */
116#define OCR2    _SFR_IO8(0x23)
117#define TCNT2   _SFR_IO8(0x24)
118#define TCCR2   _SFR_IO8(0x25)
119
120/* Timer 1 */
121#define ICR1    _SFR_IO16(0x26)
122#define ICR1L   _SFR_IO8(0x26)
123#define ICR1H   _SFR_IO8(0x27)
124#define OCR1B   _SFR_IO16(0x28)
125#define OCR1BL  _SFR_IO8(0x28)
126#define OCR1BH  _SFR_IO8(0x29)
127#define OCR1A   _SFR_IO16(0x2A)
128#define OCR1AL  _SFR_IO8(0x2A)
129#define OCR1AH  _SFR_IO8(0x2B)
130#define TCNT1   _SFR_IO16(0x2C)
131#define TCNT1L  _SFR_IO8(0x2C)
132#define TCNT1H  _SFR_IO8(0x2D)
133#define TCCR1B  _SFR_IO8(0x2E)
134#define TCCR1A  _SFR_IO8(0x2F)
135
136#define SFIOR   _SFR_IO8(0x30)
137
138#define OSCCAL  _SFR_IO8(0x31)
139
140/* Timer 0 */
141#define TCNT0   _SFR_IO8(0x32)
142#define TCCR0   _SFR_IO8(0x33)
143
144#define MCUCSR  _SFR_IO8(0x34)
145#define MCUSR   _SFR_IO8(0x34)  /* Defined as an alias for MCUCSR. */
146
147#define MCUCR   _SFR_IO8(0x35)
148
149#define TWCR    _SFR_IO8(0x36)
150
151#define SPMCR   _SFR_IO8(0x37)
152
153#define TIFR    _SFR_IO8(0x38)
154#define TIMSK   _SFR_IO8(0x39)
155
156#define GIFR    _SFR_IO8(0x3A)
157#define GIMSK   _SFR_IO8(0x3B)
158#define GICR    _SFR_IO8(0x3B)   /* Changed in 2486H-AVR-09/02 */
159
160/* 0x3C reserved (OCR0?) */
161
162/* 0x3D..0x3E SP */
163
164/* 0x3F SREG */
165
166/* Interrupt vectors */
167
168/* External Interrupt Request 0 */
169#define INT0_vect                       _VECTOR(1)
170#define SIG_INTERRUPT0                  _VECTOR(1)
171
172/* External Interrupt Request 1 */
173#define INT1_vect                       _VECTOR(2)
174#define SIG_INTERRUPT1                  _VECTOR(2)
175
176/* Timer/Counter2 Compare Match */
177#define TIMER2_COMP_vect                _VECTOR(3)
178#define SIG_OUTPUT_COMPARE2             _VECTOR(3)
179
180/* Timer/Counter2 Overflow */
181#define TIMER2_OVF_vect                 _VECTOR(4)
182#define SIG_OVERFLOW2                   _VECTOR(4)
183
184/* Timer/Counter1 Capture Event */
185#define TIMER1_CAPT_vect                _VECTOR(5)
186#define SIG_INPUT_CAPTURE1              _VECTOR(5)
187
188/* Timer/Counter1 Compare Match A */
189#define TIMER1_COMPA_vect               _VECTOR(6)
190#define SIG_OUTPUT_COMPARE1A            _VECTOR(6)
191
192/* Timer/Counter1 Compare Match B */
193#define TIMER1_COMPB_vect               _VECTOR(7)
194#define SIG_OUTPUT_COMPARE1B            _VECTOR(7)
195
196/* Timer/Counter1 Overflow */
197#define TIMER1_OVF_vect                 _VECTOR(8)
198#define SIG_OVERFLOW1                   _VECTOR(8)
199
200/* Timer/Counter0 Overflow */
201#define TIMER0_OVF_vect                 _VECTOR(9)
202#define SIG_OVERFLOW0                   _VECTOR(9)
203
204/* Serial Transfer Complete */
205#define SPI_STC_vect                    _VECTOR(10)
206#define SIG_SPI                         _VECTOR(10)
207
208/* USART, Rx Complete */
209#define USART_RXC_vect                  _VECTOR(11)
210#define SIG_UART_RECV                   _VECTOR(11)
211
212/* USART Data Register Empty */
213#define USART_UDRE_vect                 _VECTOR(12)
214#define SIG_UART_DATA                   _VECTOR(12)
215
216/* USART, Tx Complete */
217#define USART_TXC_vect                  _VECTOR(13)
218#define SIG_UART_TRANS                  _VECTOR(13)
219
220/* ADC Conversion Complete */
221#define ADC_vect                        _VECTOR(14)
222#define SIG_ADC                         _VECTOR(14)
223
224/* EEPROM Ready */
225#define EE_RDY_vect                     _VECTOR(15)
226#define SIG_EEPROM_READY                _VECTOR(15)
227
228/* Analog Comparator */
229#define ANA_COMP_vect                   _VECTOR(16)
230#define SIG_COMPARATOR                  _VECTOR(16)
231
232/* 2-wire Serial Interface */
233#define TWI_vect                        _VECTOR(17)
234#define SIG_2WIRE_SERIAL                _VECTOR(17)
235
236/* Store Program Memory Ready */
237#define SPM_RDY_vect                    _VECTOR(18)
238#define SIG_SPM_READY                   _VECTOR(18)
239
240#define _VECTORS_SIZE 38
241
242/* Bit numbers */
243
244/* GIMSK / GICR */
245#define INT1    7
246#define INT0    6
247#define IVSEL   1
248#define IVCE    0
249
250/* GIFR */
251#define INTF1   7
252#define INTF0   6
253
254/* TIMSK */
255#define OCIE2   7
256#define TOIE2   6
257#define TICIE1  5
258#define OCIE1A  4
259#define OCIE1B  3
260#define TOIE1   2
261/* bit 1 reserved (OCIE0?) */
262#define TOIE0   0
263
264/* TIFR */
265#define OCF2    7
266#define TOV2    6
267#define ICF1    5
268#define OCF1A   4
269#define OCF1B   3
270#define TOV1    2
271/* bit 1 reserved (OCF0?) */
272#define TOV0    0
273
274/* SPMCR */
275#define SPMIE   7
276#define RWWSB   6
277/* bit 5 reserved */
278#define RWWSRE  4
279#define BLBSET  3
280#define PGWRT   2
281#define PGERS   1
282#define SPMEN   0
283
284/* TWCR */
285#define TWINT   7
286#define TWEA    6
287#define TWSTA   5
288#define TWSTO   4
289#define TWWC    3
290#define TWEN    2
291/* bit 1 reserved (TWI_TST?) */
292#define TWIE    0
293
294/* TWAR */
295#define TWA6    7
296#define TWA5    6
297#define TWA4    5
298#define TWA3    4
299#define TWA2    3
300#define TWA1    2
301#define TWA0    1
302#define TWGCE   0
303
304/* TWSR */
305#define TWS7    7
306#define TWS6    6
307#define TWS5    5
308#define TWS4    4
309#define TWS3    3
310/* bit 2 reserved */
311#define TWPS1   1
312#define TWPS0   0
313
314/* MCUCR */
315#define SE      7
316#define SM2     6
317#define SM1     5
318#define SM0     4
319#define ISC11   3
320#define ISC10   2
321#define ISC01   1
322#define ISC00   0
323
324/* MCUCSR */
325/* bits 7-4 reserved */
326#define WDRF    3
327#define BORF    2
328#define EXTRF   1
329#define PORF    0
330
331/*
332   The ADHSM bit has been removed from all documentation,
333   as being not needed at all since the comparator has proven
334   to be fast enough even without feeding it more power.
335*/
336
337/* SFIOR */
338/* bits 7-5 reserved */
339#define ACME    3
340#define PUD     2
341#define PSR2    1
342#define PSR10   0
343
344/* TCCR0 */
345/* bits 7-3 reserved */
346#define CS02    2
347#define CS01    1
348#define CS00    0
349
350/* TCCR2 */
351#define FOC2    7
352#define WGM20   6
353#define COM21   5
354#define COM20   4
355#define WGM21   3
356#define CS22    2
357#define CS21    1
358#define CS20    0
359
360/* ASSR */
361/* bits 7-4 reserved */
362#define AS2     3
363#define TCN2UB  2
364#define OCR2UB  1
365#define TCR2UB  0
366
367/* TCCR1A */
368#define COM1A1  7
369#define COM1A0  6
370#define COM1B1  5
371#define COM1B0  4
372#define FOC1A   3
373#define FOC1B   2
374#define WGM11   1
375#define WGM10   0
376
377/* TCCR1B */
378#define ICNC1   7
379#define ICES1   6
380/* bit 5 reserved */
381#define WGM13   4
382#define WGM12   3
383#define CS12    2
384#define CS11    1
385#define CS10    0
386
387/* WDTCR */
388/* bits 7-5 reserved */
389#define WDCE    4
390#define WDE     3
391#define WDP2    2
392#define WDP1    1
393#define WDP0    0
394
395/* UBRRH */
396#define URSEL   7
397
398/* UCSRC */
399#define URSEL   7
400#define UMSEL   6
401#define UPM1    5
402#define UPM0    4
403#define USBS    3
404#define UCSZ1   2
405#define UCSZ0   1
406#define UCPOL   0
407
408/* PORTB */
409#define PB7     7
410#define PB6     6
411#define PB5     5
412#define PB4     4
413#define PB3     3
414#define PB2     2
415#define PB1     1
416#define PB0     0
417
418/* DDRB */
419#define DDB7    7
420#define DDB6    6
421#define DDB5    5
422#define DDB4    4
423#define DDB3    3
424#define DDB2    2
425#define DDB1    1
426#define DDB0    0
427
428/* PINB */
429#define PINB7   7
430#define PINB6   6
431#define PINB5   5
432#define PINB4   4
433#define PINB3   3
434#define PINB2   2
435#define PINB1   1
436#define PINB0   0
437
438/* PORTC */
439#define PC6      6
440#define PC5      5
441#define PC4      4
442#define PC3      3
443#define PC2      2
444#define PC1      1
445#define PC0      0
446
447/* DDRC */
448#define DDC6    6
449#define DDC5    5
450#define DDC4    4
451#define DDC3    3
452#define DDC2    2
453#define DDC1    1
454#define DDC0    0
455
456/* PINC */
457#define PINC6   6
458#define PINC5   5
459#define PINC4   4
460#define PINC3   3
461#define PINC2   2
462#define PINC1   1
463#define PINC0   0
464
465/* PORTD */
466#define PD7      7
467#define PD6      6
468#define PD5      5
469#define PD4      4
470#define PD3      3
471#define PD2      2
472#define PD1      1
473#define PD0      0
474
475/* DDRD */
476#define DDD7    7
477#define DDD6    6
478#define DDD5    5
479#define DDD4    4
480#define DDD3    3
481#define DDD2    2
482#define DDD1    1
483#define DDD0    0
484
485/* PIND */
486#define PIND7   7
487#define PIND6   6
488#define PIND5   5
489#define PIND4   4
490#define PIND3   3
491#define PIND2   2
492#define PIND1   1
493#define PIND0   0
494
495/* SPSR */
496#define SPIF    7
497#define WCOL    6
498#define SPI2X   0
499
500/* SPCR */
501#define SPIE    7
502#define SPE     6
503#define DORD    5
504#define MSTR    4
505#define CPOL    3
506#define CPHA    2
507#define SPR1    1
508#define SPR0    0
509
510/* UCSRA */
511#define RXC     7
512#define TXC     6
513#define UDRE    5
514#define FE      4
515#define DOR     3
516#define PE      2
517#define U2X     1
518#define MPCM    0
519
520/* UCSRB */
521#define RXCIE   7
522#define TXCIE   6
523#define UDRIE   5
524#define RXEN    4
525#define TXEN    3
526#define UCSZ2   2
527#define RXB8    1
528#define TXB8    0
529
530/* ACSR */
531#define ACD     7
532#define ACBG    6
533#define ACO     5
534#define ACI     4
535#define ACIE    3
536#define ACIC    2
537#define ACIS1   1
538#define ACIS0   0
539
540/* ADCSR / ADCSRA */
541#define ADEN    7
542#define ADSC    6
543#define ADFR    5
544#define ADIF    4
545#define ADIE    3
546#define ADPS2   2
547#define ADPS1   1
548#define ADPS0   0
549
550/* ADMUX */
551#define REFS1   7
552#define REFS0   6
553#define ADLAR   5
554/* bit 4 reserved */
555#define MUX3    3
556#define MUX2    2
557#define MUX1    1
558#define MUX0    0
559
560/* EEPROM Control Register */
561#define EERIE   3
562#define EEMWE   2
563#define EEWE    1
564#define EERE    0
565
566/* Constants */
567#define SPM_PAGESIZE 64
568#define RAMEND           0x45F
569#define XRAMEND          RAMEND
570#define E2END            0x1FF
571#define E2PAGESIZE   4
572#define FLASHEND         0x1FFF
573
574
575/* Fuses */
576
577#define FUSE_MEMORY_SIZE 2
578
579/* Low Fuse Byte */
580#define FUSE_CKSEL0      (unsigned char)~_BV(0)
581#define FUSE_CKSEL1      (unsigned char)~_BV(1)
582#define FUSE_CKSEL2      (unsigned char)~_BV(2)
583#define FUSE_CKSEL3      (unsigned char)~_BV(3)
584#define FUSE_SUT0        (unsigned char)~_BV(4)
585#define FUSE_SUT1        (unsigned char)~_BV(5)
586#define FUSE_BODEN       (unsigned char)~_BV(6)
587#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
588#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
589
590/* High Fuse Byte */
591#define FUSE_BOOTRST     (unsigned char)~_BV(0)
592#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
593#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
594#define FUSE_EESAVE      (unsigned char)~_BV(3)
595#define FUSE_CKOPT       (unsigned char)~_BV(4)
596#define FUSE_SPIEN       (unsigned char)~_BV(5)
597#define FUSE_WDTON       (unsigned char)~_BV(6)
598#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
599#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
600
601
602/* Lock Bits */
603#define __LOCK_BITS_EXIST
604#define __BOOT_LOCK_BITS_0_EXIST
605#define __BOOT_LOCK_BITS_1_EXIST
606
607
608/* Signature */
609#define SIGNATURE_0 0x1E
610#define SIGNATURE_1 0x93
611#define SIGNATURE_2 0x07
612
613
614#endif /* _AVR_IOM8_H_ */
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