| 1 | /* Copyright (c) 2004 Eric B. Weddington |
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| 2 | Copyright (c) 2005,2006 Anatoly Sokolov |
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| 3 | All rights reserved. |
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| 4 | |
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| 5 | Redistribution and use in source and binary forms, with or without |
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| 6 | modification, are permitted provided that the following conditions are met: |
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| 7 | |
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| 8 | * Redistributions of source code must retain the above copyright |
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| 9 | notice, this list of conditions and the following disclaimer. |
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| 10 | |
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| 11 | * Redistributions in binary form must reproduce the above copyright |
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| 12 | notice, this list of conditions and the following disclaimer in |
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| 13 | the documentation and/or other materials provided with the |
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| 14 | distribution. |
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| 15 | |
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| 16 | * Neither the name of the copyright holders nor the names of |
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| 17 | contributors may be used to endorse or promote products derived |
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| 18 | from this software without specific prior written permission. |
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| 19 | |
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| 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 30 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 31 | |
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| 32 | /* avr/iom6490.h - definitions for ATmega6490 */ |
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| 33 | |
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| 34 | #ifndef _AVR_IOM6490_H_ |
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| 35 | #define _AVR_IOM6490_H_ 1 |
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| 36 | |
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| 37 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 38 | |
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| 39 | #ifndef _AVR_IO_H_ |
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| 40 | # error "Include <avr/io.h> instead of this file." |
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| 41 | #endif |
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| 42 | |
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| 43 | #ifndef _AVR_IOXXX_H_ |
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| 44 | # define _AVR_IOXXX_H_ "iom6490.h" |
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| 45 | #else |
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| 46 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 47 | #endif |
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| 48 | |
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| 49 | /* Registers and associated bit numbers */ |
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| 50 | |
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| 51 | #define PINA _SFR_IO8(0x00) |
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| 52 | #define PINA7 7 |
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| 53 | #define PINA6 6 |
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| 54 | #define PINA5 5 |
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| 55 | #define PINA4 4 |
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| 56 | #define PINA3 3 |
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| 57 | #define PINA2 2 |
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| 58 | #define PINA1 1 |
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| 59 | #define PINA0 0 |
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| 60 | |
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| 61 | #define DDRA _SFR_IO8(0x01) |
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| 62 | #define DDA7 7 |
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| 63 | #define DDA6 6 |
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| 64 | #define DDA5 5 |
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| 65 | #define DDA4 4 |
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| 66 | #define DDA3 3 |
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| 67 | #define DDA2 2 |
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| 68 | #define DDA1 1 |
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| 69 | #define DDA0 0 |
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| 70 | |
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| 71 | #define PORTA _SFR_IO8(0x02) |
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| 72 | #define PA7 7 |
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| 73 | #define PA6 6 |
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| 74 | #define PA5 5 |
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| 75 | #define PA4 4 |
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| 76 | #define PA3 3 |
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| 77 | #define PA2 2 |
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| 78 | #define PA1 1 |
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| 79 | #define PA0 0 |
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| 80 | |
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| 81 | #define PINB _SFR_IO8(0x03) |
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| 82 | #define PINB7 7 |
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| 83 | #define PINB6 6 |
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| 84 | #define PINB5 5 |
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| 85 | #define PINB4 4 |
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| 86 | #define PINB3 3 |
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| 87 | #define PINB2 2 |
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| 88 | #define PINB1 1 |
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| 89 | #define PINB0 0 |
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| 90 | |
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| 91 | #define DDRB _SFR_IO8(0x04) |
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| 92 | #define DDB7 7 |
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| 93 | #define DDB6 6 |
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| 94 | #define DDB5 5 |
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| 95 | #define DDB4 4 |
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| 96 | #define DDB3 3 |
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| 97 | #define DDB2 2 |
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| 98 | #define DDB1 1 |
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| 99 | #define DDB0 0 |
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| 100 | |
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| 101 | #define PORTB _SFR_IO8(0x05) |
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| 102 | #define PB7 7 |
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| 103 | #define PB6 6 |
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| 104 | #define PB5 5 |
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| 105 | #define PB4 4 |
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| 106 | #define PB3 3 |
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| 107 | #define PB2 2 |
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| 108 | #define PB1 1 |
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| 109 | #define PB0 0 |
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| 110 | |
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| 111 | #define PINC _SFR_IO8(0x06) |
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| 112 | #define PINC7 7 |
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| 113 | #define PINC6 6 |
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| 114 | #define PINC5 5 |
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| 115 | #define PINC4 4 |
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| 116 | #define PINC3 3 |
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| 117 | #define PINC2 2 |
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| 118 | #define PINC1 1 |
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| 119 | #define PINC0 0 |
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| 120 | |
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| 121 | #define DDRC _SFR_IO8(0x07) |
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| 122 | #define DDC7 7 |
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| 123 | #define DDC6 6 |
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| 124 | #define DDC5 5 |
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| 125 | #define DDC4 4 |
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| 126 | #define DDC3 3 |
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| 127 | #define DDC2 2 |
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| 128 | #define DDC1 1 |
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| 129 | #define DDC0 0 |
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| 130 | |
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| 131 | #define PORTC _SFR_IO8(0x08) |
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| 132 | #define PC7 7 |
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| 133 | #define PC6 6 |
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| 134 | #define PC5 5 |
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| 135 | #define PC4 4 |
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| 136 | #define PC3 3 |
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| 137 | #define PC2 2 |
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| 138 | #define PC1 1 |
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| 139 | #define PC0 0 |
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| 140 | |
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| 141 | #define PIND _SFR_IO8(0x09) |
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| 142 | #define PIND7 7 |
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| 143 | #define PIND6 6 |
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| 144 | #define PIND5 5 |
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| 145 | #define PIND4 4 |
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| 146 | #define PIND3 3 |
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| 147 | #define PIND2 2 |
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| 148 | #define PIND1 1 |
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| 149 | #define PIND0 0 |
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| 150 | |
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| 151 | #define DDRD _SFR_IO8(0x0A) |
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| 152 | #define DDD7 7 |
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| 153 | #define DDD6 6 |
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| 154 | #define DDD5 5 |
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| 155 | #define DDD4 4 |
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| 156 | #define DDD3 3 |
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| 157 | #define DDD2 2 |
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| 158 | #define DDD1 1 |
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| 159 | #define DDD0 0 |
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| 160 | |
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| 161 | #define PORTD _SFR_IO8(0x0B) |
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| 162 | #define PD7 7 |
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| 163 | #define PD6 6 |
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| 164 | #define PD5 5 |
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| 165 | #define PD4 4 |
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| 166 | #define PD3 3 |
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| 167 | #define PD2 2 |
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| 168 | #define PD1 1 |
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| 169 | #define PD0 0 |
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| 170 | |
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| 171 | #define PINE _SFR_IO8(0x0C) |
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| 172 | #define PINE7 7 |
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| 173 | #define PINE6 6 |
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| 174 | #define PINE5 5 |
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| 175 | #define PINE4 4 |
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| 176 | #define PINE3 3 |
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| 177 | #define PINE2 2 |
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| 178 | #define PINE1 1 |
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| 179 | #define PINE0 0 |
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| 180 | |
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| 181 | #define DDRE _SFR_IO8(0x0D) |
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| 182 | #define DDE7 7 |
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| 183 | #define DDE6 6 |
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| 184 | #define DDE5 5 |
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| 185 | #define DDE4 4 |
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| 186 | #define DDE3 3 |
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| 187 | #define DDE2 2 |
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| 188 | #define DDE1 1 |
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| 189 | #define DDE0 0 |
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| 190 | |
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| 191 | #define PORTE _SFR_IO8(0x0E) |
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| 192 | #define PE7 7 |
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| 193 | #define PE6 6 |
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| 194 | #define PE5 5 |
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| 195 | #define PE4 4 |
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| 196 | #define PE3 3 |
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| 197 | #define PE2 2 |
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| 198 | #define PE1 1 |
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| 199 | #define PE0 0 |
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| 200 | |
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| 201 | #define PINF _SFR_IO8(0x0F) |
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| 202 | #define PINF7 7 |
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| 203 | #define PINF6 6 |
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| 204 | #define PINF5 5 |
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| 205 | #define PINF4 4 |
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| 206 | #define PINF3 3 |
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| 207 | #define PINF2 2 |
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| 208 | #define PINF1 1 |
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| 209 | #define PINF0 0 |
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| 210 | |
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| 211 | #define DDRF _SFR_IO8(0x10) |
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| 212 | #define DDF7 7 |
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| 213 | #define DDF6 6 |
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| 214 | #define DDF5 5 |
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| 215 | #define DDF4 4 |
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| 216 | #define DDF3 3 |
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| 217 | #define DDF2 2 |
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| 218 | #define DDF1 1 |
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| 219 | #define DDF0 0 |
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| 220 | |
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| 221 | #define PORTF _SFR_IO8(0x11) |
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| 222 | #define PF7 7 |
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| 223 | #define PF6 6 |
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| 224 | #define PF5 5 |
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| 225 | #define PF4 4 |
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| 226 | #define PF3 3 |
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| 227 | #define PF2 2 |
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| 228 | #define PF1 1 |
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| 229 | #define PF0 0 |
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| 230 | |
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| 231 | #define PING _SFR_IO8(0x12) |
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| 232 | #define PING5 5 |
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| 233 | #define PING4 4 |
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| 234 | #define PING3 3 |
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| 235 | #define PING2 2 |
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| 236 | #define PING1 1 |
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| 237 | #define PING0 0 |
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| 238 | |
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| 239 | #define DDRG _SFR_IO8(0x13) |
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| 240 | #define DDG4 4 |
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| 241 | #define DDG3 3 |
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| 242 | #define DDG2 2 |
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| 243 | #define DDG1 1 |
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| 244 | #define DDG0 0 |
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| 245 | |
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| 246 | #define PORTG _SFR_IO8(0x14) |
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| 247 | #define PG4 4 |
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| 248 | #define PG3 3 |
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| 249 | #define PG2 2 |
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| 250 | #define PG1 1 |
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| 251 | #define PG0 0 |
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| 252 | |
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| 253 | #define TIFR0 _SFR_IO8(0x15) |
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| 254 | #define TOV0 0 |
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| 255 | #define OCF0A 1 |
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| 256 | |
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| 257 | #define TIFR1 _SFR_IO8(0x16) |
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| 258 | #define TOV1 0 |
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| 259 | #define OCF1A 1 |
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| 260 | #define OCF1B 2 |
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| 261 | #define ICF1 5 |
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| 262 | |
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| 263 | #define TIFR2 _SFR_IO8(0x17) |
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| 264 | #define TOV2 0 |
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| 265 | #define OCF2A 1 |
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| 266 | |
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| 267 | /* Reserved [0x18..0x1B] */ |
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| 268 | |
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| 269 | #define EIFR _SFR_IO8(0x1C) |
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| 270 | #define INTF0 0 |
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| 271 | #define PCIF0 4 |
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| 272 | #define PCIF1 5 |
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| 273 | #define PCIF2 6 |
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| 274 | #define PCIF3 7 |
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| 275 | |
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| 276 | #define EIMSK _SFR_IO8(0x1D) |
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| 277 | #define INT0 0 |
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| 278 | #define PCIE0 4 |
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| 279 | #define PCIE1 5 |
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| 280 | #define PCIE2 6 |
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| 281 | #define PCIE3 7 |
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| 282 | |
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| 283 | #define GPIOR0 _SFR_IO8(0x1E) |
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| 284 | |
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| 285 | #define EECR _SFR_IO8(0x1F) |
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| 286 | #define EERIE 3 |
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| 287 | #define EEMWE 2 |
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| 288 | #define EEWE 1 |
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| 289 | #define EERE 0 |
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| 290 | |
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| 291 | #define EEDR _SFR_IO8(0X20) |
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| 292 | |
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| 293 | /* Combine EEARL and EEARH */ |
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| 294 | #define EEAR _SFR_IO16(0x21) |
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| 295 | #define EEARL _SFR_IO8(0x21) |
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| 296 | #define EEARH _SFR_IO8(0X22) |
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| 297 | |
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| 298 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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| 299 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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| 300 | subroutines. |
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| 301 | First two letters: EECR address. |
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| 302 | Second two letters: EEDR address. |
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| 303 | Last two letters: EEAR address. */ |
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| 304 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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| 305 | |
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| 306 | #define GTCCR _SFR_IO8(0x23) |
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| 307 | #define PSR10 0 |
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| 308 | #define PSR2 1 |
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| 309 | #define TSM 7 |
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| 310 | |
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| 311 | #define TCCR0A _SFR_IO8(0x24) |
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| 312 | #define CS00 0 |
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| 313 | #define CS01 1 |
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| 314 | #define CS02 2 |
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| 315 | #define WGM01 3 |
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| 316 | #define COM0A0 4 |
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| 317 | #define COM0A1 5 |
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| 318 | #define WGM00 6 |
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| 319 | #define FOC0A 7 |
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| 320 | |
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| 321 | /* Reserved [0x25] */ |
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| 322 | |
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| 323 | #define TCNT0 _SFR_IO8(0X26) |
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| 324 | |
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| 325 | #define OCR0A _SFR_IO8(0X27) |
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| 326 | |
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| 327 | /* Reserved [0x28..0x29] */ |
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| 328 | |
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| 329 | #define GPIOR1 _SFR_IO8(0x2A) |
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| 330 | |
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| 331 | #define GPIOR2 _SFR_IO8(0x2B) |
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| 332 | |
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| 333 | #define SPCR _SFR_IO8(0x2C) |
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| 334 | #define SPR0 0 |
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| 335 | #define SPR1 1 |
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| 336 | #define CPHA 2 |
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| 337 | #define CPOL 3 |
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| 338 | #define MSTR 4 |
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| 339 | #define DORD 5 |
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| 340 | #define SPE 6 |
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| 341 | #define SPIE 7 |
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| 342 | |
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| 343 | #define SPSR _SFR_IO8(0x2D) |
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| 344 | #define SPI2X 0 |
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| 345 | #define WCOL 6 |
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| 346 | #define SPIF 7 |
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| 347 | |
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| 348 | #define SPDR _SFR_IO8(0X2E) |
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| 349 | |
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| 350 | /* Reserved [0x2F] */ |
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| 351 | |
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| 352 | #define ACSR _SFR_IO8(0x30) |
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| 353 | #define ACIS0 0 |
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| 354 | #define ACIS1 1 |
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| 355 | #define ACIC 2 |
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| 356 | #define ACIE 3 |
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| 357 | #define ACI 4 |
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| 358 | #define ACO 5 |
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| 359 | #define ACBG 6 |
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| 360 | #define ACD 7 |
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| 361 | |
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| 362 | #define OCDR _SFR_IO8(0x31) |
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| 363 | #define OCDR0 0 |
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| 364 | #define OCDR1 1 |
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| 365 | #define OCDR2 2 |
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| 366 | #define OCDR3 3 |
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| 367 | #define OCDR4 4 |
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| 368 | #define OCDR5 5 |
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| 369 | #define OCDR6 6 |
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| 370 | #define OCDR7 7 |
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| 371 | #define IDRD 7 |
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| 372 | |
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| 373 | /* Reserved [0x32] */ |
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| 374 | |
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| 375 | #define SMCR _SFR_IO8(0x33) |
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| 376 | #define SE 0 |
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| 377 | #define SM0 1 |
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| 378 | #define SM1 2 |
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| 379 | #define SM2 3 |
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| 380 | |
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| 381 | #define MCUSR _SFR_IO8(0x34) |
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| 382 | #define PORF 0 |
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| 383 | #define EXTRF 1 |
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| 384 | #define BORF 2 |
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| 385 | #define WDRF 3 |
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| 386 | #define JTRF 4 |
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| 387 | |
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| 388 | #define MCUCR _SFR_IO8(0X35) |
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| 389 | #define IVCE 0 |
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| 390 | #define IVSEL 1 |
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| 391 | #define PUD 4 |
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| 392 | #define JTD 7 |
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| 393 | |
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| 394 | /* Reserved [0x36] */ |
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| 395 | |
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| 396 | #define SPMCSR _SFR_IO8(0x37) |
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| 397 | #define SPMEN 0 |
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| 398 | #define PGERS 1 |
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| 399 | #define PGWRT 2 |
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| 400 | #define BLBSET 3 |
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| 401 | #define RWWSRE 4 |
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| 402 | #define RWWSB 6 |
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| 403 | #define SPMIE 7 |
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| 404 | |
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| 405 | /* Reserved [0x38..0x3C] */ |
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| 406 | |
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| 407 | /* SP [0x3D..0x3E] */ |
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| 408 | /* SREG [0x3F] */ |
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| 409 | |
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| 410 | #define WDTCR _SFR_MEM8(0x60) |
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| 411 | #define WDP0 0 |
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| 412 | #define WDP1 1 |
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| 413 | #define WDP2 2 |
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| 414 | #define WDE 3 |
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| 415 | #define WDCE 4 |
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| 416 | |
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| 417 | #define CLKPR _SFR_MEM8(0x61) |
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| 418 | #define CLKPS0 0 |
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| 419 | #define CLKPS1 1 |
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| 420 | #define CLKPS2 2 |
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| 421 | #define CLKPS3 3 |
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| 422 | #define CLKPCE 7 |
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| 423 | |
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| 424 | /* Reserved [0x62..0x63] */ |
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| 425 | |
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| 426 | #define PRR _SFR_MEM8(0x64) |
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| 427 | #define PRADC 0 |
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| 428 | #define PRUSART0 1 |
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| 429 | #define PRSPI 2 |
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| 430 | #define PRTIM1 3 |
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| 431 | #define PRLCD 4 |
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| 432 | |
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| 433 | /* Reserved [0x65] */ |
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| 434 | |
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| 435 | #define OSCCAL _SFR_MEM8(0x66) |
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| 436 | |
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| 437 | /* Reserved [0x67..0x68] */ |
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| 438 | |
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| 439 | #define EICRA _SFR_MEM8(0x69) |
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| 440 | #define ISC00 0 |
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| 441 | #define ISC01 1 |
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| 442 | |
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| 443 | /* Reserved [0x6A] */ |
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| 444 | |
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| 445 | #define PCMSK0 _SFR_MEM8(0x6B) |
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| 446 | #define PCINT0 0 |
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| 447 | #define PCINT1 1 |
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| 448 | #define PCINT2 2 |
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| 449 | #define PCINT3 3 |
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| 450 | #define PCINT4 4 |
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| 451 | #define PCINT5 5 |
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| 452 | #define PCINT6 6 |
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| 453 | #define PCINT7 7 |
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| 454 | |
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| 455 | #define PCMSK1 _SFR_MEM8(0x6C) |
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| 456 | #define PCINT8 0 |
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| 457 | #define PCINT9 1 |
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| 458 | #define PCINT10 2 |
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| 459 | #define PCINT11 3 |
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| 460 | #define PCINT12 4 |
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| 461 | #define PCINT13 5 |
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| 462 | #define PCINT14 6 |
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| 463 | #define PCINT15 7 |
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| 464 | |
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| 465 | #define PCMSK2 _SFR_MEM8(0x6D) |
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| 466 | #define PCINT16 0 |
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| 467 | #define PCINT17 1 |
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| 468 | #define PCINT18 2 |
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| 469 | #define PCINT19 3 |
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| 470 | #define PCINT20 4 |
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| 471 | #define PCINT21 5 |
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| 472 | #define PCINT22 6 |
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| 473 | #define PCINT23 7 |
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| 474 | |
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| 475 | #define TIMSK0 _SFR_MEM8(0x6E) |
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| 476 | #define TOIE0 0 |
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| 477 | #define OCIE0A 1 |
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| 478 | |
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| 479 | #define TIMSK1 _SFR_MEM8(0x6F) |
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| 480 | #define TOIE1 0 |
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| 481 | #define OCIE1A 1 |
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| 482 | #define OCIE1B 2 |
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| 483 | #define ICIE1 5 |
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| 484 | |
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| 485 | #define TIMSK2 _SFR_MEM8(0x70) |
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| 486 | #define TOIE2 0 |
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| 487 | #define OCIE2A 1 |
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| 488 | |
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| 489 | /* Reserved [0x71..0x72] */ |
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| 490 | |
|---|
| 491 | #define PCMSK3 _SFR_MEM8(0x73) |
|---|
| 492 | #define PCINT24 0 |
|---|
| 493 | #define PCINT25 1 |
|---|
| 494 | #define PCINT26 2 |
|---|
| 495 | #define PCINT27 3 |
|---|
| 496 | #define PCINT28 4 |
|---|
| 497 | #define PCINT29 5 |
|---|
| 498 | #define PCINT30 6 |
|---|
| 499 | |
|---|
| 500 | /* Reserved [0x74..0x77] */ |
|---|
| 501 | |
|---|
| 502 | /* Combine ADCL and ADCH */ |
|---|
| 503 | #ifndef __ASSEMBLER__ |
|---|
| 504 | #define ADC _SFR_MEM16(0x78) |
|---|
| 505 | #endif |
|---|
| 506 | #define ADCW _SFR_MEM16(0x78) |
|---|
| 507 | #define ADCL _SFR_MEM8(0x78) |
|---|
| 508 | #define ADCH _SFR_MEM8(0x79) |
|---|
| 509 | |
|---|
| 510 | #define ADCSRA _SFR_MEM8(0x7A) |
|---|
| 511 | #define ADPS0 0 |
|---|
| 512 | #define ADPS1 1 |
|---|
| 513 | #define ADPS2 2 |
|---|
| 514 | #define ADIE 3 |
|---|
| 515 | #define ADIF 4 |
|---|
| 516 | #define ADATE 5 |
|---|
| 517 | #define ADSC 6 |
|---|
| 518 | #define ADEN 7 |
|---|
| 519 | |
|---|
| 520 | #define ADCSRB _SFR_MEM8(0x7B) |
|---|
| 521 | #define ADTS0 0 |
|---|
| 522 | #define ADTS1 1 |
|---|
| 523 | #define ADTS2 2 |
|---|
| 524 | #define ACME 6 |
|---|
| 525 | |
|---|
| 526 | #define ADMUX _SFR_MEM8(0x7C) |
|---|
| 527 | #define MUX0 0 |
|---|
| 528 | #define MUX1 1 |
|---|
| 529 | #define MUX2 2 |
|---|
| 530 | #define MUX3 3 |
|---|
| 531 | #define MUX4 4 |
|---|
| 532 | #define ADLAR 5 |
|---|
| 533 | #define REFS0 6 |
|---|
| 534 | #define REFS1 7 |
|---|
| 535 | |
|---|
| 536 | /* Reserved [0x7D] */ |
|---|
| 537 | |
|---|
| 538 | #define DIDR0 _SFR_MEM8(0x7E) |
|---|
| 539 | #define ADC0D 0 |
|---|
| 540 | #define ADC1D 1 |
|---|
| 541 | #define ADC2D 2 |
|---|
| 542 | #define ADC3D 3 |
|---|
| 543 | #define ADC4D 4 |
|---|
| 544 | #define ADC5D 5 |
|---|
| 545 | #define ADC6D 6 |
|---|
| 546 | #define ADC7D 7 |
|---|
| 547 | |
|---|
| 548 | #define DIDR1 _SFR_MEM8(0x7F) |
|---|
| 549 | #define AIN0D 0 |
|---|
| 550 | #define AIN1D 1 |
|---|
| 551 | |
|---|
| 552 | #define TCCR1A _SFR_MEM8(0X80) |
|---|
| 553 | #define WGM10 0 |
|---|
| 554 | #define WGM11 1 |
|---|
| 555 | #define COM1B0 4 |
|---|
| 556 | #define COM1B1 5 |
|---|
| 557 | #define COM1A0 6 |
|---|
| 558 | #define COM1A1 7 |
|---|
| 559 | |
|---|
| 560 | #define TCCR1B _SFR_MEM8(0X81) |
|---|
| 561 | #define CS10 0 |
|---|
| 562 | #define CS11 1 |
|---|
| 563 | #define CS12 2 |
|---|
| 564 | #define WGM12 3 |
|---|
| 565 | #define WGM13 4 |
|---|
| 566 | #define ICES1 6 |
|---|
| 567 | #define ICNC1 7 |
|---|
| 568 | |
|---|
| 569 | #define TCCR1C _SFR_MEM8(0x82) |
|---|
| 570 | #define FOC1B 6 |
|---|
| 571 | #define FOC1A 7 |
|---|
| 572 | |
|---|
| 573 | /* Reserved [0x83] */ |
|---|
| 574 | |
|---|
| 575 | /* Combine TCNT1L and TCNT1H */ |
|---|
| 576 | #define TCNT1 _SFR_MEM16(0x84) |
|---|
| 577 | |
|---|
| 578 | #define TCNT1L _SFR_MEM8(0x84) |
|---|
| 579 | #define TCNT1H _SFR_MEM8(0x85) |
|---|
| 580 | |
|---|
| 581 | /* Combine ICR1L and ICR1H */ |
|---|
| 582 | #define ICR1 _SFR_MEM16(0x86) |
|---|
| 583 | |
|---|
| 584 | #define ICR1L _SFR_MEM8(0x86) |
|---|
| 585 | #define ICR1H _SFR_MEM8(0x87) |
|---|
| 586 | |
|---|
| 587 | /* Combine OCR1AL and OCR1AH */ |
|---|
| 588 | #define OCR1A _SFR_MEM16(0x88) |
|---|
| 589 | |
|---|
| 590 | #define OCR1AL _SFR_MEM8(0x88) |
|---|
| 591 | #define OCR1AH _SFR_MEM8(0x89) |
|---|
| 592 | |
|---|
| 593 | /* Combine OCR1BL and OCR1BH */ |
|---|
| 594 | #define OCR1B _SFR_MEM16(0x8A) |
|---|
| 595 | |
|---|
| 596 | #define OCR1BL _SFR_MEM8(0x8A) |
|---|
| 597 | #define OCR1BH _SFR_MEM8(0x8B) |
|---|
| 598 | |
|---|
| 599 | /* Reserved [0x8C..0xAF] */ |
|---|
| 600 | |
|---|
| 601 | #define TCCR2A _SFR_MEM8(0xB0) |
|---|
| 602 | #define CS20 0 |
|---|
| 603 | #define CS21 1 |
|---|
| 604 | #define CS22 2 |
|---|
| 605 | #define WGM21 3 |
|---|
| 606 | #define COM2A0 4 |
|---|
| 607 | #define COM2A1 5 |
|---|
| 608 | #define WGM20 6 |
|---|
| 609 | #define FOC2A 7 |
|---|
| 610 | |
|---|
| 611 | /* Reserved [0xB1] */ |
|---|
| 612 | |
|---|
| 613 | #define TCNT2 _SFR_MEM8(0xB2) |
|---|
| 614 | |
|---|
| 615 | #define OCR2A _SFR_MEM8(0xB3) |
|---|
| 616 | |
|---|
| 617 | /* Reserved [0xB4..0xB5] */ |
|---|
| 618 | |
|---|
| 619 | #define ASSR _SFR_MEM8(0xB6) |
|---|
| 620 | #define TCR2UB 0 |
|---|
| 621 | #define OCR2UB 1 |
|---|
| 622 | #define TCN2UB 2 |
|---|
| 623 | #define AS2 3 |
|---|
| 624 | #define EXCLK 4 |
|---|
| 625 | |
|---|
| 626 | /* Reserved [0xB7] */ |
|---|
| 627 | |
|---|
| 628 | #define USICR _SFR_MEM8(0xB8) |
|---|
| 629 | #define USITC 0 |
|---|
| 630 | #define USICLK 1 |
|---|
| 631 | #define USICS0 2 |
|---|
| 632 | #define USICS1 3 |
|---|
| 633 | #define USIWM0 4 |
|---|
| 634 | #define USIWM1 5 |
|---|
| 635 | #define USIOIE 6 |
|---|
| 636 | #define USISIE 7 |
|---|
| 637 | |
|---|
| 638 | #define USISR _SFR_MEM8(0xB9) |
|---|
| 639 | #define USICNT0 0 |
|---|
| 640 | #define USICNT1 1 |
|---|
| 641 | #define USICNT2 2 |
|---|
| 642 | #define USICNT3 3 |
|---|
| 643 | #define USIDC 4 |
|---|
| 644 | #define USIPF 5 |
|---|
| 645 | #define USIOIF 6 |
|---|
| 646 | #define USISIF 7 |
|---|
| 647 | |
|---|
| 648 | #define USIDR _SFR_MEM8(0xBA) |
|---|
| 649 | |
|---|
| 650 | /* Reserved [0xBB..0xBF] */ |
|---|
| 651 | |
|---|
| 652 | #define UCSR0A _SFR_MEM8(0xC0) |
|---|
| 653 | #define MPCM0 0 |
|---|
| 654 | #define U2X0 1 |
|---|
| 655 | #define UPE0 2 |
|---|
| 656 | #define DOR0 3 |
|---|
| 657 | #define FE0 4 |
|---|
| 658 | #define UDRE0 5 |
|---|
| 659 | #define TXC0 6 |
|---|
| 660 | #define RXC0 7 |
|---|
| 661 | |
|---|
| 662 | #define UCSR0B _SFR_MEM8(0XC1) |
|---|
| 663 | #define TXB80 0 |
|---|
| 664 | #define RXB80 1 |
|---|
| 665 | #define UCSZ02 2 |
|---|
| 666 | #define TXEN0 3 |
|---|
| 667 | #define RXEN0 4 |
|---|
| 668 | #define UDRIE0 5 |
|---|
| 669 | #define TXCIE0 6 |
|---|
| 670 | #define RXCIE0 7 |
|---|
| 671 | |
|---|
| 672 | #define UCSR0C _SFR_MEM8(0xC2) |
|---|
| 673 | #define UCPOL0 0 |
|---|
| 674 | #define UCSZ00 1 |
|---|
| 675 | #define UCSZ01 2 |
|---|
| 676 | #define USBS0 3 |
|---|
| 677 | #define UPM00 4 |
|---|
| 678 | #define UPM01 5 |
|---|
| 679 | #define UMSEL0 6 |
|---|
| 680 | |
|---|
| 681 | /* Reserved [0xC3] */ |
|---|
| 682 | |
|---|
| 683 | /* Combine UBRR0L and UBRR0H */ |
|---|
| 684 | #define UBRR0 _SFR_MEM16(0xC4) |
|---|
| 685 | |
|---|
| 686 | #define UBRR0L _SFR_MEM8(0xC4) |
|---|
| 687 | #define UBRR0H _SFR_MEM8(0xC5) |
|---|
| 688 | |
|---|
| 689 | #define UDR0 _SFR_MEM8(0XC6) |
|---|
| 690 | |
|---|
| 691 | /* Reserved [0xC7..0xD7] */ |
|---|
| 692 | |
|---|
| 693 | #define PINH _SFR_MEM8(0xD8) |
|---|
| 694 | #define PINH7 7 |
|---|
| 695 | #define PINH6 6 |
|---|
| 696 | #define PINH5 5 |
|---|
| 697 | #define PINH4 4 |
|---|
| 698 | #define PINH3 3 |
|---|
| 699 | #define PINH2 2 |
|---|
| 700 | #define PINH1 1 |
|---|
| 701 | #define PINH0 0 |
|---|
| 702 | |
|---|
| 703 | #define DDRH _SFR_MEM8(0xD9) |
|---|
| 704 | #define DDH7 7 |
|---|
| 705 | #define DDH6 6 |
|---|
| 706 | #define DDH5 5 |
|---|
| 707 | #define DDH4 4 |
|---|
| 708 | #define DDH3 3 |
|---|
| 709 | #define DDH2 2 |
|---|
| 710 | #define DDH1 1 |
|---|
| 711 | #define DDH0 0 |
|---|
| 712 | |
|---|
| 713 | #define PORTH _SFR_MEM8(0xDA) |
|---|
| 714 | #define PH7 7 |
|---|
| 715 | #define PH6 6 |
|---|
| 716 | #define PH5 5 |
|---|
| 717 | #define PH4 4 |
|---|
| 718 | #define PH3 3 |
|---|
| 719 | #define PH2 2 |
|---|
| 720 | #define PH1 1 |
|---|
| 721 | #define PH0 0 |
|---|
| 722 | |
|---|
| 723 | #define PINJ _SFR_MEM8(0xDB) |
|---|
| 724 | #define PINJ6 6 |
|---|
| 725 | #define PINJ5 5 |
|---|
| 726 | #define PINJ4 4 |
|---|
| 727 | #define PINJ3 3 |
|---|
| 728 | #define PINJ2 2 |
|---|
| 729 | #define PINJ1 1 |
|---|
| 730 | #define PINJ0 0 |
|---|
| 731 | |
|---|
| 732 | #define DDRJ _SFR_MEM8(0xDC) |
|---|
| 733 | #define DDJ6 6 |
|---|
| 734 | #define DDJ5 5 |
|---|
| 735 | #define DDJ4 4 |
|---|
| 736 | #define DDJ3 3 |
|---|
| 737 | #define DDJ2 2 |
|---|
| 738 | #define DDJ1 1 |
|---|
| 739 | #define DDJ0 0 |
|---|
| 740 | |
|---|
| 741 | #define PORTJ _SFR_MEM8(0xDD) |
|---|
| 742 | #define PJ6 6 |
|---|
| 743 | #define PJ5 5 |
|---|
| 744 | #define PJ4 4 |
|---|
| 745 | #define PJ3 3 |
|---|
| 746 | #define PJ2 2 |
|---|
| 747 | #define PJ1 1 |
|---|
| 748 | #define PJ0 0 |
|---|
| 749 | |
|---|
| 750 | /* Reserved [0xDE..0xE3] */ |
|---|
| 751 | |
|---|
| 752 | #define LCDCRA _SFR_MEM8(0XE4) |
|---|
| 753 | #define LCDBL 0 |
|---|
| 754 | #define LCDIE 3 |
|---|
| 755 | #define LCDIF 4 |
|---|
| 756 | #define LCDAB 6 |
|---|
| 757 | #define LCDEN 7 |
|---|
| 758 | |
|---|
| 759 | #define LCDCRB _SFR_MEM8(0XE5) |
|---|
| 760 | #define LCDPM0 0 |
|---|
| 761 | #define LCDPM1 1 |
|---|
| 762 | #define LCDPM2 2 |
|---|
| 763 | #define LCDPM3 3 |
|---|
| 764 | #define LCDMUX0 4 |
|---|
| 765 | #define LCDMUX1 5 |
|---|
| 766 | #define LCD2B 6 |
|---|
| 767 | #define LCDCS 7 |
|---|
| 768 | |
|---|
| 769 | #define LCDFRR _SFR_MEM8(0XE6) |
|---|
| 770 | #define LCDCD0 0 |
|---|
| 771 | #define LCDCD1 1 |
|---|
| 772 | #define LCDCD2 2 |
|---|
| 773 | #define LCDPS0 4 |
|---|
| 774 | #define LCDPS1 5 |
|---|
| 775 | #define LCDPS2 6 |
|---|
| 776 | |
|---|
| 777 | #define LCDCCR _SFR_MEM8(0XE7) |
|---|
| 778 | #define LCDCC0 0 |
|---|
| 779 | #define LCDCC1 1 |
|---|
| 780 | #define LCDCC2 2 |
|---|
| 781 | #define LCDCC3 3 |
|---|
| 782 | #define LCDDC0 5 |
|---|
| 783 | #define LCDDC1 6 |
|---|
| 784 | #define LCDDC2 7 |
|---|
| 785 | |
|---|
| 786 | /* Reserved [0xE8..0xEB] */ |
|---|
| 787 | |
|---|
| 788 | #define LCDDR00 _SFR_MEM8(0XEC) |
|---|
| 789 | #define SEG000 0 |
|---|
| 790 | #define SEG001 1 |
|---|
| 791 | #define SEG002 2 |
|---|
| 792 | #define SEG003 3 |
|---|
| 793 | #define SEG004 4 |
|---|
| 794 | #define SEG005 5 |
|---|
| 795 | #define SEG006 6 |
|---|
| 796 | #define SEG007 7 |
|---|
| 797 | |
|---|
| 798 | #define LCDDR01 _SFR_MEM8(0XED) |
|---|
| 799 | #define SEG008 0 |
|---|
| 800 | #define SEG009 1 |
|---|
| 801 | #define SEG010 2 |
|---|
| 802 | #define SEG011 3 |
|---|
| 803 | #define SEG012 4 |
|---|
| 804 | #define SEG013 5 |
|---|
| 805 | #define SEG014 6 |
|---|
| 806 | #define SEG015 7 |
|---|
| 807 | |
|---|
| 808 | #define LCDDR02 _SFR_MEM8(0XEE) |
|---|
| 809 | #define SEG016 0 |
|---|
| 810 | #define SEG017 1 |
|---|
| 811 | #define SEG018 2 |
|---|
| 812 | #define SEG019 3 |
|---|
| 813 | #define SEG020 4 |
|---|
| 814 | #define SEG021 5 |
|---|
| 815 | #define SEG022 6 |
|---|
| 816 | #define SEG023 7 |
|---|
| 817 | |
|---|
| 818 | #define LCDDR03 _SFR_MEM8(0XEF) |
|---|
| 819 | #define SEG024 0 |
|---|
| 820 | #define SEG025 1 |
|---|
| 821 | #define SEG026 2 |
|---|
| 822 | #define SEG027 3 |
|---|
| 823 | #define SEG028 4 |
|---|
| 824 | #define SEG029 5 |
|---|
| 825 | #define SEG030 6 |
|---|
| 826 | #define SEG031 7 |
|---|
| 827 | |
|---|
| 828 | #define LCDDR04 _SFR_MEM8(0XF0) |
|---|
| 829 | #define SEG032 0 |
|---|
| 830 | #define SEG033 1 |
|---|
| 831 | #define SEG034 2 |
|---|
| 832 | #define SEG035 3 |
|---|
| 833 | #define SEG036 4 |
|---|
| 834 | #define SEG037 5 |
|---|
| 835 | #define SEG038 6 |
|---|
| 836 | #define SEG039 7 |
|---|
| 837 | |
|---|
| 838 | #define LCDDR05 _SFR_MEM8(0XF1) |
|---|
| 839 | #define SEG100 0 |
|---|
| 840 | #define SEG101 1 |
|---|
| 841 | #define SEG102 2 |
|---|
| 842 | #define SEG103 3 |
|---|
| 843 | #define SEG104 4 |
|---|
| 844 | #define SEG105 5 |
|---|
| 845 | #define SEG106 6 |
|---|
| 846 | #define SEG107 7 |
|---|
| 847 | |
|---|
| 848 | #define LCDDR06 _SFR_MEM8(0XF2) |
|---|
| 849 | #define SEG108 0 |
|---|
| 850 | #define SEG109 1 |
|---|
| 851 | #define SEG110 2 |
|---|
| 852 | #define SEG111 3 |
|---|
| 853 | #define SEG112 4 |
|---|
| 854 | #define SEG113 5 |
|---|
| 855 | #define SEG114 6 |
|---|
| 856 | #define SEG115 7 |
|---|
| 857 | |
|---|
| 858 | #define LCDDR07 _SFR_MEM8(0XF3) |
|---|
| 859 | #define SEG116 0 |
|---|
| 860 | #define SEG117 1 |
|---|
| 861 | #define SEG118 2 |
|---|
| 862 | #define SEG119 3 |
|---|
| 863 | #define SEG120 4 |
|---|
| 864 | #define SEG121 5 |
|---|
| 865 | #define SEG122 6 |
|---|
| 866 | #define SEG123 7 |
|---|
| 867 | |
|---|
| 868 | #define LCDDR08 _SFR_MEM8(0XF4) |
|---|
| 869 | #define SEG124 0 |
|---|
| 870 | #define SEG125 1 |
|---|
| 871 | #define SEG126 2 |
|---|
| 872 | #define SEG127 3 |
|---|
| 873 | #define SEG128 4 |
|---|
| 874 | #define SEG129 5 |
|---|
| 875 | #define SEG130 6 |
|---|
| 876 | #define SEG131 7 |
|---|
| 877 | |
|---|
| 878 | #define LCDDR09 _SFR_MEM8(0XF5) |
|---|
| 879 | #define SEG132 0 |
|---|
| 880 | #define SEG133 1 |
|---|
| 881 | #define SEG134 2 |
|---|
| 882 | #define SEG135 3 |
|---|
| 883 | #define SEG136 4 |
|---|
| 884 | #define SEG137 5 |
|---|
| 885 | #define SEG138 6 |
|---|
| 886 | #define SEG139 7 |
|---|
| 887 | |
|---|
| 888 | #define LCDDR10 _SFR_MEM8(0XF6) |
|---|
| 889 | #define SEG200 0 |
|---|
| 890 | #define SEG201 1 |
|---|
| 891 | #define SEG202 2 |
|---|
| 892 | #define SEG203 3 |
|---|
| 893 | #define SEG204 4 |
|---|
| 894 | #define SEG205 5 |
|---|
| 895 | #define SEG206 6 |
|---|
| 896 | #define SEG207 7 |
|---|
| 897 | |
|---|
| 898 | #define LCDDR11 _SFR_MEM8(0XF7) |
|---|
| 899 | #define SEG208 0 |
|---|
| 900 | #define SEG209 1 |
|---|
| 901 | #define SEG210 2 |
|---|
| 902 | #define SEG211 3 |
|---|
| 903 | #define SEG212 4 |
|---|
| 904 | #define SEG213 5 |
|---|
| 905 | #define SEG214 6 |
|---|
| 906 | #define SEG215 7 |
|---|
| 907 | |
|---|
| 908 | #define LCDDR12 _SFR_MEM8(0XF8) |
|---|
| 909 | #define SEG216 0 |
|---|
| 910 | #define SEG217 1 |
|---|
| 911 | #define SEG218 2 |
|---|
| 912 | #define SEG219 3 |
|---|
| 913 | #define SEG220 4 |
|---|
| 914 | #define SEG221 5 |
|---|
| 915 | #define SEG222 6 |
|---|
| 916 | #define SEG223 7 |
|---|
| 917 | |
|---|
| 918 | #define LCDDR13 _SFR_MEM8(0XF9) |
|---|
| 919 | #define SEG224 0 |
|---|
| 920 | #define SEG225 1 |
|---|
| 921 | #define SEG226 2 |
|---|
| 922 | #define SEG227 3 |
|---|
| 923 | #define SEG228 4 |
|---|
| 924 | #define SEG229 5 |
|---|
| 925 | #define SEG230 6 |
|---|
| 926 | #define SEG231 7 |
|---|
| 927 | |
|---|
| 928 | #define LCDDR14 _SFR_MEM8(0XFA) |
|---|
| 929 | #define SEG232 0 |
|---|
| 930 | #define SEG233 1 |
|---|
| 931 | #define SEG234 2 |
|---|
| 932 | #define SEG235 3 |
|---|
| 933 | #define SEG236 4 |
|---|
| 934 | #define SEG237 5 |
|---|
| 935 | #define SEG238 6 |
|---|
| 936 | #define SEG239 7 |
|---|
| 937 | |
|---|
| 938 | #define LCDDR15 _SFR_MEM8(0XFB) |
|---|
| 939 | #define SEG300 0 |
|---|
| 940 | #define SEG301 1 |
|---|
| 941 | #define SEG302 2 |
|---|
| 942 | #define SEG303 3 |
|---|
| 943 | #define SEG304 4 |
|---|
| 944 | #define SEG305 5 |
|---|
| 945 | #define SEG306 6 |
|---|
| 946 | #define SEG307 7 |
|---|
| 947 | |
|---|
| 948 | #define LCDDR16 _SFR_MEM8(0XFC) |
|---|
| 949 | #define SEG308 0 |
|---|
| 950 | #define SEG309 1 |
|---|
| 951 | #define SEG310 2 |
|---|
| 952 | #define SEG311 3 |
|---|
| 953 | #define SEG312 4 |
|---|
| 954 | #define SEG313 5 |
|---|
| 955 | #define SEG314 6 |
|---|
| 956 | #define SEG315 7 |
|---|
| 957 | |
|---|
| 958 | #define LCDDR17 _SFR_MEM8(0XFD) |
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| 959 | #define SEG316 0 |
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| 960 | #define SEG217 1 |
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| 961 | #define SEG318 2 |
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| 962 | #define SEG319 3 |
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| 963 | #define SEG320 4 |
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| 964 | #define SEG321 5 |
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| 965 | #define SEG322 6 |
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| 966 | #define SEG323 7 |
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| 967 | |
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| 968 | #define LCDDR18 _SFR_MEM8(0XFE) |
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| 969 | #define SEG324 0 |
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| 970 | #define SEG325 1 |
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| 971 | #define SEG326 2 |
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| 972 | #define SEG327 3 |
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| 973 | #define SEG328 4 |
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| 974 | #define SEG329 5 |
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| 975 | #define SEG330 6 |
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| 976 | #define SEG331 7 |
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| 977 | |
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| 978 | #define LCDDR19 _SFR_MEM8(0XFF) |
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| 979 | #define SEG332 0 |
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| 980 | #define SEG333 1 |
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| 981 | #define SEG334 2 |
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| 982 | #define SEG335 3 |
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| 983 | #define SEG336 4 |
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| 984 | #define SEG337 5 |
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| 985 | #define SEG338 6 |
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| 986 | #define SEG339 7 |
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| 987 | |
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| 988 | |
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| 989 | /* Interrupt vectors */ |
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| 990 | /* Vector 0 is the reset vector */ |
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| 991 | /* External Interrupt Request 0 */ |
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| 992 | #define INT0_vect _VECTOR(1) |
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| 993 | #define SIG_INTERRUPT0 _VECTOR(1) |
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| 994 | |
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| 995 | /* Pin Change Interrupt Request 0 */ |
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| 996 | #define PCINT0_vect _VECTOR(2) |
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| 997 | #define SIG_PIN_CHANGE0 _VECTOR(2) |
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| 998 | |
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| 999 | /* Pin Change Interrupt Request 1 */ |
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| 1000 | #define PCINT1_vect _VECTOR(3) |
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| 1001 | #define SIG_PIN_CHANGE1 _VECTOR(3) |
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| 1002 | |
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| 1003 | /* Timer/Counter2 Compare Match */ |
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| 1004 | #define TIMER2_COMP_vect _VECTOR(4) |
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| 1005 | #define SIG_OUTPUT_COMPARE2 _VECTOR(4) |
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| 1006 | |
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| 1007 | /* Timer/Counter2 Overflow */ |
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| 1008 | #define TIMER2_OVF_vect _VECTOR(5) |
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| 1009 | #define SIG_OVERFLOW2 _VECTOR(5) |
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| 1010 | |
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| 1011 | /* Timer/Counter1 Capture Event */ |
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| 1012 | #define TIMER1_CAPT_vect _VECTOR(6) |
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| 1013 | #define SIG_INPUT_CAPTURE1 _VECTOR(6) |
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| 1014 | |
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| 1015 | /* Timer/Counter1 Compare Match A */ |
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| 1016 | #define TIMER1_COMPA_vect _VECTOR(7) |
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| 1017 | #define SIG_OUTPUT_COMPARE1A _VECTOR(7) |
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| 1018 | |
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| 1019 | /* Timer/Counter Compare Match B */ |
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| 1020 | #define TIMER1_COMPB_vect _VECTOR(8) |
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| 1021 | #define SIG_OUTPUT_COMPARE1B _VECTOR(8) |
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| 1022 | |
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| 1023 | /* Timer/Counter1 Overflow */ |
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| 1024 | #define TIMER1_OVF_vect _VECTOR(9) |
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| 1025 | #define SIG_OVERFLOW1 _VECTOR(9) |
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| 1026 | |
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| 1027 | /* Timer/Counter0 Compare Match */ |
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| 1028 | #define TIMER0_COMP_vect _VECTOR(10) |
|---|
| 1029 | #define SIG_OUTPUT_COMPARE0 _VECTOR(10) |
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| 1030 | |
|---|
| 1031 | /* Timer/Counter0 Overflow */ |
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| 1032 | #define TIMER0_OVF_vect _VECTOR(11) |
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| 1033 | #define SIG_OVERFLOW0 _VECTOR(11) |
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| 1034 | |
|---|
| 1035 | /* SPI Serial Transfer Complete */ |
|---|
| 1036 | #define SPI_STC_vect _VECTOR(12) |
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| 1037 | #define SIG_SPI _VECTOR(12) |
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| 1038 | |
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| 1039 | /* USART, Rx Complete */ |
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| 1040 | #define USART_RX_vect _VECTOR(13) |
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| 1041 | #define SIG_UART_RECV _VECTOR(13) |
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| 1042 | |
|---|
| 1043 | /* USART Data register Empty */ |
|---|
| 1044 | #define USART_UDRE_vect _VECTOR(14) |
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| 1045 | #define SIG_UART_DATA _VECTOR(14) |
|---|
| 1046 | |
|---|
| 1047 | /* USART0, Tx Complete */ |
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| 1048 | #define USART0_TX_vect _VECTOR(15) |
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| 1049 | #define SIG_UART_TRANS _VECTOR(15) |
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| 1050 | |
|---|
| 1051 | /* USI Start Condition */ |
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| 1052 | #define USI_START_vect _VECTOR(16) |
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| 1053 | #define SIG_USI_START _VECTOR(16) |
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| 1054 | |
|---|
| 1055 | /* USI Overflow */ |
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| 1056 | #define USI_OVERFLOW_vect _VECTOR(17) |
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| 1057 | #define SIG_USI_OVERFLOW _VECTOR(17) |
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| 1058 | |
|---|
| 1059 | /* Analog Comparator */ |
|---|
| 1060 | #define ANALOG_COMP_vect _VECTOR(18) |
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| 1061 | #define SIG_COMPARATOR _VECTOR(18) |
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| 1062 | |
|---|
| 1063 | /* ADC Conversion Complete */ |
|---|
| 1064 | #define ADC_vect _VECTOR(19) |
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| 1065 | #define SIG_ADC _VECTOR(19) |
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| 1066 | |
|---|
| 1067 | /* EEPROM Ready */ |
|---|
| 1068 | #define EE_READY_vect _VECTOR(20) |
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| 1069 | #define SIG_EEPROM_READY _VECTOR(20) |
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| 1070 | |
|---|
| 1071 | /* Store Program Memory Read */ |
|---|
| 1072 | #define SPM_READY_vect _VECTOR(21) |
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| 1073 | #define SIG_SPM_READY _VECTOR(21) |
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| 1074 | |
|---|
| 1075 | /* LCD Start of Frame */ |
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| 1076 | #define LCD_vect _VECTOR(22) |
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| 1077 | #define SIG_LCD _VECTOR(22) |
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| 1078 | |
|---|
| 1079 | /* Pin Change Interrupt Request 2 */ |
|---|
| 1080 | #define PCINT2_vect _VECTOR(23) |
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| 1081 | #define SIG_PIN_CHANGE2 _VECTOR(23) |
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| 1082 | |
|---|
| 1083 | /* Pin Change Interrupt Request 3 */ |
|---|
| 1084 | #define PCINT3_vect _VECTOR(24) |
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| 1085 | #define SIG_PIN_CHANGE3 _VECTOR(24) |
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| 1086 | |
|---|
| 1087 | #define _VECTORS_SIZE 100 |
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| 1088 | |
|---|
| 1089 | |
|---|
| 1090 | /* Constants */ |
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| 1091 | #define SPM_PAGESIZE 256 |
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| 1092 | #define RAMEND 0x10FF |
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| 1093 | #define XRAMEND RAMEND |
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| 1094 | #define E2END 0x7FF |
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| 1095 | #define E2PAGESIZE 8 |
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| 1096 | #define FLASHEND 0xFFFF |
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| 1097 | |
|---|
| 1098 | |
|---|
| 1099 | /* Fuses */ |
|---|
| 1100 | |
|---|
| 1101 | #define FUSE_MEMORY_SIZE 3 |
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| 1102 | |
|---|
| 1103 | /* Low Fuse Byte */ |
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| 1104 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
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| 1105 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
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| 1106 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
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| 1107 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
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| 1108 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
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| 1109 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
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| 1110 | #define FUSE_CKOUT (unsigned char)~_BV(6) |
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| 1111 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) |
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| 1112 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
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| 1113 | |
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| 1114 | /* High Fuse Byte */ |
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| 1115 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
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| 1116 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
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| 1117 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
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| 1118 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
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| 1119 | #define FUSE_WDTON (unsigned char)~_BV(4) |
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| 1120 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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| 1121 | #define FUSE_JTAGEN (unsigned char)~_BV(6) |
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| 1122 | #define FUSE_OCDEN (unsigned char)~_BV(7) |
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| 1123 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
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| 1124 | |
|---|
| 1125 | /* Extended Fuse Byte */ |
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| 1126 | #define FUSE_RSTDISBL (unsigned char)~_BV(0) |
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| 1127 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) |
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| 1128 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) |
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| 1129 | #define EFUSE_DEFAULT (0xFF) |
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| 1130 | |
|---|
| 1131 | |
|---|
| 1132 | /* Lock Bits */ |
|---|
| 1133 | #define __LOCK_BITS_EXIST |
|---|
| 1134 | #define __BOOT_LOCK_BITS_0_EXIST |
|---|
| 1135 | #define __BOOT_LOCK_BITS_1_EXIST |
|---|
| 1136 | |
|---|
| 1137 | |
|---|
| 1138 | /* Signature */ |
|---|
| 1139 | #define SIGNATURE_0 0x1E |
|---|
| 1140 | #define SIGNATURE_1 0x96 |
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| 1141 | #define SIGNATURE_2 0x04 |
|---|
| 1142 | |
|---|
| 1143 | |
|---|
| 1144 | #endif /* _AVR_IOM6490_H_ */ |
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