source: rtems/cpukit/score/cpu/avr/avr/iom649.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 19.6 KB
Line 
1/* Copyright (c) 2004 Eric B. Weddington
2   Copyright (c) 2005,2006 Anatoly Sokolov
3   All rights reserved.
4
5   Redistribution and use in source and binary forms, with or without
6   modification, are permitted provided that the following conditions are met:
7
8   * Redistributions of source code must retain the above copyright
9     notice, this list of conditions and the following disclaimer.
10
11   * Redistributions in binary form must reproduce the above copyright
12     notice, this list of conditions and the following disclaimer in
13     the documentation and/or other materials provided with the
14     distribution.
15
16   * Neither the name of the copyright holders nor the names of
17     contributors may be used to endorse or promote products derived
18     from this software without specific prior written permission.
19
20  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  POSSIBILITY OF SUCH DAMAGE. */
31
32/* avr/iom649.h - definitions for ATmega649 */
33
34#ifndef _AVR_IOM649_H_
35#define _AVR_IOM649_H_ 1
36
37/* This file should only be included from <avr/io.h>, never directly. */
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom649.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDA7    7
63#define DDA6    6
64#define DDA5    5
65#define DDA4    4
66#define DDA3    3
67#define DDA2    2
68#define DDA1    1
69#define DDA0    0
70
71#define PORTA   _SFR_IO8(0x02)
72#define PA7     7
73#define PA6     6
74#define PA5     5
75#define PA4     4
76#define PA3     3
77#define PA2     2
78#define PA1     1
79#define PA0     0
80
81#define PINB    _SFR_IO8(0x03)
82#define PINB7   7
83#define PINB6   6
84#define PINB5   5
85#define PINB4   4
86#define PINB3   3
87#define PINB2   2
88#define PINB1   1
89#define PINB0   0
90
91#define DDRB    _SFR_IO8(0x04)
92#define DDB7    7
93#define DDB6    6
94#define DDB5    5
95#define DDB4    4
96#define DDB3    3
97#define DDB2    2
98#define DDB1    1
99#define DDB0    0
100
101#define PORTB   _SFR_IO8(0x05)
102#define PB7     7
103#define PB6     6
104#define PB5     5
105#define PB4     4
106#define PB3     3
107#define PB2     2
108#define PB1     1
109#define PB0     0
110
111#define PINC    _SFR_IO8(0x06)
112#define PINC7   7
113#define PINC6   6
114#define PINC5   5
115#define PINC4   4
116#define PINC3   3
117#define PINC2   2
118#define PINC1   1
119#define PINC0   0
120
121#define DDRC    _SFR_IO8(0x07)
122#define DDC7    7
123#define DDC6    6
124#define DDC5    5
125#define DDC4    4
126#define DDC3    3
127#define DDC2    2
128#define DDC1    1
129#define DDC0    0
130
131#define PORTC   _SFR_IO8(0x08)
132#define PC7     7
133#define PC6     6
134#define PC5     5
135#define PC4     4
136#define PC3     3
137#define PC2     2
138#define PC1     1
139#define PC0     0
140
141#define PIND    _SFR_IO8(0x09)
142#define PIND7   7
143#define PIND6   6
144#define PIND5   5
145#define PIND4   4
146#define PIND3   3
147#define PIND2   2
148#define PIND1   1
149#define PIND0   0
150
151#define DDRD    _SFR_IO8(0x0A)
152#define DDD7    7
153#define DDD6    6
154#define DDD5    5
155#define DDD4    4
156#define DDD3    3
157#define DDD2    2
158#define DDD1    1
159#define DDD0    0
160
161#define PORTD   _SFR_IO8(0x0B)
162#define PD7     7
163#define PD6     6
164#define PD5     5
165#define PD4     4
166#define PD3     3
167#define PD2     2
168#define PD1     1
169#define PD0     0
170
171#define PINE    _SFR_IO8(0x0C)
172#define PINE7   7
173#define PINE6   6
174#define PINE5   5
175#define PINE4   4
176#define PINE3   3
177#define PINE2   2
178#define PINE1   1
179#define PINE0   0
180
181#define DDRE    _SFR_IO8(0x0D)
182#define DDE7    7
183#define DDE6    6
184#define DDE5    5
185#define DDE4    4
186#define DDE3    3
187#define DDE2    2
188#define DDE1    1
189#define DDE0    0
190
191#define PORTE   _SFR_IO8(0x0E)
192#define PE7     7
193#define PE6     6
194#define PE5     5
195#define PE4     4
196#define PE3     3
197#define PE2     2
198#define PE1     1
199#define PE0     0
200
201#define PINF    _SFR_IO8(0x0F)
202#define PINF7   7
203#define PINF6   6
204#define PINF5   5
205#define PINF4   4
206#define PINF3   3
207#define PINF2   2
208#define PINF1   1
209#define PINF0   0
210
211#define DDRF    _SFR_IO8(0x10)
212#define DDF7    7
213#define DDF6    6
214#define DDF5    5
215#define DDF4    4
216#define DDF3    3
217#define DDF2    2
218#define DDF1    1
219#define DDF0    0
220
221#define PORTF   _SFR_IO8(0x11)
222#define PF7     7
223#define PF6     6
224#define PF5     5
225#define PF4     4
226#define PF3     3
227#define PF2     2
228#define PF1     1
229#define PF0     0
230
231#define PING    _SFR_IO8(0x12)
232#define PING5   5
233#define PING4   4
234#define PING3   3
235#define PING2   2
236#define PING1   1
237#define PING0   0
238
239#define DDRG    _SFR_IO8(0x13)
240#define DDG4    4
241#define DDG3    3
242#define DDG2    2
243#define DDG1    1
244#define DDG0    0
245
246#define PORTG   _SFR_IO8(0x14)
247#define PG4     4
248#define PG3     3
249#define PG2     2
250#define PG1     1
251#define PG0     0
252
253#define TIFR0   _SFR_IO8(0x15)
254#define TOV0    0
255#define OCF0A   1
256
257#define TIFR1   _SFR_IO8(0x16)
258#define TOV1    0
259#define OCF1A   1
260#define OCF1B   2
261#define ICF1    5
262
263#define TIFR2   _SFR_IO8(0x17)
264#define TOV2    0
265#define OCF2A   1
266
267/* Reserved [0x18..0x1B] */
268
269#define EIFR   _SFR_IO8(0x1C)
270#define INTF0   0
271#define PCIF0   4
272#define PCIF1   5
273
274#define EIMSK   _SFR_IO8(0x1D)
275#define INT0    0
276#define PCIE0   4
277#define PCIE1   5
278
279#define GPIOR0  _SFR_IO8(0x1E)
280
281#define EECR   _SFR_IO8(0x1F)
282#define EERIE   3
283#define EEMWE   2
284#define EEWE    1
285#define EERE    0
286
287#define EEDR   _SFR_IO8(0X20)
288
289/* Combine EEARL and EEARH */
290#define EEAR   _SFR_IO16(0x21)
291#define EEARL  _SFR_IO8(0x21)
292#define EEARH  _SFR_IO8(0X22)
293
294/* 6-char sequence denoting where to find the EEPROM registers in memory space.
295   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
296   subroutines.
297   First two letters:  EECR address.
298   Second two letters: EEDR address.
299   Last two letters:   EEAR address.  */
300#define __EEPROM_REG_LOCATIONS__ 1F2021
301
302#define GTCCR   _SFR_IO8(0x23)
303#define PSR10   0
304#define PSR2    1
305#define TSM     7
306
307#define TCCR0A  _SFR_IO8(0x24)
308#define CS00    0
309#define CS01    1
310#define CS02    2
311#define WGM01   3
312#define COM0A0  4
313#define COM0A1  5
314#define WGM00   6
315#define FOC0A   7
316
317/* Reserved [0x25] */
318
319#define TCNT0   _SFR_IO8(0X26)
320
321#define OCR0A   _SFR_IO8(0X27)
322
323/* Reserved [0x28..0x29] */
324
325#define GPIOR1  _SFR_IO8(0x2A)
326
327#define GPIOR2  _SFR_IO8(0x2B)
328
329#define SPCR    _SFR_IO8(0x2C)
330#define SPR0    0
331#define SPR1    1
332#define CPHA    2
333#define CPOL    3
334#define MSTR    4
335#define DORD    5
336#define SPE     6
337#define SPIE    7
338
339#define SPSR    _SFR_IO8(0x2D)
340#define SPI2X   0
341#define WCOL    6
342#define SPIF    7
343
344#define SPDR    _SFR_IO8(0X2E)
345
346/* Reserved [0x2F] */
347
348#define ACSR    _SFR_IO8(0x30)
349#define ACIS0   0
350#define ACIS1   1
351#define ACIC    2
352#define ACIE    3
353#define ACI     4
354#define ACO     5
355#define ACBG    6
356#define ACD     7
357
358#define OCDR    _SFR_IO8(0x31)
359#define OCDR0   0
360#define OCDR1   1
361#define OCDR2   2
362#define OCDR3   3
363#define OCDR4   4
364#define OCDR5   5
365#define OCDR6   6
366#define OCDR7   7
367#define IDRD    7
368
369/* Reserved [0x32] */
370
371#define SMCR    _SFR_IO8(0x33)
372#define SE      0
373#define SM0     1
374#define SM1     2
375#define SM2     3
376
377#define MCUSR   _SFR_IO8(0x34)
378#define PORF    0
379#define EXTRF   1
380#define BORF    2
381#define WDRF    3
382#define JTRF    4
383
384#define MCUCR   _SFR_IO8(0X35)
385#define IVCE    0
386#define IVSEL   1
387#define PUD     4
388#define JTD     7
389
390/* Reserved [0x36] */
391
392#define SPMCSR  _SFR_IO8(0x37)
393#define SPMEN   0
394#define PGERS   1
395#define PGWRT   2
396#define BLBSET  3
397#define RWWSRE  4
398#define RWWSB   6
399#define SPMIE   7
400
401/* Reserved [0x38..0x3C] */
402
403/* SP [0x3D..0x3E] */
404/* SREG [0x3F] */
405
406#define WDTCR   _SFR_MEM8(0x60)
407#define WDP0    0
408#define WDP1    1
409#define WDP2    2
410#define WDE     3
411#define WDCE    4
412
413#define CLKPR   _SFR_MEM8(0x61)
414#define CLKPS0  0
415#define CLKPS1  1
416#define CLKPS2  2
417#define CLKPS3  3
418#define CLKPCE  7
419
420/* Reserved [0x62..0x63] */
421
422#define PRR     _SFR_MEM8(0x64)
423#define PRADC       0
424#define PRUSART0    1
425#define PRSPI       2
426#define PRTIM1      3
427#define PRLCD       4
428
429/* Reserved [0x65] */
430
431#define OSCCAL  _SFR_MEM8(0x66)
432
433/* Reserved [0x67..0x68] */
434
435#define EICRA   _SFR_MEM8(0x69)
436#define ISC00   0
437#define ISC01   1
438
439/* Reserved [0x6A] */
440
441#define PCMSK0  _SFR_MEM8(0x6B)
442#define PCINT0  0
443#define PCINT1  1
444#define PCINT2  2
445#define PCINT3  3
446#define PCINT4  4
447#define PCINT5  5
448#define PCINT6  6
449#define PCINT7  7
450
451#define PCMSK1  _SFR_MEM8(0x6C)
452#define PCINT8  0
453#define PCINT9  1
454#define PCINT10 2
455#define PCINT11 3
456#define PCINT12 4
457#define PCINT13 5
458#define PCINT14 6
459#define PCINT15 7
460
461/* Reserved [0x6D] */
462
463#define TIMSK0  _SFR_MEM8(0x6E)
464#define TOIE0   0
465#define OCIE0A  1
466
467#define TIMSK1  _SFR_MEM8(0x6F)
468#define TOIE1   0
469#define OCIE1A  1
470#define OCIE1B  2
471#define ICIE1   5
472
473#define TIMSK2  _SFR_MEM8(0x70)
474#define TOIE2   0
475#define OCIE2A  1
476
477/* Reserved [0x71..0x77] */
478
479/* Combine ADCL and ADCH */
480#ifndef __ASSEMBLER__
481#define ADC     _SFR_MEM16(0x78)
482#endif
483#define ADCW    _SFR_MEM16(0x78)
484#define ADCL    _SFR_MEM8(0x78)
485#define ADCH    _SFR_MEM8(0x79)
486
487#define ADCSRA  _SFR_MEM8(0x7A)
488#define ADPS0   0
489#define ADPS1   1
490#define ADPS2   2
491#define ADIE    3
492#define ADIF    4
493#define ADATE   5
494#define ADSC    6
495#define ADEN    7
496
497#define ADCSRB  _SFR_MEM8(0x7B)
498#define ADTS0   0
499#define ADTS1   1
500#define ADTS2   2
501#define ACME    6
502
503#define ADMUX   _SFR_MEM8(0x7C)
504#define MUX0    0
505#define MUX1    1
506#define MUX2    2
507#define MUX3    3
508#define MUX4    4
509#define ADLAR   5
510#define REFS0   6
511#define REFS1   7
512
513/* Reserved [0x7D] */
514
515#define DIDR0   _SFR_MEM8(0x7E)
516#define ADC0D   0
517#define ADC1D   1
518#define ADC2D   2
519#define ADC3D   3
520#define ADC4D   4
521#define ADC5D   5
522#define ADC6D   6
523#define ADC7D   7
524
525#define DIDR1   _SFR_MEM8(0x7F)
526#define AIN0D   0
527#define AIN1D   1
528
529#define TCCR1A  _SFR_MEM8(0X80)
530#define WGM10   0
531#define WGM11   1
532#define COM1B0  4
533#define COM1B1  5
534#define COM1A0  6
535#define COM1A1  7
536
537#define TCCR1B  _SFR_MEM8(0X81)
538#define CS10    0
539#define CS11    1
540#define CS12    2
541#define WGM12   3
542#define WGM13   4
543#define ICES1   6
544#define ICNC1   7
545
546#define TCCR1C  _SFR_MEM8(0x82)
547#define FOC1B   6
548#define FOC1A   7
549
550/* Reserved [0x83] */
551
552/* Combine TCNT1L and TCNT1H */
553#define TCNT1   _SFR_MEM16(0x84)
554
555#define TCNT1L  _SFR_MEM8(0x84)
556#define TCNT1H  _SFR_MEM8(0x85)
557
558/* Combine ICR1L and ICR1H */
559#define ICR1    _SFR_MEM16(0x86)
560
561#define ICR1L   _SFR_MEM8(0x86)
562#define ICR1H   _SFR_MEM8(0x87)
563
564/* Combine OCR1AL and OCR1AH */
565#define OCR1A   _SFR_MEM16(0x88)
566
567#define OCR1AL  _SFR_MEM8(0x88)
568#define OCR1AH  _SFR_MEM8(0x89)
569
570/* Combine OCR1BL and OCR1BH */
571#define OCR1B   _SFR_MEM16(0x8A)
572
573#define OCR1BL  _SFR_MEM8(0x8A)
574#define OCR1BH  _SFR_MEM8(0x8B)
575
576/* Reserved [0x8C..0xAF] */
577
578#define TCCR2A  _SFR_MEM8(0xB0)
579#define CS20    0
580#define CS21    1
581#define CS22    2
582#define WGM21   3
583#define COM2A0  4
584#define COM2A1  5
585#define WGM20   6
586#define FOC2A   7
587
588/* Reserved [0xB1] */
589
590#define TCNT2   _SFR_MEM8(0xB2)
591
592#define OCR2A   _SFR_MEM8(0xB3)
593
594/* Reserved [0xB4..0xB5] */
595
596#define ASSR    _SFR_MEM8(0xB6)
597#define TCR2UB  0
598#define OCR2UB  1
599#define TCN2UB  2
600#define AS2     3
601#define EXCLK   4
602
603/* Reserved [0xB7] */
604
605#define USICR   _SFR_MEM8(0xB8)
606#define USITC   0
607#define USICLK  1
608#define USICS0  2
609#define USICS1  3
610#define USIWM0  4
611#define USIWM1  5
612#define USIOIE  6
613#define USISIE  7
614
615#define USISR   _SFR_MEM8(0xB9)
616#define USICNT0 0
617#define USICNT1 1
618#define USICNT2 2
619#define USICNT3 3
620#define USIDC   4
621#define USIPF   5
622#define USIOIF  6
623#define USISIF  7
624
625#define USIDR   _SFR_MEM8(0xBA)
626
627/* Reserved [0xBB..0xBF] */
628
629#define UCSR0A  _SFR_MEM8(0xC0)
630#define MPCM0   0
631#define U2X0    1
632#define UPE0    2
633#define DOR0    3
634#define FE0     4
635#define UDRE0   5
636#define TXC0    6
637#define RXC0    7
638
639#define UCSR0B  _SFR_MEM8(0XC1)
640#define TXB80   0
641#define RXB80   1
642#define UCSZ02  2
643#define TXEN0   3
644#define RXEN0   4
645#define UDRIE0  5
646#define TXCIE0  6
647#define RXCIE0  7
648
649#define UCSR0C  _SFR_MEM8(0xC2)
650#define UCPOL0  0
651#define UCSZ00  1
652#define UCSZ01  2
653#define USBS0   3
654#define UPM00   4
655#define UPM01   5
656#define UMSEL0  6
657
658/* Reserved [0xC3] */
659
660/* Combine UBRR0L and UBRR0H */
661#define UBRR0   _SFR_MEM16(0xC4)
662
663#define UBRR0L  _SFR_MEM8(0xC4)
664#define UBRR0H  _SFR_MEM8(0xC5)
665
666#define UDR0    _SFR_MEM8(0XC6)
667
668/* Reserved [0xC7..0xE3] */
669
670#define LCDCRA  _SFR_MEM8(0XE4)
671#define LCDBL   0
672#define LCDIE   3
673#define LCDIF   4
674#define LCDAB   6
675#define LCDEN   7
676
677#define LCDCRB  _SFR_MEM8(0XE5)
678#define LCDPM0  0
679#define LCDPM1  1
680#define LCDPM2  2
681#define LCDMUX0 4
682#define LCDMUX1 5
683#define LCD2B   6
684#define LCDCS   7
685
686#define LCDFRR  _SFR_MEM8(0XE6)
687#define LCDCD0  0
688#define LCDCD1  1
689#define LCDCD2  2
690#define LCDPS0  4
691#define LCDPS1  5
692#define LCDPS2  6
693
694#define LCDCCR  _SFR_MEM8(0XE7)
695#define LCDCC0  0
696#define LCDCC1  1
697#define LCDCC2  2
698#define LCDCC3  3
699#define LCDDC0  5
700#define LCDDC1  6
701#define LCDDC2  7
702
703/* Reserved [0xE8..0xEB] */
704
705#define LCDDR00 _SFR_MEM8(0XEC)
706#define SEG000  0
707#define SEG001  1
708#define SEG002  2
709#define SEG003  3
710#define SEG004  4
711#define SEG005  5
712#define SEG006  6
713#define SEG007  7
714
715#define LCDDR01 _SFR_MEM8(0XED)
716#define SEG008  0
717#define SEG009  1
718#define SEG010  2
719#define SEG011  3
720#define SEG012  4
721#define SEG013  5
722#define SEG014  6
723#define SEG015  7
724
725#define LCDDR02 _SFR_MEM8(0XEE)
726#define SEG016  0
727#define SEG017  1
728#define SEG018  2
729#define SEG019  3
730#define SEG020  4
731#define SEG021  5
732#define SEG022  6
733#define SEG023  7
734
735#define LCDDR03 _SFR_MEM8(0XEF)
736#define SEG024  0
737
738/* Reserved [0xF0] */
739
740#define LCDDR05 _SFR_MEM8(0XF1)
741#define SEG100  0
742#define SEG101  1
743#define SEG102  2
744#define SEG103  3
745#define SEG104  4
746#define SEG105  5
747#define SEG106  6
748#define SEG107  7
749
750#define LCDDR06 _SFR_MEM8(0XF2)
751#define SEG108  0
752#define SEG109  1
753#define SEG110  2
754#define SEG111  3
755#define SEG112  4
756#define SEG113  5
757#define SEG114  6
758#define SEG115  7
759
760#define LCDDR07 _SFR_MEM8(0XF3)
761#define SEG116  0
762#define SEG117  1
763#define SEG118  2
764#define SEG119  3
765#define SEG120  4
766#define SEG121  5
767#define SEG122  6
768#define SEG123  7
769
770#define LCDDR08 _SFR_MEM8(0XF4)
771#define SEG124  0
772
773/* Reserved [0xF5] */
774
775#define LCDDR10 _SFR_MEM8(0XF6)
776#define SEG200  0
777#define SEG201  1
778#define SEG202  2
779#define SEG203  3
780#define SEG204  4
781#define SEG205  5
782#define SEG206  6
783#define SEG207  7
784
785#define LCDDR11 _SFR_MEM8(0XF7)
786#define SEG208  0
787#define SEG209  1
788#define SEG210  2
789#define SEG211  3
790#define SEG212  4
791#define SEG213  5
792#define SEG214  6
793#define SEG215  7
794
795#define LCDDR12 _SFR_MEM8(0XF8)
796#define SEG216  0
797#define SEG217  1
798#define SEG218  2
799#define SEG219  3
800#define SEG220  4
801#define SEG221  5
802#define SEG222  6
803#define SEG223  7
804
805#define LCDDR13 _SFR_MEM8(0XF9)
806#define SEG224  0
807
808/* Reserved [0xFA] */
809
810#define LCDDR15 _SFR_MEM8(0XFB)
811#define SEG300  0
812#define SEG301  1
813#define SEG302  2
814#define SEG303  3
815#define SEG304  4
816#define SEG305  5
817#define SEG306  6
818#define SEG307  7
819
820#define LCDDR16 _SFR_MEM8(0XFC)
821#define SEG308  0
822#define SEG309  1
823#define SEG310  2
824#define SEG311  3
825#define SEG312  4
826#define SEG313  5
827#define SEG314  6
828#define SEG315  7
829
830#define LCDDR17 _SFR_MEM8(0XFD)
831#define SEG316  0
832#define SEG217  1
833#define SEG318  2
834#define SEG319  3
835#define SEG320  4
836#define SEG321  5
837#define SEG322  6
838#define SEG323  7
839
840#define LCDDR18 _SFR_MEM8(0XFE)
841#define SEG324  0
842
843/* Reserved [0xFF] */
844
845/* Interrupt vectors */
846/* Vector 0 is the reset vector */
847/* External Interrupt Request 0 */
848#define INT0_vect                       _VECTOR(1)
849#define SIG_INTERRUPT0                  _VECTOR(1)
850
851/* Pin Change Interrupt Request 0 */
852#define PCINT0_vect                     _VECTOR(2)
853#define SIG_PIN_CHANGE0                 _VECTOR(2)
854
855/* Pin Change Interrupt Request 1 */
856#define PCINT1_vect                     _VECTOR(3)
857#define SIG_PIN_CHANGE1                 _VECTOR(3)
858
859/* Timer/Counter2 Compare Match */
860#define TIMER2_COMP_vect                _VECTOR(4)
861#define SIG_OUTPUT_COMPARE2             _VECTOR(4)
862
863/* Timer/Counter2 Overflow */
864#define TIMER2_OVF_vect                 _VECTOR(5)
865#define SIG_OVERFLOW2                   _VECTOR(5)
866
867/* Timer/Counter1 Capture Event */
868#define TIMER1_CAPT_vect                _VECTOR(6)
869#define SIG_INPUT_CAPTURE1              _VECTOR(6)
870
871/* Timer/Counter1 Compare Match A */
872#define TIMER1_COMPA_vect               _VECTOR(7)
873#define SIG_OUTPUT_COMPARE1A            _VECTOR(7)
874
875/* Timer/Counter Compare Match B */
876#define TIMER1_COMPB_vect               _VECTOR(8)
877#define SIG_OUTPUT_COMPARE1B            _VECTOR(8)
878
879/* Timer/Counter1 Overflow */
880#define TIMER1_OVF_vect                 _VECTOR(9)
881#define SIG_OVERFLOW1                   _VECTOR(9)
882
883/* Timer/Counter0 Compare Match */
884#define TIMER0_COMP_vect                _VECTOR(10)
885#define SIG_OUTPUT_COMPARE0             _VECTOR(10)
886
887/* Timer/Counter0 Overflow */
888#define TIMER0_OVF_vect                 _VECTOR(11)
889#define SIG_OVERFLOW0                   _VECTOR(11)
890
891/* SPI Serial Transfer Complete */
892#define SPI_STC_vect                    _VECTOR(12)
893#define SIG_SPI                         _VECTOR(12)
894
895/* USART0, Rx Complete */
896#define USART0_RX_vect                  _VECTOR(13)
897#define SIG_UART_RECV                   _VECTOR(13)
898
899/* USART0 Data register Empty */
900#define USART0_UDRE_vect                _VECTOR(14)
901#define SIG_UART_DATA                   _VECTOR(14)
902
903/* USART0, Tx Complete */
904#define USART0_TX_vect                  _VECTOR(15)
905#define SIG_UART_TRANS                  _VECTOR(15)
906
907/* USI Start Condition */
908#define USI_START_vect                  _VECTOR(16)
909#define SIG_USI_START                   _VECTOR(16)
910
911/* USI Overflow */
912#define USI_OVERFLOW_vect               _VECTOR(17)
913#define SIG_USI_OVERFLOW                _VECTOR(17)
914
915/* Analog Comparator */
916#define ANALOG_COMP_vect                _VECTOR(18)
917#define SIG_COMPARATOR                  _VECTOR(18)
918
919/* ADC Conversion Complete */
920#define ADC_vect                        _VECTOR(19)
921#define SIG_ADC                         _VECTOR(19)
922
923/* EEPROM Ready */
924#define EE_READY_vect                   _VECTOR(20)
925#define SIG_EEPROM_READY                _VECTOR(20)
926
927/* Store Program Memory Read */
928#define SPM_READY_vect                  _VECTOR(21)
929#define SIG_SPM_READY                   _VECTOR(21)
930
931/* LCD Start of Frame */
932#define LCD_vect                        _VECTOR(22)
933#define SIG_LCD                         _VECTOR(22)
934
935#define _VECTORS_SIZE 92
936
937
938/* Constants */
939#define SPM_PAGESIZE 256
940#define RAMEND       0x10FF
941#define XRAMEND      RAMEND
942#define E2END        0x7FF
943#define E2PAGESIZE   8
944#define FLASHEND     0xFFFF
945
946
947/* Fuses */
948
949#define FUSE_MEMORY_SIZE 3
950
951/* Low Fuse Byte */
952#define FUSE_CKSEL0      (unsigned char)~_BV(0)
953#define FUSE_CKSEL1      (unsigned char)~_BV(1)
954#define FUSE_CKSEL2      (unsigned char)~_BV(2)
955#define FUSE_CKSEL3      (unsigned char)~_BV(3)
956#define FUSE_SUT0        (unsigned char)~_BV(4)
957#define FUSE_SUT1        (unsigned char)~_BV(5)
958#define FUSE_CKOUT       (unsigned char)~_BV(6)
959#define FUSE_CKDIV8      (unsigned char)~_BV(7)
960#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
961
962/* High Fuse Byte */
963#define FUSE_BOOTRST     (unsigned char)~_BV(0)
964#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
965#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
966#define FUSE_EESAVE      (unsigned char)~_BV(3)
967#define FUSE_WDTON       (unsigned char)~_BV(4)
968#define FUSE_SPIEN       (unsigned char)~_BV(5)
969#define FUSE_JTAGEN      (unsigned char)~_BV(6)
970#define FUSE_OCDEN       (unsigned char)~_BV(7)
971#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
972
973/* Extended Fuse Byte */
974#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
975#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
976#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
977#define EFUSE_DEFAULT (0xFF)
978
979
980/* Lock Bits */
981#define __LOCK_BITS_EXIST
982#define __BOOT_LOCK_BITS_0_EXIST
983#define __BOOT_LOCK_BITS_1_EXIST
984
985
986/* Signature */
987#define SIGNATURE_0 0x1E
988#define SIGNATURE_1 0x96
989#define SIGNATURE_2 0x03
990
991
992#endif /* _AVR_IOM649_H_ */
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