source: rtems/cpukit/score/cpu/avr/avr/iom645.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 16.6 KB
Line 
1/* Copyright (c) 2004,2005,2006 Eric B. Weddington
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom645.h - definitions for ATmega645 */
34
35#ifndef _AVR_IOM645_H_
36#define _AVR_IOM645_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom645.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Registers and associated bit numbers */
51
52#define PINA    _SFR_IO8(0x00)
53#define PINA7   7
54#define PINA6   6
55#define PINA5   5
56#define PINA4   4
57#define PINA3   3
58#define PINA2   2
59#define PINA1   1
60#define PINA0   0
61
62#define DDRA    _SFR_IO8(0x01)
63#define DDA7    7
64#define DDA6    6
65#define DDA5    5
66#define DDA4    4
67#define DDA3    3
68#define DDA2    2
69#define DDA1    1
70#define DDA0    0
71
72#define PORTA   _SFR_IO8(0x02)
73#define PA7     7
74#define PA6     6
75#define PA5     5
76#define PA4     4
77#define PA3     3
78#define PA2     2
79#define PA1     1
80#define PA0     0
81
82#define PINB    _SFR_IO8(0x03)
83#define PINB7   7
84#define PINB6   6
85#define PINB5   5
86#define PINB4   4
87#define PINB3   3
88#define PINB2   2
89#define PINB1   1
90#define PINB0   0
91
92#define DDRB    _SFR_IO8(0x04)
93#define DDB7    7
94#define DDB6    6
95#define DDB5    5
96#define DDB4    4
97#define DDB3    3
98#define DDB2    2
99#define DDB1    1
100#define DDB0    0
101
102#define PORTB   _SFR_IO8(0x05)
103#define PB7     7
104#define PB6     6
105#define PB5     5
106#define PB4     4
107#define PB3     3
108#define PB2     2
109#define PB1     1
110#define PB0     0
111
112#define PINC    _SFR_IO8(0x06)
113#define PINC7   7
114#define PINC6   6
115#define PINC5   5
116#define PINC4   4
117#define PINC3   3
118#define PINC2   2
119#define PINC1   1
120#define PINC0   0
121
122#define DDRC    _SFR_IO8(0x07)
123#define DDC7    7
124#define DDC6    6
125#define DDC5    5
126#define DDC4    4
127#define DDC3    3
128#define DDC2    2
129#define DDC1    1
130#define DDC0    0
131
132#define PORTC   _SFR_IO8(0x08)
133#define PC7     7
134#define PC6     6
135#define PC5     5
136#define PC4     4
137#define PC3     3
138#define PC2     2
139#define PC1     1
140#define PC0     0
141
142#define PIND    _SFR_IO8(0x09)
143#define PIND7   7
144#define PIND6   6
145#define PIND5   5
146#define PIND4   4
147#define PIND3   3
148#define PIND2   2
149#define PIND1   1
150#define PIND0   0
151
152#define DDRD    _SFR_IO8(0x0A)
153#define DDD7    7
154#define DDD6    6
155#define DDD5    5
156#define DDD4    4
157#define DDD3    3
158#define DDD2    2
159#define DDD1    1
160#define DDD0    0
161
162#define PORTD   _SFR_IO8(0x0B)
163#define PD7     7
164#define PD6     6
165#define PD5     5
166#define PD4     4
167#define PD3     3
168#define PD2     2
169#define PD1     1
170#define PD0     0
171
172#define PINE    _SFR_IO8(0x0C)
173#define PINE7   7
174#define PINE6   6
175#define PINE5   5
176#define PINE4   4
177#define PINE3   3
178#define PINE2   2
179#define PINE1   1
180#define PINE0   0
181
182#define DDRE    _SFR_IO8(0x0D)
183#define DDE7    7
184#define DDE6    6
185#define DDE5    5
186#define DDE4    4
187#define DDE3    3
188#define DDE2    2
189#define DDE1    1
190#define DDE0    0
191
192#define PORTE   _SFR_IO8(0x0E)
193#define PE7     7
194#define PE6     6
195#define PE5     5
196#define PE4     4
197#define PE3     3
198#define PE2     2
199#define PE1     1
200#define PE0     0
201
202#define PINF    _SFR_IO8(0x0F)
203#define PINF7   7
204#define PINF6   6
205#define PINF5   5
206#define PINF4   4
207#define PINF3   3
208#define PINF2   2
209#define PINF1   1
210#define PINF0   0
211
212#define DDRF    _SFR_IO8(0x10)
213#define DDF7    7
214#define DDF6    6
215#define DDF5    5
216#define DDF4    4
217#define DDF3    3
218#define DDF2    2
219#define DDF1    1
220#define DDF0    0
221
222#define PORTF   _SFR_IO8(0x11)
223#define PF7     7
224#define PF6     6
225#define PF5     5
226#define PF4     4
227#define PF3     3
228#define PF2     2
229#define PF1     1
230#define PF0     0
231
232#define PING    _SFR_IO8(0x12)
233#define PING5   5
234#define PING4   4
235#define PING3   3
236#define PING2   2
237#define PING1   1
238#define PING0   0
239
240#define DDRG    _SFR_IO8(0x13)
241#define DDG4    4
242#define DDG3    3
243#define DDG2    2
244#define DDG1    1
245#define DDG0    0
246
247#define PORTG   _SFR_IO8(0x14)
248#define PG4     4
249#define PG3     3
250#define PG2     2
251#define PG1     1
252#define PG0     0
253
254#define TIFR0   _SFR_IO8(0x15)
255#define TOV0    0
256#define OCF0A   1
257
258#define TIFR1   _SFR_IO8(0x16)
259#define TOV1    0
260#define OCF1A   1
261#define OCF1B   2
262#define ICF1    5
263
264#define TIFR2   _SFR_IO8(0x17)
265#define TOV2    0
266#define OCF2A   1
267
268/* Reserved [0x18..0x1B] */
269
270#define EIFR   _SFR_IO8(0x1C)
271#define INTF0   0
272#define PCIF0   4
273#define PCIF1   5
274
275#define EIMSK   _SFR_IO8(0x1D)
276#define INT0    0
277#define PCIE0   4
278#define PCIE1   5
279
280#define GPIOR0  _SFR_IO8(0x1E)
281
282#define EECR    _SFR_IO8(0x1F)
283#define EERE    0
284#define EEWE    1
285#define EEMWE   2
286#define EERIE   3
287
288#define EEDR    _SFR_IO8(0X20)
289
290/* Combine EEARL and EEARH */
291#define EEAR    _SFR_IO16(0x21)
292#define EEARL   _SFR_IO8(0x21)
293#define EEARH   _SFR_IO8(0X22)
294
295/* 6-char sequence denoting where to find the EEPROM registers in memory space.
296   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
297   subroutines.
298   First two letters:  EECR address.
299   Second two letters: EEDR address.
300   Last two letters:   EEAR address.  */
301#define __EEPROM_REG_LOCATIONS__ 1F2021
302
303#define GTCCR   _SFR_IO8(0x23)
304#define PSR10   0
305#define PSR2    1
306#define TSM     7
307
308#define TCCR0A  _SFR_IO8(0x24)
309#define CS00    0
310#define CS01    1
311#define CS02    2
312#define WGM01   3
313#define COM0A0  4
314#define COM0A1  5
315#define WGM00   6
316#define FOC0A   7
317
318/* Reserved [0x25] */
319
320#define TCNT0   _SFR_IO8(0X26)
321
322#define OCR0A   _SFR_IO8(0X27)
323
324/* Reserved [0x28..0x29] */
325
326#define GPIOR1  _SFR_IO8(0x2A)
327
328#define GPIOR2  _SFR_IO8(0x2B)
329
330#define SPCR    _SFR_IO8(0x2C)
331#define SPR0    0
332#define SPR1    1
333#define CPHA    2
334#define CPOL    3
335#define MSTR    4
336#define DORD    5
337#define SPE     6
338#define SPIE    7
339
340#define SPSR    _SFR_IO8(0x2D)
341#define SPI2X   0
342#define WCOL    6
343#define SPIF    7
344
345#define SPDR    _SFR_IO8(0X2E)
346
347/* Reserved [0x2F] */
348
349#define ACSR    _SFR_IO8(0x30)
350#define ACIS0   0
351#define ACIS1   1
352#define ACIC    2
353#define ACIE    3
354#define ACI     4
355#define ACO     5
356#define ACBG    6
357#define ACD     7
358
359#define OCDR    _SFR_IO8(0x31)
360#define OCDR0   0
361#define OCDR1   1
362#define OCDR2   2
363#define OCDR3   3
364#define OCDR4   4
365#define OCDR5   5
366#define OCDR6   6
367#define OCDR7   7
368#define IDRD    7
369
370/* Reserved [0x32] */
371
372#define SMCR    _SFR_IO8(0x33)
373#define SE      0
374#define SM0     1
375#define SM1     2
376#define SM2     3
377
378#define MCUSR   _SFR_IO8(0x34)
379#define PORF    0
380#define EXTRF   1
381#define BORF    2
382#define WDRF    3
383#define JTRF    4
384
385#define MCUCR   _SFR_IO8(0X35)
386#define IVCE    0
387#define IVSEL   1
388#define PUD     4
389#define JTD     7
390
391/* Reserved [0x36] */
392
393#define SPMCSR  _SFR_IO8(0x37)
394#define SPMEN   0
395#define PGERS   1
396#define PGWRT   2
397#define BLBSET  3
398#define RWWSRE  4
399#define RWWSB   6
400#define SPMIE   7
401
402/* Reserved [0x38..0x3C] */
403
404/* SP [0x3D..0x3E] */
405/* SREG [0x3F] */
406
407#define WDTCR   _SFR_MEM8(0x60)
408#define WDP0    0
409#define WDP1    1
410#define WDP2    2
411#define WDE     3
412#define WDCE    4
413
414#define CLKPR   _SFR_MEM8(0x61)
415#define CLKPS0  0
416#define CLKPS1  1
417#define CLKPS2  2
418#define CLKPS3  3
419#define CLKPCE  7
420
421/* Reserved [0x62..0x63] */
422
423#define PRR     _SFR_MEM8(0x64)
424#define PRADC       0
425#define PRUSART0    1
426#define PRSPI       2
427#define PRTIM1      3
428
429/* Reserved [0x65] */
430
431#define OSCCAL  _SFR_MEM8(0x66)
432
433/* Reserved [0x67..0x68] */
434
435#define EICRA   _SFR_MEM8(0x69)
436#define ISC00   0
437#define ISC01   1
438
439/* Reserved [0x6A] */
440
441#define PCMSK0  _SFR_MEM8(0x6B)
442#define PCINT0  0
443#define PCINT1  1
444#define PCINT2  2
445#define PCINT3  3
446#define PCINT4  4
447#define PCINT5  5
448#define PCINT6  6
449#define PCINT7  7
450
451#define PCMSK1  _SFR_MEM8(0x6C)
452#define PCINT8  0
453#define PCINT9  1
454#define PCINT10 2
455#define PCINT11 3
456#define PCINT12 4
457#define PCINT13 5
458#define PCINT14 6
459#define PCINT15 7
460
461/* Reserved [0x6D] */
462
463#define TIMSK0  _SFR_MEM8(0x6E)
464#define TOIE0   0
465#define OCIE0A  1
466
467#define TIMSK1  _SFR_MEM8(0x6F)
468#define TOIE1   0
469#define OCIE1A  1
470#define OCIE1B  2
471#define ICIE1   5
472
473#define TIMSK2  _SFR_MEM8(0x70)
474#define TOIE2   0
475#define OCIE2A  1
476
477/* Reserved [0x71..0x77] */
478
479/* Combine ADCL and ADCH */
480#ifndef __ASSEMBLER__
481#define ADC     _SFR_MEM16(0x78)
482#endif
483#define ADCW    _SFR_MEM16(0x78)
484#define ADCL    _SFR_MEM8(0x78)
485#define ADCH    _SFR_MEM8(0x79)
486
487#define ADCSRA  _SFR_MEM8(0x7A)
488#define ADPS0   0
489#define ADPS1   1
490#define ADPS2   2
491#define ADIE    3
492#define ADIF    4
493#define ADATE   5
494#define ADSC    6
495#define ADEN    7
496
497#define ADCSRB  _SFR_MEM8(0x7B)
498#define ADTS0   0
499#define ADTS1   1
500#define ADTS2   2
501#define ACME    6
502
503#define ADMUX   _SFR_MEM8(0x7C)
504#define MUX0    0
505#define MUX1    1
506#define MUX2    2
507#define MUX3    3
508#define MUX4    4
509#define ADLAR   5
510#define REFS0   6
511#define REFS1   7
512
513/* Reserved [0x7D] */
514
515#define DIDR0   _SFR_MEM8(0x7E)
516#define ADC0D   0
517#define ADC1D   1
518#define ADC2D   2
519#define ADC3D   3
520#define ADC4D   4
521#define ADC5D   5
522#define ADC6D   6
523#define ADC7D   7
524
525#define DIDR1   _SFR_MEM8(0x7F)
526#define AIN0D   0
527#define AIN1D   1
528
529#define TCCR1A  _SFR_MEM8(0X80)
530#define WGM10   0
531#define WGM11   1
532#define COM1B0  4
533#define COM1B1  5
534#define COM1A0  6
535#define COM1A1  7
536
537#define TCCR1B  _SFR_MEM8(0X81)
538#define CS10    0
539#define CS11    1
540#define CS12    2
541#define WGM12   3
542#define WGM13   4
543#define ICES1   6
544#define ICNC1   7
545
546#define TCCR1C  _SFR_MEM8(0x82)
547#define FOC1B   6
548#define FOC1A   7
549
550/* Reserved [0x83] */
551
552/* Combine TCNT1L and TCNT1H */
553#define TCNT1   _SFR_MEM16(0x84)
554
555#define TCNT1L  _SFR_MEM8(0x84)
556#define TCNT1H  _SFR_MEM8(0x85)
557
558/* Combine ICR1L and ICR1H */
559#define ICR1    _SFR_MEM16(0x86)
560
561#define ICR1L   _SFR_MEM8(0x86)
562#define ICR1H   _SFR_MEM8(0x87)
563
564/* Combine OCR1AL and OCR1AH */
565#define OCR1A   _SFR_MEM16(0x88)
566
567#define OCR1AL  _SFR_MEM8(0x88)
568#define OCR1AH  _SFR_MEM8(0x89)
569
570/* Combine OCR1BL and OCR1BH */
571#define OCR1B   _SFR_MEM16(0x8A)
572
573#define OCR1BL  _SFR_MEM8(0x8A)
574#define OCR1BH  _SFR_MEM8(0x8B)
575
576/* Reserved [0x8C..0xAF] */
577
578#define TCCR2A  _SFR_MEM8(0xB0)
579#define CS20    0
580#define CS21    1
581#define CS22    2
582#define WGM21   3
583#define COM2A0  4
584#define COM2A1  5
585#define WGM20   6
586#define FOC2A   7
587
588/* Reserved [0xB1] */
589
590#define TCNT2   _SFR_MEM8(0xB2)
591
592#define OCR2A   _SFR_MEM8(0xB3)
593
594/* Reserved [0xB4..0xB5] */
595
596#define ASSR    _SFR_MEM8(0xB6)
597#define TCR2UB  0
598#define OCR2UB  1
599#define TCN2UB  2
600#define AS2     3
601#define EXCLK   4
602
603/* Reserved [0xB7] */
604
605#define USICR   _SFR_MEM8(0xB8)
606#define USITC   0
607#define USICLK  1
608#define USICS0  2
609#define USICS1  3
610#define USIWM0  4
611#define USIWM1  5
612#define USIOIE  6
613#define USISIE  7
614
615#define USISR   _SFR_MEM8(0xB9)
616#define USICNT0 0
617#define USICNT1 1
618#define USICNT2 2
619#define USICNT3 3
620#define USIDC   4
621#define USIPF   5
622#define USIOIF  6
623#define USISIF  7
624
625#define USIDR   _SFR_MEM8(0xBA)
626
627/* Reserved [0xBB..0xBF] */
628
629#define UCSR0A  _SFR_MEM8(0xC0)
630#define MPCM0   0
631#define U2X0    1
632#define UPE0    2
633#define DOR0    3
634#define FE0     4
635#define UDRE0   5
636#define TXC0    6
637#define RXC0    7
638
639#define UCSR0B  _SFR_MEM8(0XC1)
640#define TXB80   0
641#define RXB80   1
642#define UCSZ02  2
643#define TXEN0   3
644#define RXEN0   4
645#define UDRIE0  5
646#define TXCIE0  6
647#define RXCIE0  7
648
649#define UCSR0C  _SFR_MEM8(0xC2)
650#define UCPOL0  0
651#define UCSZ00  1
652#define UCSZ01  2
653#define USBS0   3
654#define UPM00   4
655#define UPM01   5
656#define UMSEL0  6
657
658/* Reserved [0xC3] */
659
660/* Combine UBRR0L and UBRR0H */
661#define UBRR0   _SFR_MEM16(0xC4)
662
663#define UBRR0L  _SFR_MEM8(0xC4)
664#define UBRR0H  _SFR_MEM8(0xC5)
665
666#define UDR0    _SFR_MEM8(0XC6)
667
668/* Reserved [0xC7..0xFF] */
669
670
671/* Interrupt vectors */
672/* Vector 0 is the reset vector */
673/* External Interrupt Request 0 */
674#define INT0_vect                       _VECTOR(1)
675#define SIG_INTERRUPT0                  _VECTOR(1)
676
677/* Pin Change Interrupt Request 0 */
678#define PCINT0_vect                     _VECTOR(2)
679#define SIG_PIN_CHANGE0                 _VECTOR(2)
680
681/* Pin Change Interrupt Request 1 */
682#define PCINT1_vect                     _VECTOR(3)
683#define SIG_PIN_CHANGE1                 _VECTOR(3)
684
685/* Timer/Counter2 Compare Match */
686#define TIMER2_COMP_vect                _VECTOR(4)
687#define SIG_OUTPUT_COMPARE2             _VECTOR(4)
688
689/* Timer/Counter2 Overflow */
690#define TIMER2_OVF_vect                 _VECTOR(5)
691#define SIG_OVERFLOW2                   _VECTOR(5)
692
693/* Timer/Counter1 Capture Event */
694#define TIMER1_CAPT_vect                _VECTOR(6)
695#define SIG_INPUT_CAPTURE1              _VECTOR(6)
696
697/* Timer/Counter1 Compare Match A */
698#define TIMER1_COMPA_vect               _VECTOR(7)
699#define SIG_OUTPUT_COMPARE1A            _VECTOR(7)
700
701/* Timer/Counter Compare Match B */
702#define TIMER1_COMPB_vect               _VECTOR(8)
703#define SIG_OUTPUT_COMPARE1B            _VECTOR(8)
704
705/* Timer/Counter1 Overflow */
706#define TIMER1_OVF_vect                 _VECTOR(9)
707#define SIG_OVERFLOW1                   _VECTOR(9)
708
709/* Timer/Counter0 Compare Match */
710#define TIMER0_COMP_vect                _VECTOR(10)
711#define SIG_OUTPUT_COMPARE0             _VECTOR(10)
712
713/* Timer/Counter0 Overflow */
714#define TIMER0_OVF_vect                 _VECTOR(11)
715#define SIG_OVERFLOW0                   _VECTOR(11)
716
717/* SPI Serial Transfer Complete */
718#define SPI_STC_vect                    _VECTOR(12)
719#define SIG_SPI                         _VECTOR(12)
720
721/* USART0, Rx Complete */
722#define USART0_RX_vect                  _VECTOR(13)
723#define SIG_UART_RECV                   _VECTOR(13)
724
725/* USART0 Data register Empty */
726#define USART0_UDRE_vect                _VECTOR(14)
727#define SIG_UART_DATA                   _VECTOR(14)
728
729/* USART0, Tx Complete */
730#define USART0_TX_vect                  _VECTOR(15)
731#define SIG_UART_TRANS                  _VECTOR(15)
732
733/* USI Start Condition */
734#define USI_START_vect                  _VECTOR(16)
735#define SIG_USI_START                   _VECTOR(16)
736
737/* USI Overflow */
738#define USI_OVERFLOW_vect               _VECTOR(17)
739#define SIG_USI_OVERFLOW                _VECTOR(17)
740
741/* Analog Comparator */
742#define ANALOG_COMP_vect                _VECTOR(18)
743#define SIG_COMPARATOR                  _VECTOR(18)
744
745/* ADC Conversion Complete */
746#define ADC_vect                        _VECTOR(19)
747#define SIG_ADC                         _VECTOR(19)
748
749/* EEPROM Ready */
750#define EE_READY_vect                   _VECTOR(20)
751#define SIG_EEPROM_READY                _VECTOR(20)
752
753/* Store Program Memory Read */
754#define SPM_READY_vect                  _VECTOR(21)
755#define SIG_SPM_READY                   _VECTOR(21)
756
757/* Vector 22 is Reserved */
758
759#define _VECTORS_SIZE 92
760
761
762/* Constants */
763#define SPM_PAGESIZE 256
764#define RAMEND       0x10FF
765#define XRAMEND      RAMEND
766#define E2END        0x7FF
767#define E2PAGESIZE   8
768#define FLASHEND     0xFFFF
769
770
771/* Fuses */
772
773#define FUSE_MEMORY_SIZE 3
774
775/* Low Fuse Byte */
776#define FUSE_CKSEL0      (unsigned char)~_BV(0)
777#define FUSE_CKSEL1      (unsigned char)~_BV(1)
778#define FUSE_CKSEL2      (unsigned char)~_BV(2)
779#define FUSE_CKSEL3      (unsigned char)~_BV(3)
780#define FUSE_SUT0        (unsigned char)~_BV(4)
781#define FUSE_SUT1        (unsigned char)~_BV(5)
782#define FUSE_CKOUT       (unsigned char)~_BV(6)
783#define FUSE_CKDIV8      (unsigned char)~_BV(7)
784#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
785
786/* High Fuse Byte */
787#define FUSE_BOOTRST     (unsigned char)~_BV(0)
788#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
789#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
790#define FUSE_EESAVE      (unsigned char)~_BV(3)
791#define FUSE_WDTON       (unsigned char)~_BV(4)
792#define FUSE_SPIEN       (unsigned char)~_BV(5)
793#define FUSE_JTAGEN      (unsigned char)~_BV(6)
794#define FUSE_OCDEN       (unsigned char)~_BV(7)
795#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
796
797/* Extended Fuse Byte */
798#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
799#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
800#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
801#define EFUSE_DEFAULT (0xFF)
802
803
804/* Lock Bits */
805#define __LOCK_BITS_EXIST
806#define __BOOT_LOCK_BITS_0_EXIST
807#define __BOOT_LOCK_BITS_1_EXIST
808
809
810/* Signature */
811#define SIGNATURE_0 0x1E
812#define SIGNATURE_1 0x96
813#define SIGNATURE_2 0x05
814
815
816#endif /* _AVR_IOM645_H_ */
Note: See TracBrowser for help on using the repository browser.