| 1 | /* Copyright (c) 2002, Steinar Haugen |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/iom64.h - defines for ATmega64 |
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| 34 | |
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| 35 | As of 2002-11-23: |
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| 36 | - This should be up to date with data sheet Rev. 2490C-AVR-09/02 */ |
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| 37 | |
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| 38 | #ifndef _AVR_IOM64_H_ |
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| 39 | #define _AVR_IOM64_H_ 1 |
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| 40 | |
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| 41 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 42 | |
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| 43 | #ifndef _AVR_IO_H_ |
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| 44 | # error "Include <avr/io.h> instead of this file." |
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| 45 | #endif |
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| 46 | |
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| 47 | #ifndef _AVR_IOXXX_H_ |
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| 48 | # define _AVR_IOXXX_H_ "iom64.h" |
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| 49 | #else |
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| 50 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 51 | #endif |
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| 52 | |
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| 53 | /* I/O registers */ |
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| 54 | |
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| 55 | /* Input Pins, Port F */ |
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| 56 | #define PINF _SFR_IO8(0x00) |
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| 57 | |
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| 58 | /* Input Pins, Port E */ |
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| 59 | #define PINE _SFR_IO8(0x01) |
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| 60 | |
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| 61 | /* Data Direction Register, Port E */ |
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| 62 | #define DDRE _SFR_IO8(0x02) |
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| 63 | |
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| 64 | /* Data Register, Port E */ |
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| 65 | #define PORTE _SFR_IO8(0x03) |
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| 66 | |
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| 67 | /* ADC Data Register */ |
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| 68 | #define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ |
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| 69 | #ifndef __ASSEMBLER__ |
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| 70 | #define ADC _SFR_IO16(0x04) |
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| 71 | #endif |
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| 72 | #define ADCL _SFR_IO8(0x04) |
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| 73 | #define ADCH _SFR_IO8(0x05) |
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| 74 | |
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| 75 | /* ADC Control and Status Register A */ |
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| 76 | #define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ |
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| 77 | #define ADCSRA _SFR_IO8(0x06) |
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| 78 | |
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| 79 | /* ADC Multiplexer select */ |
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| 80 | #define ADMUX _SFR_IO8(0x07) |
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| 81 | |
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| 82 | /* Analog Comparator Control and Status Register */ |
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| 83 | #define ACSR _SFR_IO8(0x08) |
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| 84 | |
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| 85 | /* USART0 Baud Rate Register Low */ |
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| 86 | #define UBRR0L _SFR_IO8(0x09) |
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| 87 | |
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| 88 | /* USART0 Control and Status Register B */ |
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| 89 | #define UCSR0B _SFR_IO8(0x0A) |
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| 90 | |
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| 91 | /* USART0 Control and Status Register A */ |
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| 92 | #define UCSR0A _SFR_IO8(0x0B) |
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| 93 | |
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| 94 | /* USART0 I/O Data Register */ |
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| 95 | #define UDR0 _SFR_IO8(0x0C) |
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| 96 | |
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| 97 | /* SPI Control Register */ |
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| 98 | #define SPCR _SFR_IO8(0x0D) |
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| 99 | |
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| 100 | /* SPI Status Register */ |
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| 101 | #define SPSR _SFR_IO8(0x0E) |
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| 102 | |
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| 103 | /* SPI I/O Data Register */ |
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| 104 | #define SPDR _SFR_IO8(0x0F) |
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| 105 | |
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| 106 | /* Input Pins, Port D */ |
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| 107 | #define PIND _SFR_IO8(0x10) |
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| 108 | |
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| 109 | /* Data Direction Register, Port D */ |
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| 110 | #define DDRD _SFR_IO8(0x11) |
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| 111 | |
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| 112 | /* Data Register, Port D */ |
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| 113 | #define PORTD _SFR_IO8(0x12) |
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| 114 | |
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| 115 | /* Input Pins, Port C */ |
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| 116 | #define PINC _SFR_IO8(0x13) |
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| 117 | |
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| 118 | /* Data Direction Register, Port C */ |
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| 119 | #define DDRC _SFR_IO8(0x14) |
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| 120 | |
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| 121 | /* Data Register, Port C */ |
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| 122 | #define PORTC _SFR_IO8(0x15) |
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| 123 | |
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| 124 | /* Input Pins, Port B */ |
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| 125 | #define PINB _SFR_IO8(0x16) |
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| 126 | |
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| 127 | /* Data Direction Register, Port B */ |
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| 128 | #define DDRB _SFR_IO8(0x17) |
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| 129 | |
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| 130 | /* Data Register, Port B */ |
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| 131 | #define PORTB _SFR_IO8(0x18) |
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| 132 | |
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| 133 | /* Input Pins, Port A */ |
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| 134 | #define PINA _SFR_IO8(0x19) |
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| 135 | |
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| 136 | /* Data Direction Register, Port A */ |
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| 137 | #define DDRA _SFR_IO8(0x1A) |
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| 138 | |
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| 139 | /* Data Register, Port A */ |
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| 140 | #define PORTA _SFR_IO8(0x1B) |
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| 141 | |
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| 142 | /* EEPROM Control Register */ |
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| 143 | #define EECR _SFR_IO8(0x1C) |
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| 144 | |
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| 145 | /* EEPROM Data Register */ |
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| 146 | #define EEDR _SFR_IO8(0x1D) |
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| 147 | |
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| 148 | /* EEPROM Address Register */ |
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| 149 | #define EEAR _SFR_IO16(0x1E) |
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| 150 | #define EEARL _SFR_IO8(0x1E) |
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| 151 | #define EEARH _SFR_IO8(0x1F) |
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| 152 | |
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| 153 | /* Special Function I/O Register */ |
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| 154 | #define SFIOR _SFR_IO8(0x20) |
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| 155 | |
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| 156 | /* Watchdog Timer Control Register */ |
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| 157 | #define WDTCR _SFR_IO8(0x21) |
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| 158 | |
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| 159 | /* On-chip Debug Register */ |
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| 160 | #define OCDR _SFR_IO8(0x22) |
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| 161 | |
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| 162 | /* Timer2 Output Compare Register */ |
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| 163 | #define OCR2 _SFR_IO8(0x23) |
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| 164 | |
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| 165 | /* Timer/Counter 2 */ |
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| 166 | #define TCNT2 _SFR_IO8(0x24) |
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| 167 | |
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| 168 | /* Timer/Counter 2 Control register */ |
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| 169 | #define TCCR2 _SFR_IO8(0x25) |
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| 170 | |
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| 171 | /* T/C 1 Input Capture Register */ |
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| 172 | #define ICR1 _SFR_IO16(0x26) |
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| 173 | #define ICR1L _SFR_IO8(0x26) |
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| 174 | #define ICR1H _SFR_IO8(0x27) |
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| 175 | |
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| 176 | /* Timer/Counter1 Output Compare Register B */ |
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| 177 | #define OCR1B _SFR_IO16(0x28) |
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| 178 | #define OCR1BL _SFR_IO8(0x28) |
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| 179 | #define OCR1BH _SFR_IO8(0x29) |
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| 180 | |
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| 181 | /* Timer/Counter1 Output Compare Register A */ |
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| 182 | #define OCR1A _SFR_IO16(0x2A) |
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| 183 | #define OCR1AL _SFR_IO8(0x2A) |
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| 184 | #define OCR1AH _SFR_IO8(0x2B) |
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| 185 | |
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| 186 | /* Timer/Counter 1 */ |
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| 187 | #define TCNT1 _SFR_IO16(0x2C) |
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| 188 | #define TCNT1L _SFR_IO8(0x2C) |
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| 189 | #define TCNT1H _SFR_IO8(0x2D) |
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| 190 | |
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| 191 | /* Timer/Counter 1 Control and Status Register */ |
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| 192 | #define TCCR1B _SFR_IO8(0x2E) |
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| 193 | |
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| 194 | /* Timer/Counter 1 Control Register */ |
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| 195 | #define TCCR1A _SFR_IO8(0x2F) |
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| 196 | |
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| 197 | /* Timer/Counter 0 Asynchronous Control & Status Register */ |
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| 198 | #define ASSR _SFR_IO8(0x30) |
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| 199 | |
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| 200 | /* Output Compare Register 0 */ |
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| 201 | #define OCR0 _SFR_IO8(0x31) |
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| 202 | |
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| 203 | /* Timer/Counter 0 */ |
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| 204 | #define TCNT0 _SFR_IO8(0x32) |
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| 205 | |
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| 206 | /* Timer/Counter 0 Control Register */ |
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| 207 | #define TCCR0 _SFR_IO8(0x33) |
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| 208 | |
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| 209 | /* MCU Status Register */ |
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| 210 | #define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ |
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| 211 | #define MCUCSR _SFR_IO8(0x34) |
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| 212 | |
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| 213 | /* MCU general Control Register */ |
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| 214 | #define MCUCR _SFR_IO8(0x35) |
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| 215 | |
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| 216 | /* Timer/Counter Interrupt Flag Register */ |
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| 217 | #define TIFR _SFR_IO8(0x36) |
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| 218 | |
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| 219 | /* Timer/Counter Interrupt MaSK register */ |
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| 220 | #define TIMSK _SFR_IO8(0x37) |
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| 221 | |
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| 222 | /* External Interrupt Flag Register */ |
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| 223 | #define EIFR _SFR_IO8(0x38) |
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| 224 | |
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| 225 | /* External Interrupt MaSK register */ |
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| 226 | #define EIMSK _SFR_IO8(0x39) |
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| 227 | |
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| 228 | /* External Interrupt Control Register B */ |
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| 229 | #define EICRB _SFR_IO8(0x3A) |
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| 230 | |
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| 231 | /* XDIV Divide control register */ |
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| 232 | #define XDIV _SFR_IO8(0x3C) |
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| 233 | |
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| 234 | /* 0x3D..0x3E SP */ |
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| 235 | |
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| 236 | /* 0x3F SREG */ |
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| 237 | |
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| 238 | /* Extended I/O registers */ |
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| 239 | |
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| 240 | /* Data Direction Register, Port F */ |
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| 241 | #define DDRF _SFR_MEM8(0x61) |
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| 242 | |
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| 243 | /* Data Register, Port F */ |
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| 244 | #define PORTF _SFR_MEM8(0x62) |
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| 245 | |
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| 246 | /* Input Pins, Port G */ |
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| 247 | #define PING _SFR_MEM8(0x63) |
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| 248 | |
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| 249 | /* Data Direction Register, Port G */ |
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| 250 | #define DDRG _SFR_MEM8(0x64) |
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| 251 | |
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| 252 | /* Data Register, Port G */ |
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| 253 | #define PORTG _SFR_MEM8(0x65) |
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| 254 | |
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| 255 | /* Store Program Memory Control and Status Register */ |
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| 256 | #define SPMCR _SFR_MEM8(0x68) |
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| 257 | #define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ |
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| 258 | |
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| 259 | /* External Interrupt Control Register A */ |
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| 260 | #define EICRA _SFR_MEM8(0x6A) |
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| 261 | |
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| 262 | /* External Memory Control Register B */ |
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| 263 | #define XMCRB _SFR_MEM8(0x6C) |
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| 264 | |
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| 265 | /* External Memory Control Register A */ |
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| 266 | #define XMCRA _SFR_MEM8(0x6D) |
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| 267 | |
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| 268 | /* Oscillator Calibration Register */ |
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| 269 | #define OSCCAL _SFR_MEM8(0x6F) |
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| 270 | |
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| 271 | /* 2-wire Serial Interface Bit Rate Register */ |
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| 272 | #define TWBR _SFR_MEM8(0x70) |
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| 273 | |
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| 274 | /* 2-wire Serial Interface Status Register */ |
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| 275 | #define TWSR _SFR_MEM8(0x71) |
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| 276 | |
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| 277 | /* 2-wire Serial Interface Address Register */ |
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| 278 | #define TWAR _SFR_MEM8(0x72) |
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| 279 | |
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| 280 | /* 2-wire Serial Interface Data Register */ |
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| 281 | #define TWDR _SFR_MEM8(0x73) |
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| 282 | |
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| 283 | /* 2-wire Serial Interface Control Register */ |
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| 284 | #define TWCR _SFR_MEM8(0x74) |
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| 285 | |
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| 286 | /* Time Counter 1 Output Compare Register C */ |
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| 287 | #define OCR1C _SFR_MEM16(0x78) |
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| 288 | #define OCR1CL _SFR_MEM8(0x78) |
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| 289 | #define OCR1CH _SFR_MEM8(0x79) |
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| 290 | |
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| 291 | /* Timer/Counter 1 Control Register C */ |
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| 292 | #define TCCR1C _SFR_MEM8(0x7A) |
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| 293 | |
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| 294 | /* Extended Timer Interrupt Flag Register */ |
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| 295 | #define ETIFR _SFR_MEM8(0x7C) |
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| 296 | |
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| 297 | /* Extended Timer Interrupt Mask Register */ |
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| 298 | #define ETIMSK _SFR_MEM8(0x7D) |
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| 299 | |
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| 300 | /* Timer/Counter 3 Input Capture Register */ |
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| 301 | #define ICR3 _SFR_MEM16(0x80) |
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| 302 | #define ICR3L _SFR_MEM8(0x80) |
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| 303 | #define ICR3H _SFR_MEM8(0x81) |
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| 304 | |
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| 305 | /* Timer/Counter 3 Output Compare Register C */ |
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| 306 | #define OCR3C _SFR_MEM16(0x82) |
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| 307 | #define OCR3CL _SFR_MEM8(0x82) |
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| 308 | #define OCR3CH _SFR_MEM8(0x83) |
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| 309 | |
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| 310 | /* Timer/Counter 3 Output Compare Register B */ |
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| 311 | #define OCR3B _SFR_MEM16(0x84) |
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| 312 | #define OCR3BL _SFR_MEM8(0x84) |
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| 313 | #define OCR3BH _SFR_MEM8(0x85) |
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| 314 | |
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| 315 | /* Timer/Counter 3 Output Compare Register A */ |
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| 316 | #define OCR3A _SFR_MEM16(0x86) |
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| 317 | #define OCR3AL _SFR_MEM8(0x86) |
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| 318 | #define OCR3AH _SFR_MEM8(0x87) |
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| 319 | |
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| 320 | /* Timer/Counter 3 Counter Register */ |
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| 321 | #define TCNT3 _SFR_MEM16(0x88) |
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| 322 | #define TCNT3L _SFR_MEM8(0x88) |
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| 323 | #define TCNT3H _SFR_MEM8(0x89) |
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| 324 | |
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| 325 | /* Timer/Counter 3 Control Register B */ |
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| 326 | #define TCCR3B _SFR_MEM8(0x8A) |
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| 327 | |
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| 328 | /* Timer/Counter 3 Control Register A */ |
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| 329 | #define TCCR3A _SFR_MEM8(0x8B) |
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| 330 | |
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| 331 | /* Timer/Counter 3 Control Register C */ |
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| 332 | #define TCCR3C _SFR_MEM8(0x8C) |
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| 333 | |
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| 334 | /* ADC Control and Status Register B */ |
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| 335 | #define ADCSRB _SFR_MEM8(0x8E) |
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| 336 | |
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| 337 | /* USART0 Baud Rate Register High */ |
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| 338 | #define UBRR0H _SFR_MEM8(0x90) |
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| 339 | |
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| 340 | /* USART0 Control and Status Register C */ |
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| 341 | #define UCSR0C _SFR_MEM8(0x95) |
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| 342 | |
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| 343 | /* USART1 Baud Rate Register High */ |
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| 344 | #define UBRR1H _SFR_MEM8(0x98) |
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| 345 | |
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| 346 | /* USART1 Baud Rate Register Low*/ |
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| 347 | #define UBRR1L _SFR_MEM8(0x99) |
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| 348 | |
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| 349 | /* USART1 Control and Status Register B */ |
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| 350 | #define UCSR1B _SFR_MEM8(0x9A) |
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| 351 | |
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| 352 | /* USART1 Control and Status Register A */ |
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| 353 | #define UCSR1A _SFR_MEM8(0x9B) |
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| 354 | |
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| 355 | /* USART1 I/O Data Register */ |
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| 356 | #define UDR1 _SFR_MEM8(0x9C) |
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| 357 | |
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| 358 | /* USART1 Control and Status Register C */ |
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| 359 | #define UCSR1C _SFR_MEM8(0x9D) |
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| 360 | |
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| 361 | /* Interrupt vectors */ |
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| 362 | |
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| 363 | /* External Interrupt Request 0 */ |
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| 364 | #define INT0_vect _VECTOR(1) |
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| 365 | #define SIG_INTERRUPT0 _VECTOR(1) |
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| 366 | |
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| 367 | /* External Interrupt Request 1 */ |
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| 368 | #define INT1_vect _VECTOR(2) |
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| 369 | #define SIG_INTERRUPT1 _VECTOR(2) |
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| 370 | |
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| 371 | /* External Interrupt Request 2 */ |
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| 372 | #define INT2_vect _VECTOR(3) |
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| 373 | #define SIG_INTERRUPT2 _VECTOR(3) |
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| 374 | |
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| 375 | /* External Interrupt Request 3 */ |
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| 376 | #define INT3_vect _VECTOR(4) |
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| 377 | #define SIG_INTERRUPT3 _VECTOR(4) |
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| 378 | |
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| 379 | /* External Interrupt Request 4 */ |
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| 380 | #define INT4_vect _VECTOR(5) |
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| 381 | #define SIG_INTERRUPT4 _VECTOR(5) |
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| 382 | |
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| 383 | /* External Interrupt Request 5 */ |
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| 384 | #define INT5_vect _VECTOR(6) |
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| 385 | #define SIG_INTERRUPT5 _VECTOR(6) |
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| 386 | |
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| 387 | /* External Interrupt Request 6 */ |
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| 388 | #define INT6_vect _VECTOR(7) |
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| 389 | #define SIG_INTERRUPT6 _VECTOR(7) |
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| 390 | |
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| 391 | /* External Interrupt Request 7 */ |
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| 392 | #define INT7_vect _VECTOR(8) |
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| 393 | #define SIG_INTERRUPT7 _VECTOR(8) |
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| 394 | |
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| 395 | /* Timer/Counter2 Compare Match */ |
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| 396 | #define TIMER2_COMP_vect _VECTOR(9) |
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| 397 | #define SIG_OUTPUT_COMPARE2 _VECTOR(9) |
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| 398 | |
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| 399 | /* Timer/Counter2 Overflow */ |
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| 400 | #define TIMER2_OVF_vect _VECTOR(10) |
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| 401 | #define SIG_OVERFLOW2 _VECTOR(10) |
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| 402 | |
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| 403 | /* Timer/Counter1 Capture Event */ |
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| 404 | #define TIMER1_CAPT_vect _VECTOR(11) |
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| 405 | #define SIG_INPUT_CAPTURE1 _VECTOR(11) |
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| 406 | |
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| 407 | /* Timer/Counter1 Compare Match A */ |
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| 408 | #define TIMER1_COMPA_vect _VECTOR(12) |
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| 409 | #define SIG_OUTPUT_COMPARE1A _VECTOR(12) |
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| 410 | |
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| 411 | /* Timer/Counter Compare Match B */ |
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| 412 | #define TIMER1_COMPB_vect _VECTOR(13) |
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| 413 | #define SIG_OUTPUT_COMPARE1B _VECTOR(13) |
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| 414 | |
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| 415 | /* Timer/Counter1 Overflow */ |
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| 416 | #define TIMER1_OVF_vect _VECTOR(14) |
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| 417 | #define SIG_OVERFLOW1 _VECTOR(14) |
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| 418 | |
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| 419 | /* Timer/Counter0 Compare Match */ |
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| 420 | #define TIMER0_COMP_vect _VECTOR(15) |
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| 421 | #define SIG_OUTPUT_COMPARE0 _VECTOR(15) |
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| 422 | |
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| 423 | /* Timer/Counter0 Overflow */ |
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| 424 | #define TIMER0_OVF_vect _VECTOR(16) |
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| 425 | #define SIG_OVERFLOW0 _VECTOR(16) |
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| 426 | |
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| 427 | /* SPI Serial Transfer Complete */ |
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| 428 | #define SPI_STC_vect _VECTOR(17) |
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| 429 | #define SIG_SPI _VECTOR(17) |
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| 430 | |
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| 431 | /* USART0, Rx Complete */ |
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| 432 | #define USART0_RX_vect _VECTOR(18) |
|---|
| 433 | #define SIG_UART0_RECV _VECTOR(18) |
|---|
| 434 | |
|---|
| 435 | /* USART0 Data Register Empty */ |
|---|
| 436 | #define USART0_UDRE_vect _VECTOR(19) |
|---|
| 437 | #define SIG_UART0_DATA _VECTOR(19) |
|---|
| 438 | |
|---|
| 439 | /* USART0, Tx Complete */ |
|---|
| 440 | #define USART0_TX_vect _VECTOR(20) |
|---|
| 441 | #define SIG_UART0_TRANS _VECTOR(20) |
|---|
| 442 | |
|---|
| 443 | /* ADC Conversion Complete */ |
|---|
| 444 | #define ADC_vect _VECTOR(21) |
|---|
| 445 | #define SIG_ADC _VECTOR(21) |
|---|
| 446 | |
|---|
| 447 | /* EEPROM Ready */ |
|---|
| 448 | #define EE_READY_vect _VECTOR(22) |
|---|
| 449 | #define SIG_EEPROM_READY _VECTOR(22) |
|---|
| 450 | |
|---|
| 451 | /* Analog Comparator */ |
|---|
| 452 | #define ANALOG_COMP_vect _VECTOR(23) |
|---|
| 453 | #define SIG_COMPARATOR _VECTOR(23) |
|---|
| 454 | |
|---|
| 455 | /* Timer/Counter1 Compare Match C */ |
|---|
| 456 | #define TIMER1_COMPC_vect _VECTOR(24) |
|---|
| 457 | #define SIG_OUTPUT_COMPARE1C _VECTOR(24) |
|---|
| 458 | |
|---|
| 459 | /* Timer/Counter3 Capture Event */ |
|---|
| 460 | #define TIMER3_CAPT_vect _VECTOR(25) |
|---|
| 461 | #define SIG_INPUT_CAPTURE3 _VECTOR(25) |
|---|
| 462 | |
|---|
| 463 | /* Timer/Counter3 Compare Match A */ |
|---|
| 464 | #define TIMER3_COMPA_vect _VECTOR(26) |
|---|
| 465 | #define SIG_OUTPUT_COMPARE3A _VECTOR(26) |
|---|
| 466 | |
|---|
| 467 | /* Timer/Counter3 Compare Match B */ |
|---|
| 468 | #define TIMER3_COMPB_vect _VECTOR(27) |
|---|
| 469 | #define SIG_OUTPUT_COMPARE3B _VECTOR(27) |
|---|
| 470 | |
|---|
| 471 | /* Timer/Counter3 Compare Match C */ |
|---|
| 472 | #define TIMER3_COMPC_vect _VECTOR(28) |
|---|
| 473 | #define SIG_OUTPUT_COMPARE3C _VECTOR(28) |
|---|
| 474 | |
|---|
| 475 | /* Timer/Counter3 Overflow */ |
|---|
| 476 | #define TIMER3_OVF_vect _VECTOR(29) |
|---|
| 477 | #define SIG_OVERFLOW3 _VECTOR(29) |
|---|
| 478 | |
|---|
| 479 | /* USART1, Rx Complete */ |
|---|
| 480 | #define USART1_RX_vect _VECTOR(30) |
|---|
| 481 | #define SIG_UART1_RECV _VECTOR(30) |
|---|
| 482 | |
|---|
| 483 | /* USART1, Data Register Empty */ |
|---|
| 484 | #define USART1_UDRE_vect _VECTOR(31) |
|---|
| 485 | #define SIG_UART1_DATA _VECTOR(31) |
|---|
| 486 | |
|---|
| 487 | /* USART1, Tx Complete */ |
|---|
| 488 | #define USART1_TX_vect _VECTOR(32) |
|---|
| 489 | #define SIG_UART1_TRANS _VECTOR(32) |
|---|
| 490 | |
|---|
| 491 | /* 2-wire Serial Interface */ |
|---|
| 492 | #define TWI_vect _VECTOR(33) |
|---|
| 493 | #define SIG_2WIRE_SERIAL _VECTOR(33) |
|---|
| 494 | |
|---|
| 495 | /* Store Program Memory Read */ |
|---|
| 496 | #define SPM_READY_vect _VECTOR(34) |
|---|
| 497 | #define SIG_SPM_READY _VECTOR(34) |
|---|
| 498 | |
|---|
| 499 | #define _VECTORS_SIZE 140 |
|---|
| 500 | |
|---|
| 501 | /* |
|---|
| 502 | The Register Bit names are represented by their bit number (0-7). |
|---|
| 503 | */ |
|---|
| 504 | |
|---|
| 505 | /* 2-wire Control Register - TWCR */ |
|---|
| 506 | #define TWINT 7 |
|---|
| 507 | #define TWEA 6 |
|---|
| 508 | #define TWSTA 5 |
|---|
| 509 | #define TWSTO 4 |
|---|
| 510 | #define TWWC 3 |
|---|
| 511 | #define TWEN 2 |
|---|
| 512 | #define TWIE 0 |
|---|
| 513 | |
|---|
| 514 | /* 2-wire Address Register - TWAR */ |
|---|
| 515 | #define TWA6 7 |
|---|
| 516 | #define TWA5 6 |
|---|
| 517 | #define TWA4 5 |
|---|
| 518 | #define TWA3 4 |
|---|
| 519 | #define TWA2 3 |
|---|
| 520 | #define TWA1 2 |
|---|
| 521 | #define TWA0 1 |
|---|
| 522 | #define TWGCE 0 |
|---|
| 523 | |
|---|
| 524 | /* 2-wire Status Register - TWSR */ |
|---|
| 525 | #define TWS7 7 |
|---|
| 526 | #define TWS6 6 |
|---|
| 527 | #define TWS5 5 |
|---|
| 528 | #define TWS4 4 |
|---|
| 529 | #define TWS3 3 |
|---|
| 530 | #define TWPS1 1 |
|---|
| 531 | #define TWPS0 0 |
|---|
| 532 | |
|---|
| 533 | /* External Memory Control Register A - XMCRA */ |
|---|
| 534 | #define SRL2 6 |
|---|
| 535 | #define SRL1 5 |
|---|
| 536 | #define SRL0 4 |
|---|
| 537 | #define SRW01 3 |
|---|
| 538 | #define SRW00 2 |
|---|
| 539 | #define SRW11 1 |
|---|
| 540 | |
|---|
| 541 | /* External Memory Control Register B - XMCRA */ |
|---|
| 542 | #define XMBK 7 |
|---|
| 543 | #define XMM2 2 |
|---|
| 544 | #define XMM1 1 |
|---|
| 545 | #define XMM0 0 |
|---|
| 546 | |
|---|
| 547 | /* XDIV Divide control register - XDIV */ |
|---|
| 548 | #define XDIVEN 7 |
|---|
| 549 | #define XDIV6 6 |
|---|
| 550 | #define XDIV5 5 |
|---|
| 551 | #define XDIV4 4 |
|---|
| 552 | #define XDIV3 3 |
|---|
| 553 | #define XDIV2 2 |
|---|
| 554 | #define XDIV1 1 |
|---|
| 555 | #define XDIV0 0 |
|---|
| 556 | |
|---|
| 557 | /* External Interrupt Control Register A - EICRA */ |
|---|
| 558 | #define ISC31 7 |
|---|
| 559 | #define ISC30 6 |
|---|
| 560 | #define ISC21 5 |
|---|
| 561 | #define ISC20 4 |
|---|
| 562 | #define ISC11 3 |
|---|
| 563 | #define ISC10 2 |
|---|
| 564 | #define ISC01 1 |
|---|
| 565 | #define ISC00 0 |
|---|
| 566 | |
|---|
| 567 | /* External Interrupt Control Register B - EICRB */ |
|---|
| 568 | #define ISC71 7 |
|---|
| 569 | #define ISC70 6 |
|---|
| 570 | #define ISC61 5 |
|---|
| 571 | #define ISC60 4 |
|---|
| 572 | #define ISC51 3 |
|---|
| 573 | #define ISC50 2 |
|---|
| 574 | #define ISC41 1 |
|---|
| 575 | #define ISC40 0 |
|---|
| 576 | |
|---|
| 577 | /* Store Program Memory Control Register - SPMCSR, SPMCR */ |
|---|
| 578 | #define SPMIE 7 |
|---|
| 579 | #define RWWSB 6 |
|---|
| 580 | #define RWWSRE 4 |
|---|
| 581 | #define BLBSET 3 |
|---|
| 582 | #define PGWRT 2 |
|---|
| 583 | #define PGERS 1 |
|---|
| 584 | #define SPMEN 0 |
|---|
| 585 | |
|---|
| 586 | /* External Interrupt MaSK register - EIMSK */ |
|---|
| 587 | #define INT7 7 |
|---|
| 588 | #define INT6 6 |
|---|
| 589 | #define INT5 5 |
|---|
| 590 | #define INT4 4 |
|---|
| 591 | #define INT3 3 |
|---|
| 592 | #define INT2 2 |
|---|
| 593 | #define INT1 1 |
|---|
| 594 | #define INT0 0 |
|---|
| 595 | |
|---|
| 596 | /* External Interrupt Flag Register - EIFR */ |
|---|
| 597 | #define INTF7 7 |
|---|
| 598 | #define INTF6 6 |
|---|
| 599 | #define INTF5 5 |
|---|
| 600 | #define INTF4 4 |
|---|
| 601 | #define INTF3 3 |
|---|
| 602 | #define INTF2 2 |
|---|
| 603 | #define INTF1 1 |
|---|
| 604 | #define INTF0 0 |
|---|
| 605 | |
|---|
| 606 | /* Timer/Counter Interrupt MaSK register - TIMSK */ |
|---|
| 607 | #define OCIE2 7 |
|---|
| 608 | #define TOIE2 6 |
|---|
| 609 | #define TICIE1 5 |
|---|
| 610 | #define OCIE1A 4 |
|---|
| 611 | #define OCIE1B 3 |
|---|
| 612 | #define TOIE1 2 |
|---|
| 613 | #define OCIE0 1 |
|---|
| 614 | #define TOIE0 0 |
|---|
| 615 | |
|---|
| 616 | /* Timer/Counter Interrupt Flag Register - TIFR */ |
|---|
| 617 | #define OCF2 7 |
|---|
| 618 | #define TOV2 6 |
|---|
| 619 | #define ICF1 5 |
|---|
| 620 | #define OCF1A 4 |
|---|
| 621 | #define OCF1B 3 |
|---|
| 622 | #define TOV1 2 |
|---|
| 623 | #define OCF0 1 |
|---|
| 624 | #define TOV0 0 |
|---|
| 625 | |
|---|
| 626 | /* Extended Timer Interrupt MaSK register - ETIMSK */ |
|---|
| 627 | #define TICIE3 5 |
|---|
| 628 | #define OCIE3A 4 |
|---|
| 629 | #define OCIE3B 3 |
|---|
| 630 | #define TOIE3 2 |
|---|
| 631 | #define OCIE3C 1 |
|---|
| 632 | #define OCIE1C 0 |
|---|
| 633 | |
|---|
| 634 | /* Extended Timer Interrupt Flag Register - ETIFR */ |
|---|
| 635 | #define ICF3 5 |
|---|
| 636 | #define OCF3A 4 |
|---|
| 637 | #define OCF3B 3 |
|---|
| 638 | #define TOV3 2 |
|---|
| 639 | #define OCF3C 1 |
|---|
| 640 | #define OCF1C 0 |
|---|
| 641 | |
|---|
| 642 | /* MCU Control Register - MCUCR */ |
|---|
| 643 | #define SRE 7 |
|---|
| 644 | #define SRW10 6 |
|---|
| 645 | #define SE 5 |
|---|
| 646 | #define SM1 4 |
|---|
| 647 | #define SM0 3 |
|---|
| 648 | #define SM2 2 |
|---|
| 649 | #define IVSEL 1 |
|---|
| 650 | #define IVCE 0 |
|---|
| 651 | |
|---|
| 652 | /* MCU Control And Status Register - MCUCSR */ |
|---|
| 653 | #define JTD 7 |
|---|
| 654 | #define JTRF 4 |
|---|
| 655 | #define WDRF 3 |
|---|
| 656 | #define BORF 2 |
|---|
| 657 | #define EXTRF 1 |
|---|
| 658 | #define PORF 0 |
|---|
| 659 | |
|---|
| 660 | /* Timer/Counter Control Register (generic) */ |
|---|
| 661 | #define FOC 7 |
|---|
| 662 | #define WGM0 6 |
|---|
| 663 | #define COM1 5 |
|---|
| 664 | #define COM0 4 |
|---|
| 665 | #define WGM1 3 |
|---|
| 666 | #define CS2 2 |
|---|
| 667 | #define CS1 1 |
|---|
| 668 | #define CS0 0 |
|---|
| 669 | |
|---|
| 670 | /* Timer/Counter 0 Control Register - TCCR0 */ |
|---|
| 671 | #define FOC0 7 |
|---|
| 672 | #define WGM00 6 |
|---|
| 673 | #define COM01 5 |
|---|
| 674 | #define COM00 4 |
|---|
| 675 | #define WGM01 3 |
|---|
| 676 | #define CS02 2 |
|---|
| 677 | #define CS01 1 |
|---|
| 678 | #define CS00 0 |
|---|
| 679 | |
|---|
| 680 | /* Timer/Counter 2 Control Register - TCCR2 */ |
|---|
| 681 | #define FOC2 7 |
|---|
| 682 | #define WGM20 6 |
|---|
| 683 | #define COM21 5 |
|---|
| 684 | #define COM20 4 |
|---|
| 685 | #define WGM21 3 |
|---|
| 686 | #define CS22 2 |
|---|
| 687 | #define CS21 1 |
|---|
| 688 | #define CS20 0 |
|---|
| 689 | |
|---|
| 690 | /* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ |
|---|
| 691 | #define AS0 3 |
|---|
| 692 | #define TCN0UB 2 |
|---|
| 693 | #define OCR0UB 1 |
|---|
| 694 | #define TCR0UB 0 |
|---|
| 695 | |
|---|
| 696 | /* Timer/Counter Control Register A (generic) */ |
|---|
| 697 | #define COMA1 7 |
|---|
| 698 | #define COMA0 6 |
|---|
| 699 | #define COMB1 5 |
|---|
| 700 | #define COMB0 4 |
|---|
| 701 | #define COMC1 3 |
|---|
| 702 | #define COMC0 2 |
|---|
| 703 | #define WGMA1 1 |
|---|
| 704 | #define WGMA0 0 |
|---|
| 705 | |
|---|
| 706 | /* Timer/Counter 1 Control and Status Register A - TCCR1A */ |
|---|
| 707 | #define COM1A1 7 |
|---|
| 708 | #define COM1A0 6 |
|---|
| 709 | #define COM1B1 5 |
|---|
| 710 | #define COM1B0 4 |
|---|
| 711 | #define COM1C1 3 |
|---|
| 712 | #define COM1C0 2 |
|---|
| 713 | #define WGM11 1 |
|---|
| 714 | #define WGM10 0 |
|---|
| 715 | |
|---|
| 716 | /* Timer/Counter 3 Control and Status Register A - TCCR3A */ |
|---|
| 717 | #define COM3A1 7 |
|---|
| 718 | #define COM3A0 6 |
|---|
| 719 | #define COM3B1 5 |
|---|
| 720 | #define COM3B0 4 |
|---|
| 721 | #define COM3C1 3 |
|---|
| 722 | #define COM3C0 2 |
|---|
| 723 | #define WGM31 1 |
|---|
| 724 | #define WGM30 0 |
|---|
| 725 | |
|---|
| 726 | /* Timer/Counter Control and Status Register B (generic) */ |
|---|
| 727 | #define ICNC 7 |
|---|
| 728 | #define ICES 6 |
|---|
| 729 | #define WGMB3 4 |
|---|
| 730 | #define WGMB2 3 |
|---|
| 731 | #define CSB2 2 |
|---|
| 732 | #define CSB1 1 |
|---|
| 733 | #define CSB0 0 |
|---|
| 734 | |
|---|
| 735 | /* Timer/Counter 1 Control and Status Register B - TCCR1B */ |
|---|
| 736 | #define ICNC1 7 |
|---|
| 737 | #define ICES1 6 |
|---|
| 738 | #define WGM13 4 |
|---|
| 739 | #define WGM12 3 |
|---|
| 740 | #define CS12 2 |
|---|
| 741 | #define CS11 1 |
|---|
| 742 | #define CS10 0 |
|---|
| 743 | |
|---|
| 744 | /* Timer/Counter 3 Control and Status Register B - TCCR3B */ |
|---|
| 745 | #define ICNC3 7 |
|---|
| 746 | #define ICES3 6 |
|---|
| 747 | #define WGM33 4 |
|---|
| 748 | #define WGM32 3 |
|---|
| 749 | #define CS32 2 |
|---|
| 750 | #define CS31 1 |
|---|
| 751 | #define CS30 0 |
|---|
| 752 | |
|---|
| 753 | /* Timer/Counter Control Register C (generic) */ |
|---|
| 754 | #define FOCA 7 |
|---|
| 755 | #define FOCB 6 |
|---|
| 756 | #define FOCC 5 |
|---|
| 757 | |
|---|
| 758 | /* Timer/Counter 3 Control Register C - TCCR3C */ |
|---|
| 759 | #define FOC3A 7 |
|---|
| 760 | #define FOC3B 6 |
|---|
| 761 | #define FOC3C 5 |
|---|
| 762 | |
|---|
| 763 | /* Timer/Counter 1 Control Register C - TCCR1C */ |
|---|
| 764 | #define FOC1A 7 |
|---|
| 765 | #define FOC1B 6 |
|---|
| 766 | #define FOC1C 5 |
|---|
| 767 | |
|---|
| 768 | /* On-chip Debug Register - OCDR */ |
|---|
| 769 | #define IDRD 7 |
|---|
| 770 | #define OCDR7 7 |
|---|
| 771 | #define OCDR6 6 |
|---|
| 772 | #define OCDR5 5 |
|---|
| 773 | #define OCDR4 4 |
|---|
| 774 | #define OCDR3 3 |
|---|
| 775 | #define OCDR2 2 |
|---|
| 776 | #define OCDR1 1 |
|---|
| 777 | #define OCDR0 0 |
|---|
| 778 | |
|---|
| 779 | /* Watchdog Timer Control Register - WDTCR */ |
|---|
| 780 | #define WDCE 4 |
|---|
| 781 | #define WDE 3 |
|---|
| 782 | #define WDP2 2 |
|---|
| 783 | #define WDP1 1 |
|---|
| 784 | #define WDP0 0 |
|---|
| 785 | |
|---|
| 786 | /* |
|---|
| 787 | The ADHSM bit has been removed from all documentation, |
|---|
| 788 | as being not needed at all since the comparator has proven |
|---|
| 789 | to be fast enough even without feeding it more power. |
|---|
| 790 | */ |
|---|
| 791 | |
|---|
| 792 | /* Special Function I/O Register - SFIOR */ |
|---|
| 793 | #define TSM 7 |
|---|
| 794 | #define ACME 3 |
|---|
| 795 | #define PUD 2 |
|---|
| 796 | #define PSR0 1 |
|---|
| 797 | #define PSR321 0 |
|---|
| 798 | |
|---|
| 799 | /* Port Data Register (generic) */ |
|---|
| 800 | #define PORT7 7 |
|---|
| 801 | #define PORT6 6 |
|---|
| 802 | #define PORT5 5 |
|---|
| 803 | #define PORT4 4 |
|---|
| 804 | #define PORT3 3 |
|---|
| 805 | #define PORT2 2 |
|---|
| 806 | #define PORT1 1 |
|---|
| 807 | #define PORT0 0 |
|---|
| 808 | |
|---|
| 809 | /* Port Data Direction Register (generic) */ |
|---|
| 810 | #define DD7 7 |
|---|
| 811 | #define DD6 6 |
|---|
| 812 | #define DD5 5 |
|---|
| 813 | #define DD4 4 |
|---|
| 814 | #define DD3 3 |
|---|
| 815 | #define DD2 2 |
|---|
| 816 | #define DD1 1 |
|---|
| 817 | #define DD0 0 |
|---|
| 818 | |
|---|
| 819 | /* Port Input Pins (generic) */ |
|---|
| 820 | #define PIN7 7 |
|---|
| 821 | #define PIN6 6 |
|---|
| 822 | #define PIN5 5 |
|---|
| 823 | #define PIN4 4 |
|---|
| 824 | #define PIN3 3 |
|---|
| 825 | #define PIN2 2 |
|---|
| 826 | #define PIN1 1 |
|---|
| 827 | #define PIN0 0 |
|---|
| 828 | |
|---|
| 829 | /* SPI Status Register - SPSR */ |
|---|
| 830 | #define SPIF 7 |
|---|
| 831 | #define WCOL 6 |
|---|
| 832 | #define SPI2X 0 |
|---|
| 833 | |
|---|
| 834 | /* SPI Control Register - SPCR */ |
|---|
| 835 | #define SPIE 7 |
|---|
| 836 | #define SPE 6 |
|---|
| 837 | #define DORD 5 |
|---|
| 838 | #define MSTR 4 |
|---|
| 839 | #define CPOL 3 |
|---|
| 840 | #define CPHA 2 |
|---|
| 841 | #define SPR1 1 |
|---|
| 842 | #define SPR0 0 |
|---|
| 843 | |
|---|
| 844 | /* USART Register C (generic) */ |
|---|
| 845 | #define UMSEL 6 |
|---|
| 846 | #define UPM1 5 |
|---|
| 847 | #define UPM0 4 |
|---|
| 848 | #define USBS 3 |
|---|
| 849 | #define UCSZ1 2 |
|---|
| 850 | #define UCSZ0 1 |
|---|
| 851 | #define UCPOL 0 |
|---|
| 852 | |
|---|
| 853 | /* USART1 Register C - UCSR1C */ |
|---|
| 854 | #define UMSEL1 6 |
|---|
| 855 | #define UPM11 5 |
|---|
| 856 | #define UPM10 4 |
|---|
| 857 | #define USBS1 3 |
|---|
| 858 | #define UCSZ11 2 |
|---|
| 859 | #define UCSZ10 1 |
|---|
| 860 | #define UCPOL1 0 |
|---|
| 861 | |
|---|
| 862 | /* USART0 Register C - UCSR0C */ |
|---|
| 863 | #define UMSEL0 6 |
|---|
| 864 | #define UPM01 5 |
|---|
| 865 | #define UPM00 4 |
|---|
| 866 | #define USBS0 3 |
|---|
| 867 | #define UCSZ01 2 |
|---|
| 868 | #define UCSZ00 1 |
|---|
| 869 | #define UCPOL0 0 |
|---|
| 870 | |
|---|
| 871 | /* USART Status Register A (generic) */ |
|---|
| 872 | #define RXC 7 |
|---|
| 873 | #define TXC 6 |
|---|
| 874 | #define UDRE 5 |
|---|
| 875 | #define FE 4 |
|---|
| 876 | #define DOR 3 |
|---|
| 877 | #define UPE 2 |
|---|
| 878 | #define U2X 1 |
|---|
| 879 | #define MPCM 0 |
|---|
| 880 | |
|---|
| 881 | /* USART1 Status Register A - UCSR1A */ |
|---|
| 882 | #define RXC1 7 |
|---|
| 883 | #define TXC1 6 |
|---|
| 884 | #define UDRE1 5 |
|---|
| 885 | #define FE1 4 |
|---|
| 886 | #define DOR1 3 |
|---|
| 887 | #define UPE1 2 |
|---|
| 888 | #define U2X1 1 |
|---|
| 889 | #define MPCM1 0 |
|---|
| 890 | |
|---|
| 891 | /* USART0 Status Register A - UCSR0A */ |
|---|
| 892 | #define RXC0 7 |
|---|
| 893 | #define TXC0 6 |
|---|
| 894 | #define UDRE0 5 |
|---|
| 895 | #define FE0 4 |
|---|
| 896 | #define DOR0 3 |
|---|
| 897 | #define UPE0 2 |
|---|
| 898 | #define U2X0 1 |
|---|
| 899 | #define MPCM0 0 |
|---|
| 900 | |
|---|
| 901 | /* USART Control Register B (generic) */ |
|---|
| 902 | #define RXCIE 7 |
|---|
| 903 | #define TXCIE 6 |
|---|
| 904 | #define UDRIE 5 |
|---|
| 905 | #define RXEN 4 |
|---|
| 906 | #define TXEN 3 |
|---|
| 907 | #define UCSZ 2 |
|---|
| 908 | #define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ |
|---|
| 909 | #define RXB8 1 |
|---|
| 910 | #define TXB8 0 |
|---|
| 911 | |
|---|
| 912 | /* USART1 Control Register B - UCSR1B */ |
|---|
| 913 | #define RXCIE1 7 |
|---|
| 914 | #define TXCIE1 6 |
|---|
| 915 | #define UDRIE1 5 |
|---|
| 916 | #define RXEN1 4 |
|---|
| 917 | #define TXEN1 3 |
|---|
| 918 | #define UCSZ12 2 |
|---|
| 919 | #define RXB81 1 |
|---|
| 920 | #define TXB81 0 |
|---|
| 921 | |
|---|
| 922 | /* USART0 Control Register B - UCSR0B */ |
|---|
| 923 | #define RXCIE0 7 |
|---|
| 924 | #define TXCIE0 6 |
|---|
| 925 | #define UDRIE0 5 |
|---|
| 926 | #define RXEN0 4 |
|---|
| 927 | #define TXEN0 3 |
|---|
| 928 | #define UCSZ02 2 |
|---|
| 929 | #define RXB80 1 |
|---|
| 930 | #define TXB80 0 |
|---|
| 931 | |
|---|
| 932 | /* Analog Comparator Control and Status Register - ACSR */ |
|---|
| 933 | #define ACD 7 |
|---|
| 934 | #define ACBG 6 |
|---|
| 935 | #define ACO 5 |
|---|
| 936 | #define ACI 4 |
|---|
| 937 | #define ACIE 3 |
|---|
| 938 | #define ACIC 2 |
|---|
| 939 | #define ACIS1 1 |
|---|
| 940 | #define ACIS0 0 |
|---|
| 941 | |
|---|
| 942 | /* ADC Control and Status Register B - ADCSRB */ |
|---|
| 943 | #define ADTS2 2 |
|---|
| 944 | #define ADTS1 1 |
|---|
| 945 | #define ADTS0 0 |
|---|
| 946 | |
|---|
| 947 | /* ADC Control and status Register A - ADCSRA */ |
|---|
| 948 | #define ADEN 7 |
|---|
| 949 | #define ADSC 6 |
|---|
| 950 | #define ADATE 5 |
|---|
| 951 | #define ADIF 4 |
|---|
| 952 | #define ADIE 3 |
|---|
| 953 | #define ADPS2 2 |
|---|
| 954 | #define ADPS1 1 |
|---|
| 955 | #define ADPS0 0 |
|---|
| 956 | |
|---|
| 957 | /* ADC Multiplexer select - ADMUX */ |
|---|
| 958 | #define REFS1 7 |
|---|
| 959 | #define REFS0 6 |
|---|
| 960 | #define ADLAR 5 |
|---|
| 961 | #define MUX4 4 |
|---|
| 962 | #define MUX3 3 |
|---|
| 963 | #define MUX2 2 |
|---|
| 964 | #define MUX1 1 |
|---|
| 965 | #define MUX0 0 |
|---|
| 966 | |
|---|
| 967 | /* Port A Data Register - PORTA */ |
|---|
| 968 | #define PA7 7 |
|---|
| 969 | #define PA6 6 |
|---|
| 970 | #define PA5 5 |
|---|
| 971 | #define PA4 4 |
|---|
| 972 | #define PA3 3 |
|---|
| 973 | #define PA2 2 |
|---|
| 974 | #define PA1 1 |
|---|
| 975 | #define PA0 0 |
|---|
| 976 | |
|---|
| 977 | /* Port A Data Direction Register - DDRA */ |
|---|
| 978 | #define DDA7 7 |
|---|
| 979 | #define DDA6 6 |
|---|
| 980 | #define DDA5 5 |
|---|
| 981 | #define DDA4 4 |
|---|
| 982 | #define DDA3 3 |
|---|
| 983 | #define DDA2 2 |
|---|
| 984 | #define DDA1 1 |
|---|
| 985 | #define DDA0 0 |
|---|
| 986 | |
|---|
| 987 | /* Port A Input Pins - PINA */ |
|---|
| 988 | #define PINA7 7 |
|---|
| 989 | #define PINA6 6 |
|---|
| 990 | #define PINA5 5 |
|---|
| 991 | #define PINA4 4 |
|---|
| 992 | #define PINA3 3 |
|---|
| 993 | #define PINA2 2 |
|---|
| 994 | #define PINA1 1 |
|---|
| 995 | #define PINA0 0 |
|---|
| 996 | |
|---|
| 997 | /* Port B Data Register - PORTB */ |
|---|
| 998 | #define PB7 7 |
|---|
| 999 | #define PB6 6 |
|---|
| 1000 | #define PB5 5 |
|---|
| 1001 | #define PB4 4 |
|---|
| 1002 | #define PB3 3 |
|---|
| 1003 | #define PB2 2 |
|---|
| 1004 | #define PB1 1 |
|---|
| 1005 | #define PB0 0 |
|---|
| 1006 | |
|---|
| 1007 | /* Port B Data Direction Register - DDRB */ |
|---|
| 1008 | #define DDB7 7 |
|---|
| 1009 | #define DDB6 6 |
|---|
| 1010 | #define DDB5 5 |
|---|
| 1011 | #define DDB4 4 |
|---|
| 1012 | #define DDB3 3 |
|---|
| 1013 | #define DDB2 2 |
|---|
| 1014 | #define DDB1 1 |
|---|
| 1015 | #define DDB0 0 |
|---|
| 1016 | |
|---|
| 1017 | /* Port B Input Pins - PINB */ |
|---|
| 1018 | #define PINB7 7 |
|---|
| 1019 | #define PINB6 6 |
|---|
| 1020 | #define PINB5 5 |
|---|
| 1021 | #define PINB4 4 |
|---|
| 1022 | #define PINB3 3 |
|---|
| 1023 | #define PINB2 2 |
|---|
| 1024 | #define PINB1 1 |
|---|
| 1025 | #define PINB0 0 |
|---|
| 1026 | |
|---|
| 1027 | /* Port C Data Register - PORTC */ |
|---|
| 1028 | #define PC7 7 |
|---|
| 1029 | #define PC6 6 |
|---|
| 1030 | #define PC5 5 |
|---|
| 1031 | #define PC4 4 |
|---|
| 1032 | #define PC3 3 |
|---|
| 1033 | #define PC2 2 |
|---|
| 1034 | #define PC1 1 |
|---|
| 1035 | #define PC0 0 |
|---|
| 1036 | |
|---|
| 1037 | /* Port C Data Direction Register - DDRC */ |
|---|
| 1038 | #define DDC7 7 |
|---|
| 1039 | #define DDC6 6 |
|---|
| 1040 | #define DDC5 5 |
|---|
| 1041 | #define DDC4 4 |
|---|
| 1042 | #define DDC3 3 |
|---|
| 1043 | #define DDC2 2 |
|---|
| 1044 | #define DDC1 1 |
|---|
| 1045 | #define DDC0 0 |
|---|
| 1046 | |
|---|
| 1047 | /* Port C Input Pins - PINC */ |
|---|
| 1048 | #define PINC7 7 |
|---|
| 1049 | #define PINC6 6 |
|---|
| 1050 | #define PINC5 5 |
|---|
| 1051 | #define PINC4 4 |
|---|
| 1052 | #define PINC3 3 |
|---|
| 1053 | #define PINC2 2 |
|---|
| 1054 | #define PINC1 1 |
|---|
| 1055 | #define PINC0 0 |
|---|
| 1056 | |
|---|
| 1057 | /* Port D Data Register - PORTD */ |
|---|
| 1058 | #define PD7 7 |
|---|
| 1059 | #define PD6 6 |
|---|
| 1060 | #define PD5 5 |
|---|
| 1061 | #define PD4 4 |
|---|
| 1062 | #define PD3 3 |
|---|
| 1063 | #define PD2 2 |
|---|
| 1064 | #define PD1 1 |
|---|
| 1065 | #define PD0 0 |
|---|
| 1066 | |
|---|
| 1067 | /* Port D Data Direction Register - DDRD */ |
|---|
| 1068 | #define DDD7 7 |
|---|
| 1069 | #define DDD6 6 |
|---|
| 1070 | #define DDD5 5 |
|---|
| 1071 | #define DDD4 4 |
|---|
| 1072 | #define DDD3 3 |
|---|
| 1073 | #define DDD2 2 |
|---|
| 1074 | #define DDD1 1 |
|---|
| 1075 | #define DDD0 0 |
|---|
| 1076 | |
|---|
| 1077 | /* Port D Input Pins - PIND */ |
|---|
| 1078 | #define PIND7 7 |
|---|
| 1079 | #define PIND6 6 |
|---|
| 1080 | #define PIND5 5 |
|---|
| 1081 | #define PIND4 4 |
|---|
| 1082 | #define PIND3 3 |
|---|
| 1083 | #define PIND2 2 |
|---|
| 1084 | #define PIND1 1 |
|---|
| 1085 | #define PIND0 0 |
|---|
| 1086 | |
|---|
| 1087 | /* Port E Data Register - PORTE */ |
|---|
| 1088 | #define PE7 7 |
|---|
| 1089 | #define PE6 6 |
|---|
| 1090 | #define PE5 5 |
|---|
| 1091 | #define PE4 4 |
|---|
| 1092 | #define PE3 3 |
|---|
| 1093 | #define PE2 2 |
|---|
| 1094 | #define PE1 1 |
|---|
| 1095 | #define PE0 0 |
|---|
| 1096 | |
|---|
| 1097 | /* Port E Data Direction Register - DDRE */ |
|---|
| 1098 | #define DDE7 7 |
|---|
| 1099 | #define DDE6 6 |
|---|
| 1100 | #define DDE5 5 |
|---|
| 1101 | #define DDE4 4 |
|---|
| 1102 | #define DDE3 3 |
|---|
| 1103 | #define DDE2 2 |
|---|
| 1104 | #define DDE1 1 |
|---|
| 1105 | #define DDE0 0 |
|---|
| 1106 | |
|---|
| 1107 | /* Port E Input Pins - PINE */ |
|---|
| 1108 | #define PINE7 7 |
|---|
| 1109 | #define PINE6 6 |
|---|
| 1110 | #define PINE5 5 |
|---|
| 1111 | #define PINE4 4 |
|---|
| 1112 | #define PINE3 3 |
|---|
| 1113 | #define PINE2 2 |
|---|
| 1114 | #define PINE1 1 |
|---|
| 1115 | #define PINE0 0 |
|---|
| 1116 | |
|---|
| 1117 | /* Port F Data Register - PORTF */ |
|---|
| 1118 | #define PF7 7 |
|---|
| 1119 | #define PF6 6 |
|---|
| 1120 | #define PF5 5 |
|---|
| 1121 | #define PF4 4 |
|---|
| 1122 | #define PF3 3 |
|---|
| 1123 | #define PF2 2 |
|---|
| 1124 | #define PF1 1 |
|---|
| 1125 | #define PF0 0 |
|---|
| 1126 | |
|---|
| 1127 | /* Port F Data Direction Register - DDRF */ |
|---|
| 1128 | #define DDF7 7 |
|---|
| 1129 | #define DDF6 6 |
|---|
| 1130 | #define DDF5 5 |
|---|
| 1131 | #define DDF4 4 |
|---|
| 1132 | #define DDF3 3 |
|---|
| 1133 | #define DDF2 2 |
|---|
| 1134 | #define DDF1 1 |
|---|
| 1135 | #define DDF0 0 |
|---|
| 1136 | |
|---|
| 1137 | /* Port F Input Pins - PINF */ |
|---|
| 1138 | #define PINF7 7 |
|---|
| 1139 | #define PINF6 6 |
|---|
| 1140 | #define PINF5 5 |
|---|
| 1141 | #define PINF4 4 |
|---|
| 1142 | #define PINF3 3 |
|---|
| 1143 | #define PINF2 2 |
|---|
| 1144 | #define PINF1 1 |
|---|
| 1145 | #define PINF0 0 |
|---|
| 1146 | |
|---|
| 1147 | /* Port G Data Register - PORTG */ |
|---|
| 1148 | #define PG4 4 |
|---|
| 1149 | #define PG3 3 |
|---|
| 1150 | #define PG2 2 |
|---|
| 1151 | #define PG1 1 |
|---|
| 1152 | #define PG0 0 |
|---|
| 1153 | |
|---|
| 1154 | /* Port G Data Direction Register - DDRG */ |
|---|
| 1155 | #define DDG4 4 |
|---|
| 1156 | #define DDG3 3 |
|---|
| 1157 | #define DDG2 2 |
|---|
| 1158 | #define DDG1 1 |
|---|
| 1159 | #define DDG0 0 |
|---|
| 1160 | |
|---|
| 1161 | /* Port G Input Pins - PING */ |
|---|
| 1162 | #define PING4 4 |
|---|
| 1163 | #define PING3 3 |
|---|
| 1164 | #define PING2 2 |
|---|
| 1165 | #define PING1 1 |
|---|
| 1166 | #define PING0 0 |
|---|
| 1167 | |
|---|
| 1168 | /* EEPROM Control Register */ |
|---|
| 1169 | #define EERIE 3 |
|---|
| 1170 | #define EEMWE 2 |
|---|
| 1171 | #define EEWE 1 |
|---|
| 1172 | #define EERE 0 |
|---|
| 1173 | |
|---|
| 1174 | /* Constants */ |
|---|
| 1175 | #define SPM_PAGESIZE 256 |
|---|
| 1176 | #define RAMEND 0x10FF /* Last On-Chip SRAM Location */ |
|---|
| 1177 | #define XRAMEND 0xFFFF |
|---|
| 1178 | #define E2END 0x07FF |
|---|
| 1179 | #define E2PAGESIZE 8 |
|---|
| 1180 | #define FLASHEND 0xFFFF |
|---|
| 1181 | |
|---|
| 1182 | |
|---|
| 1183 | /* Fuses */ |
|---|
| 1184 | |
|---|
| 1185 | #define FUSE_MEMORY_SIZE 3 |
|---|
| 1186 | |
|---|
| 1187 | /* Low Fuse Byte */ |
|---|
| 1188 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
|---|
| 1189 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
|---|
| 1190 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
|---|
| 1191 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
|---|
| 1192 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
|---|
| 1193 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
|---|
| 1194 | #define FUSE_BODEN (unsigned char)~_BV(6) |
|---|
| 1195 | #define FUSE_BODLEVEL (unsigned char)~_BV(7) |
|---|
| 1196 | #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) |
|---|
| 1197 | |
|---|
| 1198 | /* High Fuse Byte */ |
|---|
| 1199 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
|---|
| 1200 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
|---|
| 1201 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
|---|
| 1202 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
|---|
| 1203 | #define FUSE_CKOPT (unsigned char)~_BV(4) |
|---|
| 1204 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
|---|
| 1205 | #define FUSE_JTAGEN (unsigned char)~_BV(6) |
|---|
| 1206 | #define FUSE_OCDEN (unsigned char)~_BV(7) |
|---|
| 1207 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
|---|
| 1208 | |
|---|
| 1209 | /* Extended Fuse Byte */ |
|---|
| 1210 | #define FUSE_WDTON (unsigned char)~_BV(0) |
|---|
| 1211 | #define FUSE_M103C (unsigned char)~_BV(1) |
|---|
| 1212 | #define EFUSE_DEFAULT (FUSE_M103C) |
|---|
| 1213 | |
|---|
| 1214 | |
|---|
| 1215 | /* Lock Bits */ |
|---|
| 1216 | #define __LOCK_BITS_EXIST |
|---|
| 1217 | #define __BOOT_LOCK_BITS_0_EXIST |
|---|
| 1218 | #define __BOOT_LOCK_BITS_1_EXIST |
|---|
| 1219 | |
|---|
| 1220 | |
|---|
| 1221 | /* Signature */ |
|---|
| 1222 | #define SIGNATURE_0 0x1E |
|---|
| 1223 | #define SIGNATURE_1 0x96 |
|---|
| 1224 | #define SIGNATURE_2 0x02 |
|---|
| 1225 | |
|---|
| 1226 | |
|---|
| 1227 | #endif /* _AVR_IOM64_H_ */ |
|---|
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