source: rtems/cpukit/score/cpu/avr/avr/iom406.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 16.0 KB
Line 
1/* Copyright (c) 2006, Pieter Conradie
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom406.h - definitions for ATmega406 */
34
35#ifndef _AVR_IOM406_H_
36#define _AVR_IOM406_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom406.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52#define PINA    _SFR_IO8(0x00)
53#define PINA7   7
54#define PINA6   6
55#define PINA5   5
56#define PINA4   4
57#define PINA3   3
58#define PINA2   2
59#define PINA1   1
60#define PINA0   0
61
62#define DDRA    _SFR_IO8(0x01)
63#define DDA7    7
64#define DDA6    6
65#define DDA5    5
66#define DDA4    4
67#define DDA3    3
68#define DDA2    2
69#define DDA1    1
70#define DDA0    0
71
72#define PORTA   _SFR_IO8(0x02)
73#define PA7     7
74#define PA6     6
75#define PA5     5
76#define PA4     4
77#define PA3     3
78#define PA2     2
79#define PA1     1
80#define PA0     0
81
82#define PINB    _SFR_IO8(0x03)
83#define PINB7   7
84#define PINB6   6
85#define PINB5   5
86#define PINB4   4
87#define PINB3   3
88#define PINB2   2
89#define PINB1   1
90#define PINB0   0
91
92#define DDRB    _SFR_IO8(0x04)
93#define DDB7    7
94#define DDB6    6
95#define DDB5    5
96#define DDB4    4
97#define DDB3    3
98#define DDB2    2
99#define DDB1    1
100#define DDB0    0
101
102#define PORTB   _SFR_IO8(0x05)
103#define PB7     7
104#define PB6     6
105#define PB5     5
106#define PB4     4
107#define PB3     3
108#define PB2     2
109#define PB1     1
110#define PB0     0
111
112/* Reserved [0x06..0x07] */
113
114#define PORTC   _SFR_IO8(0x08)
115#define PC0     0
116
117#define PIND    _SFR_IO8(0x09)
118#define PIND1   1
119#define PIND0   0
120
121#define DDRD    _SFR_IO8(0x0A)
122#define DDD1    1
123#define DDD0    0
124
125#define PORTD   _SFR_IO8(0x0B)
126#define PD1     1
127#define PD0     0
128
129/* Reserved [0x0C..0x14] */
130
131/* Timer/Counter0 Interrupt Flag Register */
132#define TIFR0   _SFR_IO8(0x15)
133#define OCF0B   2
134#define OCF0A   1
135#define TOV0    0
136
137/* Timer/Counter1 Interrupt Flag Register */
138#define TIFR1   _SFR_IO8(0x16)
139#define OCF1A   1
140#define TOV1    0
141
142/* Reserved [0x17..0x1A] */
143
144/* Pin Change Interrupt Control Register */
145#define PCIFR   _SFR_IO8(0x1B)
146#define PCIF1   1
147#define PCIF0   0
148
149/* External Interrupt Flag Register */
150#define EIFR    _SFR_IO8(0x1C)
151#define INTF3   3
152#define INTF2   2
153#define INTF1   1
154#define INTF0   0
155
156/* External Interrupt MaSK register */
157#define EIMSK   _SFR_IO8(0x1D)
158#define INT3    3
159#define INT2    2
160#define INT1    1
161#define INT0    0
162
163/* General Purpose I/O Register 0 */
164#define GPIOR0  _SFR_IO8(0x1E)
165
166/* EEPROM Control Register */
167#define EECR    _SFR_IO8(0x1F)
168#define EEPM1   5
169#define EEPM0   4
170#define EERIE   3
171#define EEMPE   2
172#define EEPE    1
173#define EERE    0
174
175/* EEPROM Data Register */
176#define EEDR    _SFR_IO8(0x20)
177
178/* EEPROM Address Register */
179#define EEAR    _SFR_IO16(0x21)
180#define EEARL   _SFR_IO8(0x21)
181#define EEARH   _SFR_IO8(0x22)
182
183/* 6-char sequence denoting where to find the EEPROM registers in memory space.
184   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
185   subroutines.
186   First two letters:  EECR address.
187   Second two letters: EEDR address.
188   Last two letters:   EEAR address.  */
189#define __EEPROM_REG_LOCATIONS__ 1F2021
190
191/* General Timer/Counter Control Register */
192#define GTCCR   _SFR_IO8(0x23)
193#define TSM     7
194#define PSRSYNC 0
195
196/* Timer/Counter Control Register A */
197#define TCCR0A  _SFR_IO8(0x24)
198#define COM0A1  7
199#define COM0A0  6
200#define COM0B1  5
201#define COM0B0  4
202#define WGM01   1
203#define WGM00   0
204
205/* Timer/Counter Control Register B */
206#define TCCR0B  _SFR_IO8(0x25)
207#define FOC0A   7
208#define FOC0B   6
209#define WGM02   3
210#define CS02    2
211#define CS01    1
212#define CS00    0
213
214/* Timer/Counter 0 */
215#define TCNT0   _SFR_IO8(0x26)
216
217/* Output Compare Register A */
218#define OCR0A   _SFR_IO8(0x27)
219
220/* Output Compare Register B */
221#define OCR0B   _SFR_IO8(0x28)
222
223/* Reserved [0x29] */
224
225/* General Purpose I/O Register 1 */
226#define GPIOR1  _SFR_IO8(0x2A)
227
228/* General Purpose I/O Register 2 */
229#define GPIOR2  _SFR_IO8(0x2B)
230
231/* Reserved [0x2C..0x30] */
232
233/* On-chip Debug Register */
234#define OCDR    _SFR_IO8(0x31)
235
236/* Reserved [0x32] */
237
238/* Sleep Mode Control Register */
239#define SMCR    _SFR_IO8(0x33)
240#define SM2     3
241#define SM1     2
242#define SM0     1
243#define SE      0
244
245/* MCU Status Register */
246#define MCUSR   _SFR_IO8(0x34)
247#define JTRF    4
248#define WDRF    3
249#define BODRF   2
250#define EXTRF   1
251#define PORF    0
252
253/* MCU general Control Register */
254#define MCUCR   _SFR_IO8(0x35)
255#define JTD     7
256#define PUD     4
257#define IVSEL   1
258#define IVCE    0
259
260/* Reserved [0x36] */
261
262/* Store Program Memory Control and Status Register */
263#define SPMCSR  _SFR_IO8(0x37)
264#define SPMIE   7
265#define RWWSB   6
266#define SIGRD   5
267#define RWWSRE  4
268#define BLBSET  3
269#define PGWRT   2
270#define PGERS   1
271#define SPMEN   0
272
273/* Reserved [0x36..0x3C] */
274
275/* 0x3D..0x3E SP */
276
277/* 0x3F SREG */
278
279/* Extended I/O registers */
280
281/* Watchdog Timer Control Register */
282#define WDTCSR  _SFR_MEM8(0x60)
283#define WDIF    7
284#define WDIE    6
285#define WDP3    5
286#define WDCE    4
287#define WDE     3
288#define WDP2    2
289#define WDP1    1
290#define WDP0    0
291
292/* Reserved [0x61] */
293
294/* Wake-up Timer Control and Status Register */
295#define WUTCSR  _SFR_MEM8(0x62)
296#define WUTIF   7
297#define WUTIE   6
298#define WUTCF   5
299#define WUTR    4
300#define WUTE    3
301#define WUTP2   2
302#define WUTP1   1
303#define WUTP0   0
304
305/* Reserved [0x63] */
306
307/* Power Reduction Register 0 */
308#define PRR0    _SFR_MEM8(0x64)
309#define PRTWI   3
310#define PRTIM1  2
311#define PRTIM0  1
312#define PRVADC  0
313
314/* Reserved [0x65] */
315
316/* Fast Oscillator Calibration Register */
317#define FOSCCAL _SFR_MEM8(0x66)
318
319/* Reserved [0x67] */
320
321/* Pin Change Interrupt Control Register */
322#define PCICR   _SFR_MEM8(0x68)
323#define PCIE1   1
324#define PCIE0   0
325
326/* External Interrupt Control Register A */
327#define EICRA   _SFR_MEM8(0x69)
328#define ISC31   7
329#define ISC30   6
330#define ISC21   5
331#define ISC20   4
332#define ISC11   3
333#define ISC10   2
334#define ISC01   1
335#define ISC00   0
336
337/* Reserved [0x6A] */
338
339/* Pin Change Mask Register 0 */
340#define PCMSK0  _SFR_MEM8(0x6B)
341#define PCINT7  7
342#define PCINT6  6
343#define PCINT5  5
344#define PCINT4  4
345#define PCINT3  3
346#define PCINT2  2
347#define PCINT1  1
348#define PCINT0  0
349
350/* Pin Change Mask Register 1 */
351#define PCMSK1  _SFR_MEM8(0x6C)
352#define PCINT15 7
353#define PCINT14 6
354#define PCINT13 5
355#define PCINT12 4
356#define PCINT11 3
357#define PCINT10 2
358#define PCINT9  1
359#define PCINT8  0
360
361/* Reserved [0x6D] */
362
363/* Timer/Counter Interrupt MaSK register 0 */
364#define TIMSK0  _SFR_MEM8(0x6E)
365#define OCIE0B  2
366#define OCIE0A  1
367#define TOIE0   0
368
369/* Timer/Counter Interrupt MaSK register 1 */
370#define TIMSK1  _SFR_MEM8(0x6F)
371#define OCIE1A  1
372#define TOIE1   0
373
374/* Reserved [0x70..0x77] */
375
376/* V-ADC Data Register */
377#define VADC    _SFR_MEM16(0x78)
378#define VADCL   _SFR_MEM8(0x78)
379#define VADCH   _SFR_MEM8(0x79)
380
381/* V-ADC Control and Status Register */
382#define VADCSR  _SFR_MEM8(0x7A)
383#define VADEN   3
384#define VADSC   2
385#define VADCCIF 1
386#define VADCCIE 0
387
388/* Reserved [0x7B] */
389
390/* V-ADC Multiplexer Selection Register */
391#define VADMUX  _SFR_MEM8(0x7C)
392#define VADMUX3 3
393#define VADMUX2 2
394#define VADMUX1 1
395#define VADMUX0 0
396
397/* Reserved [0x7D] */
398
399/* Digital Input Disable Register 0 */
400#define DIDR0   _SFR_MEM8(0x7E)
401#define VADC3D  3
402#define VADC2D  2
403#define VADC1D  1
404#define VADC0D  0
405
406/* Reserved [0x82..0x83] */
407
408/* Timer/Counter 1 Control and Status Register */
409#define TCCR1B  _SFR_MEM8(0x81)
410#define CTC1    3
411#define CS12    2
412#define CS11    1
413#define CS10    0
414
415/* Reserved [0x82..0x83] */
416
417/* Timer/Counter 1 */
418#define TCNT1   _SFR_MEM16(0x84)
419#define TCNT1L  _SFR_MEM8(0x84)
420#define TCNT1H  _SFR_MEM8(0x85)
421
422/* Reserved [0x86..0x87] */
423
424/* Timer/Counter1 Output Compare Register A */
425#define OCR1A   _SFR_MEM16(0x88)
426#define OCR1AL  _SFR_MEM8(0x88)
427#define OCR1AH  _SFR_MEM8(0x89)
428
429/* Reserved [0x8A..0xB7] */
430
431/* 2-wire Serial Interface Bit Rate Register */
432#define TWBR    _SFR_MEM8(0xB8)
433
434/* 2-wire Serial Interface Status Register */
435#define TWSR    _SFR_MEM8(0xB9)
436#define TWS7    7
437#define TWS6    6
438#define TWS5    5
439#define TWS4    4
440#define TWS3    3
441#define TWPS1   1
442#define TWPS0   0
443
444/* 2-wire Serial Interface Address Register */
445#define TWAR    _SFR_MEM8(0xBA)
446#define TWA6    7
447#define TWA5    6
448#define TWA4    5
449#define TWA3    4
450#define TWA2    3
451#define TWA1    2
452#define TWA0    1
453#define TWGCE   0
454
455/* 2-wire Serial Interface Data Register */
456#define TWDR    _SFR_MEM8(0xBB)
457
458/* 2-wire Serial Interface Control Register */
459#define TWCR    _SFR_MEM8(0xBC)
460#define TWINT   7
461#define TWEA    6
462#define TWSTA   5
463#define TWSTO   4
464#define TWWC    3
465#define TWEN    2
466#define TWIE    0
467
468/* 2-wire Serial (Slave) Address Mask Register */
469#define TWAMR   _SFR_MEM8(0xBD)
470#define TWAM6   7
471#define TWAM5   6
472#define TWAM4   5
473#define TWAM3   4
474#define TWAM2   3
475#define TWAM1   2
476#define TWAM0   1
477
478/* 2-wire Serial Bus Control and Status Register */
479#define TWBCSR  _SFR_MEM8(0xBE)
480#define TWBCIF  7
481#define TWBCIE  6
482#define TWBDT1  2
483#define TWBDT0  1
484#define TWBCIP  0
485
486/* Reserved [0xBF] */
487
488/* Clock Control Status Register */
489#define CCSR    _SFR_MEM8(0xC0)
490#define XOE     1
491#define ACS     0
492
493/* Reserved [0xC1..0xCF] */
494
495/* Bandgap Calibration C Register */
496#define BGCCR   _SFR_MEM8(0xD0)
497#define BGEN    7
498#define BGCC5   5
499#define BGCC4   4
500#define BGCC3   3
501#define BGCC2   2
502#define BGCC1   1
503#define BGCC0   0
504
505/* Bandgap Calibration R Register */
506#define BGCRR   _SFR_MEM8(0xD1)
507#define BGCR7   7
508#define BGCR6   6
509#define BGCR5   5
510#define BGCR4   4
511#define BGCR3   3
512#define BGCR2   2
513#define BGCR1   1
514#define BGCR0   0
515
516/* Reserved [0xD2..0xDF] */
517
518/* CC-ADC Accumulate Current */
519/* TODO: Add _SFR_MEM32 */
520/* #define CADAC   _SFR_MEM32(0xE0) */
521#define CADAC0  _SFR_MEM8(0xE0)
522#define CADAC1  _SFR_MEM8(0xE1)
523#define CADAC2  _SFR_MEM8(0xE2)
524#define CADAC3  _SFR_MEM8(0xE3)
525
526/* CC-ADC Control and Status Register A */
527#define CADCSRA _SFR_MEM8(0xE4)
528#define CADEN   7
529#define CADUB   5
530#define CADAS1  4
531#define CADAS0  3
532#define CADSI1  2
533#define CADSI0  1
534#define CADSE   0
535
536/* CC-ADC Control and Status Register B */
537#define CADCSRB _SFR_MEM8(0xE5)
538#define CADACIE 6
539#define CADRCIE 5
540#define CADICIE 4
541#define CADACIF 2
542#define CADRCIF 1
543#define CADICIF 0
544
545/* CC-ADC Regular Charge Current */
546#define CADRCC  _SFR_MEM8(0xE6)
547
548/* CC-ADC Regular Discharge Current */
549#define CADRDC  _SFR_MEM8(0xE7)
550
551/* CC-ADC Instantaneous Current */
552#define CADIC   _SFR_MEM16(0xE8)
553#define CADICL  _SFR_MEM8(0xE8)
554#define CADICH  _SFR_MEM8(0xE9)
555
556/* Reserved [0xEA..0xEF] */
557
558/* FET Control and Status Register */
559#define FCSR    _SFR_MEM8(0xF0)
560#define PWMOC   5
561#define PWMOPC  4
562#define CPS     3
563#define DFE     2
564#define CFE     1
565#define PFD     0
566
567/* Cell Balancing Control Register */
568#define CBCR    _SFR_MEM8(0xF1)
569#define CBE4    3
570#define CBE3    2
571#define CBE2    1
572#define CBE1    0
573
574/* Battery Protection Interrupt Register */
575#define BPIR    _SFR_MEM8(0xF2)
576#define DUVIF   7
577#define COCIF   6
578#define DOCIF   5
579#define SCIF    4
580#define DUVIE   3
581#define COCIE   2
582#define DOCIE   1
583#define SCIE    0
584
585/* Battery Protection Deep Under Voltage Register */
586#define BPDUV   _SFR_MEM8(0xF3)
587#define DUVT1   5
588#define DUVT0   4
589#define DUDL3   3
590#define DUDL2   2
591#define DUDL1   1
592#define DUDL0   0
593
594/* Battery Protection Short-circuit Detection Level Register */
595#define BPSCD   _SFR_MEM8(0xF4)
596#define SCDL3   3
597#define SCDL2   2
598#define SCDL1   1
599#define SCDL0   0
600
601/* Battery Protection Over-current Detection Level Register */
602#define BPOCD   _SFR_MEM8(0xF5)
603#define DCDL3   7
604#define DCDL2   6
605#define DCDL1   5
606#define DCDL0   4
607#define CCDL3   3
608#define CCDL2   2
609#define CCDL1   1
610#define CCDL0   0
611
612/* Current Battery Protection Timing Register */
613#define CBPTR   _SFR_MEM8(0xF6)
614#define SCPT3   7
615#define SCPT2   6
616#define SCPT1   5
617#define SCPT0   4
618#define OCPT3   3
619#define OCPT2   2
620#define OCPT1   1
621#define OCPT0   0
622
623/* Battery Protection Control Register */
624#define BPCR    _SFR_MEM8(0xF7)
625#define DUVD    3
626#define SCD     2
627#define DCD     1
628#define CCD     0
629
630/* Battery Protection Parameter Lock Register */
631#define BPPLR   _SFR_MEM8(0xF8)
632#define BPPLE   1
633#define BPPL    0
634
635/* Reserved [0xF9..0xFF] */
636
637/* Interrupt vectors */
638/* Battery Protection Interrupt */
639#define BPINT_vect                      _VECTOR(1)
640
641
642/* External Interrupt Request 0 */
643#define INT0_vect                       _VECTOR(2)
644
645
646/* External Interrupt Request 1 */
647#define INT1_vect                       _VECTOR(3)
648
649
650/* External Interrupt Request 2 */
651#define INT2_vect                       _VECTOR(4)
652
653
654/* External Interrupt Request 3 */
655#define INT3_vect                       _VECTOR(5)
656
657
658/* Pin Change Interrupt 0 */
659#define PCINT0_vect                     _VECTOR(6)
660
661
662/* Pin Change Interrupt 1 */
663#define PCINT1_vect                     _VECTOR(7)
664
665
666/* Watchdog Timeout Interrupt */
667#define WDT_vect                        _VECTOR(8)
668
669
670/* Wakeup timer overflow */
671#define WAKE_UP_vect                    _VECTOR(9)
672
673
674/* Timer/Counter 1 Compare Match */
675#define TIM1_COMP_vect                  _VECTOR(10)
676
677
678/* Timer/Counter 1 Overflow */
679#define TIM1_OVF_vect                   _VECTOR(11)
680
681
682/* Timer/Counter0 Compare A Match */
683#define TIM0_COMPA_vect                 _VECTOR(12)
684
685
686/* Timer/Counter0 Compare B Match */
687#define TIM0_COMPB_vect                 _VECTOR(13)
688
689
690/* Timer/Counter0 Overflow */
691#define TIM0_OVF_vect                   _VECTOR(14)
692
693
694/* Two-Wire Bus Connect/Disconnect */
695#define TWI_BUS_CD_vect                 _VECTOR(15)
696
697
698/* Two-Wire Serial Interface */
699#define TWI_vect                        _VECTOR(16)
700
701
702/* Voltage ADC Conversion Complete */
703#define VADC_vect                       _VECTOR(17)
704
705
706/* Coulomb Counter ADC Conversion Complete */
707#define CCADC_CONV_vect                 _VECTOR(18)
708
709/* Coloumb Counter ADC Regular Current */
710#define CCADC_REG_CUR_vect              _VECTOR(19)
711
712
713/* Coloumb Counter ADC Accumulator */
714#define CCADC_ACC_vect                  _VECTOR(20)
715
716
717/* EEPROM Ready */
718#define EE_READY_vect                   _VECTOR(21)
719
720
721/* Store Program Memory Ready */
722#define SPM_READY_vect                  _VECTOR(22)
723
724#define _VECTORS_SIZE 92
725
726/* Constants */
727#define SPM_PAGESIZE 128
728#define RAMEND       0x8FF
729#define XRAMEND      RAMEND
730#define E2END        0x1FF
731#define E2PAGESIZE   4
732#define FLASHEND     0x9FFF
733
734
735/* Fuses */
736
737#define FUSE_MEMORY_SIZE 2
738
739/* Low Fuse Byte */
740#define FUSE_CKSEL   (unsigned char)~_BV(0)
741#define FUSE_SUT0    (unsigned char)~_BV(1)
742#define FUSE_SUT1    (unsigned char)~_BV(2)
743#define FUSE_BOOTRST (unsigned char)~_BV(3)
744#define FUSE_BOOTSZ0 (unsigned char)~_BV(4)
745#define FUSE_BOOTSZ1 (unsigned char)~_BV(5)
746#define FUSE_EESAVE  (unsigned char)~_BV(6)
747#define FUSE_WDTON   (unsigned char)~_BV(7)
748#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
749
750/* High Fuse Byte */
751#define FUSE_JTAGEN      (unsigned char)~_BV(0)
752#define FUSE_OCDEN       (unsigned char)~_BV(1)
753#define HFUSE_DEFAULT (FUSE_JTAGEN)
754
755
756/* Lock Bits */
757#define __LOCK_BITS_EXIST
758#define __BOOT_LOCK_BITS_0_EXIST
759#define __BOOT_LOCK_BITS_1_EXIST
760
761
762/* Signature */
763#define SIGNATURE_0 0x1E
764#define SIGNATURE_1 0x95
765#define SIGNATURE_2 0x07
766
767
768#endif /* _AVR_IOM406_H_ */
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