[04a62dce] | 1 | /* Copyright (c) 2006, Pieter Conradie |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/iom406.h - definitions for ATmega406 */ |
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| 34 | |
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| 35 | #ifndef _AVR_IOM406_H_ |
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| 36 | #define _AVR_IOM406_H_ 1 |
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| 37 | |
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| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 39 | |
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| 40 | #ifndef _AVR_IO_H_ |
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| 41 | # error "Include <avr/io.h> instead of this file." |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifndef _AVR_IOXXX_H_ |
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| 45 | # define _AVR_IOXXX_H_ "iom406.h" |
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| 46 | #else |
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| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 48 | #endif |
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| 49 | |
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| 50 | /* I/O registers */ |
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| 51 | |
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| 52 | #define PINA _SFR_IO8(0x00) |
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| 53 | #define PINA7 7 |
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| 54 | #define PINA6 6 |
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| 55 | #define PINA5 5 |
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| 56 | #define PINA4 4 |
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| 57 | #define PINA3 3 |
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| 58 | #define PINA2 2 |
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| 59 | #define PINA1 1 |
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| 60 | #define PINA0 0 |
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| 61 | |
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| 62 | #define DDRA _SFR_IO8(0x01) |
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| 63 | #define DDA7 7 |
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| 64 | #define DDA6 6 |
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| 65 | #define DDA5 5 |
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| 66 | #define DDA4 4 |
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| 67 | #define DDA3 3 |
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| 68 | #define DDA2 2 |
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| 69 | #define DDA1 1 |
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| 70 | #define DDA0 0 |
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| 71 | |
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| 72 | #define PORTA _SFR_IO8(0x02) |
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| 73 | #define PA7 7 |
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| 74 | #define PA6 6 |
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| 75 | #define PA5 5 |
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| 76 | #define PA4 4 |
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| 77 | #define PA3 3 |
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| 78 | #define PA2 2 |
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| 79 | #define PA1 1 |
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| 80 | #define PA0 0 |
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| 81 | |
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| 82 | #define PINB _SFR_IO8(0x03) |
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| 83 | #define PINB7 7 |
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| 84 | #define PINB6 6 |
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| 85 | #define PINB5 5 |
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| 86 | #define PINB4 4 |
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| 87 | #define PINB3 3 |
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| 88 | #define PINB2 2 |
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| 89 | #define PINB1 1 |
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| 90 | #define PINB0 0 |
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| 91 | |
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| 92 | #define DDRB _SFR_IO8(0x04) |
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| 93 | #define DDB7 7 |
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| 94 | #define DDB6 6 |
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| 95 | #define DDB5 5 |
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| 96 | #define DDB4 4 |
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| 97 | #define DDB3 3 |
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| 98 | #define DDB2 2 |
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| 99 | #define DDB1 1 |
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| 100 | #define DDB0 0 |
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| 101 | |
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| 102 | #define PORTB _SFR_IO8(0x05) |
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| 103 | #define PB7 7 |
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| 104 | #define PB6 6 |
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| 105 | #define PB5 5 |
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| 106 | #define PB4 4 |
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| 107 | #define PB3 3 |
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| 108 | #define PB2 2 |
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| 109 | #define PB1 1 |
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| 110 | #define PB0 0 |
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| 111 | |
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| 112 | /* Reserved [0x06..0x07] */ |
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| 113 | |
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| 114 | #define PORTC _SFR_IO8(0x08) |
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| 115 | #define PC0 0 |
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| 116 | |
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| 117 | #define PIND _SFR_IO8(0x09) |
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| 118 | #define PIND1 1 |
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| 119 | #define PIND0 0 |
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| 120 | |
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| 121 | #define DDRD _SFR_IO8(0x0A) |
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| 122 | #define DDD1 1 |
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| 123 | #define DDD0 0 |
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| 124 | |
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| 125 | #define PORTD _SFR_IO8(0x0B) |
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| 126 | #define PD1 1 |
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| 127 | #define PD0 0 |
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| 128 | |
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| 129 | /* Reserved [0x0C..0x14] */ |
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| 130 | |
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| 131 | /* Timer/Counter0 Interrupt Flag Register */ |
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| 132 | #define TIFR0 _SFR_IO8(0x15) |
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| 133 | #define OCF0B 2 |
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| 134 | #define OCF0A 1 |
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| 135 | #define TOV0 0 |
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| 136 | |
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| 137 | /* Timer/Counter1 Interrupt Flag Register */ |
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| 138 | #define TIFR1 _SFR_IO8(0x16) |
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| 139 | #define OCF1A 1 |
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| 140 | #define TOV1 0 |
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| 141 | |
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| 142 | /* Reserved [0x17..0x1A] */ |
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| 143 | |
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| 144 | /* Pin Change Interrupt Control Register */ |
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| 145 | #define PCIFR _SFR_IO8(0x1B) |
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| 146 | #define PCIF1 1 |
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| 147 | #define PCIF0 0 |
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| 148 | |
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| 149 | /* External Interrupt Flag Register */ |
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| 150 | #define EIFR _SFR_IO8(0x1C) |
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| 151 | #define INTF3 3 |
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| 152 | #define INTF2 2 |
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| 153 | #define INTF1 1 |
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| 154 | #define INTF0 0 |
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| 155 | |
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| 156 | /* External Interrupt MaSK register */ |
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| 157 | #define EIMSK _SFR_IO8(0x1D) |
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| 158 | #define INT3 3 |
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| 159 | #define INT2 2 |
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| 160 | #define INT1 1 |
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| 161 | #define INT0 0 |
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| 162 | |
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| 163 | /* General Purpose I/O Register 0 */ |
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| 164 | #define GPIOR0 _SFR_IO8(0x1E) |
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| 165 | |
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| 166 | /* EEPROM Control Register */ |
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| 167 | #define EECR _SFR_IO8(0x1F) |
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| 168 | #define EEPM1 5 |
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| 169 | #define EEPM0 4 |
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| 170 | #define EERIE 3 |
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| 171 | #define EEMPE 2 |
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| 172 | #define EEPE 1 |
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| 173 | #define EERE 0 |
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| 174 | |
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| 175 | /* EEPROM Data Register */ |
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| 176 | #define EEDR _SFR_IO8(0x20) |
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| 177 | |
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| 178 | /* EEPROM Address Register */ |
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| 179 | #define EEAR _SFR_IO16(0x21) |
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| 180 | #define EEARL _SFR_IO8(0x21) |
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| 181 | #define EEARH _SFR_IO8(0x22) |
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| 182 | |
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| 183 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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| 184 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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| 185 | subroutines. |
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| 186 | First two letters: EECR address. |
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| 187 | Second two letters: EEDR address. |
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| 188 | Last two letters: EEAR address. */ |
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| 189 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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| 190 | |
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| 191 | /* General Timer/Counter Control Register */ |
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| 192 | #define GTCCR _SFR_IO8(0x23) |
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| 193 | #define TSM 7 |
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| 194 | #define PSRSYNC 0 |
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| 195 | |
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| 196 | /* Timer/Counter Control Register A */ |
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| 197 | #define TCCR0A _SFR_IO8(0x24) |
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| 198 | #define COM0A1 7 |
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| 199 | #define COM0A0 6 |
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| 200 | #define COM0B1 5 |
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| 201 | #define COM0B0 4 |
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| 202 | #define WGM01 1 |
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| 203 | #define WGM00 0 |
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| 204 | |
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| 205 | /* Timer/Counter Control Register B */ |
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| 206 | #define TCCR0B _SFR_IO8(0x25) |
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| 207 | #define FOC0A 7 |
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| 208 | #define FOC0B 6 |
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| 209 | #define WGM02 3 |
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| 210 | #define CS02 2 |
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| 211 | #define CS01 1 |
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| 212 | #define CS00 0 |
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| 213 | |
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| 214 | /* Timer/Counter 0 */ |
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| 215 | #define TCNT0 _SFR_IO8(0x26) |
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| 216 | |
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| 217 | /* Output Compare Register A */ |
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| 218 | #define OCR0A _SFR_IO8(0x27) |
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| 219 | |
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| 220 | /* Output Compare Register B */ |
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| 221 | #define OCR0B _SFR_IO8(0x28) |
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| 222 | |
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| 223 | /* Reserved [0x29] */ |
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| 224 | |
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| 225 | /* General Purpose I/O Register 1 */ |
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| 226 | #define GPIOR1 _SFR_IO8(0x2A) |
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| 227 | |
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| 228 | /* General Purpose I/O Register 2 */ |
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| 229 | #define GPIOR2 _SFR_IO8(0x2B) |
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| 230 | |
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| 231 | /* Reserved [0x2C..0x30] */ |
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| 232 | |
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| 233 | /* On-chip Debug Register */ |
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| 234 | #define OCDR _SFR_IO8(0x31) |
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| 235 | |
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| 236 | /* Reserved [0x32] */ |
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| 237 | |
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| 238 | /* Sleep Mode Control Register */ |
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| 239 | #define SMCR _SFR_IO8(0x33) |
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| 240 | #define SM2 3 |
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| 241 | #define SM1 2 |
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| 242 | #define SM0 1 |
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| 243 | #define SE 0 |
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| 244 | |
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| 245 | /* MCU Status Register */ |
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| 246 | #define MCUSR _SFR_IO8(0x34) |
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| 247 | #define JTRF 4 |
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| 248 | #define WDRF 3 |
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| 249 | #define BODRF 2 |
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| 250 | #define EXTRF 1 |
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| 251 | #define PORF 0 |
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| 252 | |
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| 253 | /* MCU general Control Register */ |
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| 254 | #define MCUCR _SFR_IO8(0x35) |
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| 255 | #define JTD 7 |
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| 256 | #define PUD 4 |
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| 257 | #define IVSEL 1 |
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| 258 | #define IVCE 0 |
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| 259 | |
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| 260 | /* Reserved [0x36] */ |
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| 261 | |
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| 262 | /* Store Program Memory Control and Status Register */ |
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| 263 | #define SPMCSR _SFR_IO8(0x37) |
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| 264 | #define SPMIE 7 |
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| 265 | #define RWWSB 6 |
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| 266 | #define SIGRD 5 |
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| 267 | #define RWWSRE 4 |
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| 268 | #define BLBSET 3 |
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| 269 | #define PGWRT 2 |
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| 270 | #define PGERS 1 |
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| 271 | #define SPMEN 0 |
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| 272 | |
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| 273 | /* Reserved [0x36..0x3C] */ |
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| 274 | |
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| 275 | /* 0x3D..0x3E SP */ |
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| 276 | |
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| 277 | /* 0x3F SREG */ |
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| 278 | |
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| 279 | /* Extended I/O registers */ |
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| 280 | |
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| 281 | /* Watchdog Timer Control Register */ |
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| 282 | #define WDTCSR _SFR_MEM8(0x60) |
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| 283 | #define WDIF 7 |
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| 284 | #define WDIE 6 |
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| 285 | #define WDP3 5 |
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| 286 | #define WDCE 4 |
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| 287 | #define WDE 3 |
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| 288 | #define WDP2 2 |
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| 289 | #define WDP1 1 |
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| 290 | #define WDP0 0 |
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| 291 | |
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| 292 | /* Reserved [0x61] */ |
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| 293 | |
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| 294 | /* Wake-up Timer Control and Status Register */ |
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| 295 | #define WUTCSR _SFR_MEM8(0x62) |
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| 296 | #define WUTIF 7 |
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| 297 | #define WUTIE 6 |
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| 298 | #define WUTCF 5 |
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| 299 | #define WUTR 4 |
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| 300 | #define WUTE 3 |
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| 301 | #define WUTP2 2 |
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| 302 | #define WUTP1 1 |
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| 303 | #define WUTP0 0 |
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| 304 | |
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| 305 | /* Reserved [0x63] */ |
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| 306 | |
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| 307 | /* Power Reduction Register 0 */ |
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| 308 | #define PRR0 _SFR_MEM8(0x64) |
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| 309 | #define PRTWI 3 |
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| 310 | #define PRTIM1 2 |
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| 311 | #define PRTIM0 1 |
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| 312 | #define PRVADC 0 |
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| 313 | |
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| 314 | /* Reserved [0x65] */ |
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| 315 | |
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| 316 | /* Fast Oscillator Calibration Register */ |
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| 317 | #define FOSCCAL _SFR_MEM8(0x66) |
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| 318 | |
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| 319 | /* Reserved [0x67] */ |
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| 320 | |
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| 321 | /* Pin Change Interrupt Control Register */ |
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| 322 | #define PCICR _SFR_MEM8(0x68) |
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| 323 | #define PCIE1 1 |
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| 324 | #define PCIE0 0 |
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| 325 | |
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| 326 | /* External Interrupt Control Register A */ |
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| 327 | #define EICRA _SFR_MEM8(0x69) |
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| 328 | #define ISC31 7 |
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| 329 | #define ISC30 6 |
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| 330 | #define ISC21 5 |
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| 331 | #define ISC20 4 |
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| 332 | #define ISC11 3 |
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| 333 | #define ISC10 2 |
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| 334 | #define ISC01 1 |
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| 335 | #define ISC00 0 |
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| 336 | |
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| 337 | /* Reserved [0x6A] */ |
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| 338 | |
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| 339 | /* Pin Change Mask Register 0 */ |
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| 340 | #define PCMSK0 _SFR_MEM8(0x6B) |
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| 341 | #define PCINT7 7 |
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| 342 | #define PCINT6 6 |
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| 343 | #define PCINT5 5 |
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| 344 | #define PCINT4 4 |
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| 345 | #define PCINT3 3 |
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| 346 | #define PCINT2 2 |
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| 347 | #define PCINT1 1 |
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| 348 | #define PCINT0 0 |
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| 349 | |
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| 350 | /* Pin Change Mask Register 1 */ |
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| 351 | #define PCMSK1 _SFR_MEM8(0x6C) |
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| 352 | #define PCINT15 7 |
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| 353 | #define PCINT14 6 |
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| 354 | #define PCINT13 5 |
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| 355 | #define PCINT12 4 |
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| 356 | #define PCINT11 3 |
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| 357 | #define PCINT10 2 |
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| 358 | #define PCINT9 1 |
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| 359 | #define PCINT8 0 |
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| 360 | |
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| 361 | /* Reserved [0x6D] */ |
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| 362 | |
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| 363 | /* Timer/Counter Interrupt MaSK register 0 */ |
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| 364 | #define TIMSK0 _SFR_MEM8(0x6E) |
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| 365 | #define OCIE0B 2 |
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| 366 | #define OCIE0A 1 |
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| 367 | #define TOIE0 0 |
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| 368 | |
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| 369 | /* Timer/Counter Interrupt MaSK register 1 */ |
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| 370 | #define TIMSK1 _SFR_MEM8(0x6F) |
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| 371 | #define OCIE1A 1 |
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| 372 | #define TOIE1 0 |
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| 373 | |
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| 374 | /* Reserved [0x70..0x77] */ |
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| 375 | |
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| 376 | /* V-ADC Data Register */ |
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| 377 | #define VADC _SFR_MEM16(0x78) |
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| 378 | #define VADCL _SFR_MEM8(0x78) |
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| 379 | #define VADCH _SFR_MEM8(0x79) |
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| 380 | |
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| 381 | /* V-ADC Control and Status Register */ |
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| 382 | #define VADCSR _SFR_MEM8(0x7A) |
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| 383 | #define VADEN 3 |
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| 384 | #define VADSC 2 |
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| 385 | #define VADCCIF 1 |
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| 386 | #define VADCCIE 0 |
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| 387 | |
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| 388 | /* Reserved [0x7B] */ |
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| 389 | |
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| 390 | /* V-ADC Multiplexer Selection Register */ |
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| 391 | #define VADMUX _SFR_MEM8(0x7C) |
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| 392 | #define VADMUX3 3 |
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| 393 | #define VADMUX2 2 |
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| 394 | #define VADMUX1 1 |
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| 395 | #define VADMUX0 0 |
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| 396 | |
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| 397 | /* Reserved [0x7D] */ |
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| 398 | |
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| 399 | /* Digital Input Disable Register 0 */ |
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| 400 | #define DIDR0 _SFR_MEM8(0x7E) |
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| 401 | #define VADC3D 3 |
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| 402 | #define VADC2D 2 |
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| 403 | #define VADC1D 1 |
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| 404 | #define VADC0D 0 |
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| 405 | |
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| 406 | /* Reserved [0x82..0x83] */ |
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| 407 | |
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| 408 | /* Timer/Counter 1 Control and Status Register */ |
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| 409 | #define TCCR1B _SFR_MEM8(0x81) |
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| 410 | #define CTC1 3 |
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| 411 | #define CS12 2 |
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| 412 | #define CS11 1 |
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| 413 | #define CS10 0 |
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| 414 | |
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| 415 | /* Reserved [0x82..0x83] */ |
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| 416 | |
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| 417 | /* Timer/Counter 1 */ |
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| 418 | #define TCNT1 _SFR_MEM16(0x84) |
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| 419 | #define TCNT1L _SFR_MEM8(0x84) |
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| 420 | #define TCNT1H _SFR_MEM8(0x85) |
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| 421 | |
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| 422 | /* Reserved [0x86..0x87] */ |
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| 423 | |
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| 424 | /* Timer/Counter1 Output Compare Register A */ |
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| 425 | #define OCR1A _SFR_MEM16(0x88) |
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| 426 | #define OCR1AL _SFR_MEM8(0x88) |
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| 427 | #define OCR1AH _SFR_MEM8(0x89) |
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| 428 | |
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| 429 | /* Reserved [0x8A..0xB7] */ |
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| 430 | |
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| 431 | /* 2-wire Serial Interface Bit Rate Register */ |
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| 432 | #define TWBR _SFR_MEM8(0xB8) |
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| 433 | |
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| 434 | /* 2-wire Serial Interface Status Register */ |
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| 435 | #define TWSR _SFR_MEM8(0xB9) |
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| 436 | #define TWS7 7 |
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| 437 | #define TWS6 6 |
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| 438 | #define TWS5 5 |
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| 439 | #define TWS4 4 |
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| 440 | #define TWS3 3 |
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| 441 | #define TWPS1 1 |
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| 442 | #define TWPS0 0 |
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| 443 | |
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| 444 | /* 2-wire Serial Interface Address Register */ |
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| 445 | #define TWAR _SFR_MEM8(0xBA) |
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| 446 | #define TWA6 7 |
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| 447 | #define TWA5 6 |
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| 448 | #define TWA4 5 |
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| 449 | #define TWA3 4 |
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| 450 | #define TWA2 3 |
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| 451 | #define TWA1 2 |
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| 452 | #define TWA0 1 |
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| 453 | #define TWGCE 0 |
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| 454 | |
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| 455 | /* 2-wire Serial Interface Data Register */ |
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| 456 | #define TWDR _SFR_MEM8(0xBB) |
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| 457 | |
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| 458 | /* 2-wire Serial Interface Control Register */ |
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| 459 | #define TWCR _SFR_MEM8(0xBC) |
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| 460 | #define TWINT 7 |
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| 461 | #define TWEA 6 |
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| 462 | #define TWSTA 5 |
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| 463 | #define TWSTO 4 |
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| 464 | #define TWWC 3 |
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| 465 | #define TWEN 2 |
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| 466 | #define TWIE 0 |
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| 467 | |
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| 468 | /* 2-wire Serial (Slave) Address Mask Register */ |
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| 469 | #define TWAMR _SFR_MEM8(0xBD) |
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| 470 | #define TWAM6 7 |
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| 471 | #define TWAM5 6 |
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| 472 | #define TWAM4 5 |
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| 473 | #define TWAM3 4 |
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| 474 | #define TWAM2 3 |
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| 475 | #define TWAM1 2 |
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| 476 | #define TWAM0 1 |
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| 477 | |
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| 478 | /* 2-wire Serial Bus Control and Status Register */ |
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| 479 | #define TWBCSR _SFR_MEM8(0xBE) |
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| 480 | #define TWBCIF 7 |
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| 481 | #define TWBCIE 6 |
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| 482 | #define TWBDT1 2 |
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| 483 | #define TWBDT0 1 |
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| 484 | #define TWBCIP 0 |
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| 485 | |
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| 486 | /* Reserved [0xBF] */ |
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| 487 | |
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| 488 | /* Clock Control Status Register */ |
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| 489 | #define CCSR _SFR_MEM8(0xC0) |
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| 490 | #define XOE 1 |
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| 491 | #define ACS 0 |
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| 492 | |
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| 493 | /* Reserved [0xC1..0xCF] */ |
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| 494 | |
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| 495 | /* Bandgap Calibration C Register */ |
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| 496 | #define BGCCR _SFR_MEM8(0xD0) |
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| 497 | #define BGEN 7 |
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| 498 | #define BGCC5 5 |
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| 499 | #define BGCC4 4 |
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| 500 | #define BGCC3 3 |
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| 501 | #define BGCC2 2 |
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| 502 | #define BGCC1 1 |
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| 503 | #define BGCC0 0 |
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| 504 | |
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| 505 | /* Bandgap Calibration R Register */ |
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| 506 | #define BGCRR _SFR_MEM8(0xD1) |
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| 507 | #define BGCR7 7 |
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| 508 | #define BGCR6 6 |
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| 509 | #define BGCR5 5 |
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| 510 | #define BGCR4 4 |
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| 511 | #define BGCR3 3 |
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| 512 | #define BGCR2 2 |
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| 513 | #define BGCR1 1 |
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| 514 | #define BGCR0 0 |
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| 515 | |
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| 516 | /* Reserved [0xD2..0xDF] */ |
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| 517 | |
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| 518 | /* CC-ADC Accumulate Current */ |
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| 519 | /* TODO: Add _SFR_MEM32 */ |
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| 520 | /* #define CADAC _SFR_MEM32(0xE0) */ |
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| 521 | #define CADAC0 _SFR_MEM8(0xE0) |
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| 522 | #define CADAC1 _SFR_MEM8(0xE1) |
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| 523 | #define CADAC2 _SFR_MEM8(0xE2) |
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| 524 | #define CADAC3 _SFR_MEM8(0xE3) |
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| 525 | |
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| 526 | /* CC-ADC Control and Status Register A */ |
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| 527 | #define CADCSRA _SFR_MEM8(0xE4) |
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| 528 | #define CADEN 7 |
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| 529 | #define CADUB 5 |
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| 530 | #define CADAS1 4 |
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| 531 | #define CADAS0 3 |
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| 532 | #define CADSI1 2 |
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| 533 | #define CADSI0 1 |
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| 534 | #define CADSE 0 |
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| 535 | |
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| 536 | /* CC-ADC Control and Status Register B */ |
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| 537 | #define CADCSRB _SFR_MEM8(0xE5) |
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| 538 | #define CADACIE 6 |
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| 539 | #define CADRCIE 5 |
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| 540 | #define CADICIE 4 |
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| 541 | #define CADACIF 2 |
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| 542 | #define CADRCIF 1 |
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| 543 | #define CADICIF 0 |
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| 544 | |
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| 545 | /* CC-ADC Regular Charge Current */ |
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| 546 | #define CADRCC _SFR_MEM8(0xE6) |
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| 547 | |
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| 548 | /* CC-ADC Regular Discharge Current */ |
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| 549 | #define CADRDC _SFR_MEM8(0xE7) |
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| 550 | |
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| 551 | /* CC-ADC Instantaneous Current */ |
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| 552 | #define CADIC _SFR_MEM16(0xE8) |
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| 553 | #define CADICL _SFR_MEM8(0xE8) |
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| 554 | #define CADICH _SFR_MEM8(0xE9) |
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| 555 | |
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| 556 | /* Reserved [0xEA..0xEF] */ |
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| 557 | |
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| 558 | /* FET Control and Status Register */ |
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| 559 | #define FCSR _SFR_MEM8(0xF0) |
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| 560 | #define PWMOC 5 |
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| 561 | #define PWMOPC 4 |
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| 562 | #define CPS 3 |
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| 563 | #define DFE 2 |
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| 564 | #define CFE 1 |
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| 565 | #define PFD 0 |
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| 566 | |
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| 567 | /* Cell Balancing Control Register */ |
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| 568 | #define CBCR _SFR_MEM8(0xF1) |
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| 569 | #define CBE4 3 |
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| 570 | #define CBE3 2 |
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| 571 | #define CBE2 1 |
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| 572 | #define CBE1 0 |
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| 573 | |
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| 574 | /* Battery Protection Interrupt Register */ |
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| 575 | #define BPIR _SFR_MEM8(0xF2) |
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| 576 | #define DUVIF 7 |
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| 577 | #define COCIF 6 |
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| 578 | #define DOCIF 5 |
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| 579 | #define SCIF 4 |
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| 580 | #define DUVIE 3 |
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| 581 | #define COCIE 2 |
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| 582 | #define DOCIE 1 |
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| 583 | #define SCIE 0 |
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| 584 | |
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| 585 | /* Battery Protection Deep Under Voltage Register */ |
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| 586 | #define BPDUV _SFR_MEM8(0xF3) |
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| 587 | #define DUVT1 5 |
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| 588 | #define DUVT0 4 |
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| 589 | #define DUDL3 3 |
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| 590 | #define DUDL2 2 |
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| 591 | #define DUDL1 1 |
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| 592 | #define DUDL0 0 |
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| 593 | |
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| 594 | /* Battery Protection Short-circuit Detection Level Register */ |
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| 595 | #define BPSCD _SFR_MEM8(0xF4) |
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| 596 | #define SCDL3 3 |
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| 597 | #define SCDL2 2 |
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| 598 | #define SCDL1 1 |
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| 599 | #define SCDL0 0 |
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| 600 | |
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| 601 | /* Battery Protection Over-current Detection Level Register */ |
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| 602 | #define BPOCD _SFR_MEM8(0xF5) |
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| 603 | #define DCDL3 7 |
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| 604 | #define DCDL2 6 |
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| 605 | #define DCDL1 5 |
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| 606 | #define DCDL0 4 |
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| 607 | #define CCDL3 3 |
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| 608 | #define CCDL2 2 |
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| 609 | #define CCDL1 1 |
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| 610 | #define CCDL0 0 |
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| 611 | |
---|
| 612 | /* Current Battery Protection Timing Register */ |
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| 613 | #define CBPTR _SFR_MEM8(0xF6) |
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| 614 | #define SCPT3 7 |
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| 615 | #define SCPT2 6 |
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| 616 | #define SCPT1 5 |
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| 617 | #define SCPT0 4 |
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| 618 | #define OCPT3 3 |
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| 619 | #define OCPT2 2 |
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| 620 | #define OCPT1 1 |
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| 621 | #define OCPT0 0 |
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| 622 | |
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| 623 | /* Battery Protection Control Register */ |
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| 624 | #define BPCR _SFR_MEM8(0xF7) |
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| 625 | #define DUVD 3 |
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| 626 | #define SCD 2 |
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| 627 | #define DCD 1 |
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| 628 | #define CCD 0 |
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| 629 | |
---|
| 630 | /* Battery Protection Parameter Lock Register */ |
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| 631 | #define BPPLR _SFR_MEM8(0xF8) |
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| 632 | #define BPPLE 1 |
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| 633 | #define BPPL 0 |
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| 634 | |
---|
| 635 | /* Reserved [0xF9..0xFF] */ |
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| 636 | |
---|
| 637 | /* Interrupt vectors */ |
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| 638 | /* Battery Protection Interrupt */ |
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| 639 | #define BPINT_vect _VECTOR(1) |
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| 640 | |
---|
| 641 | |
---|
| 642 | /* External Interrupt Request 0 */ |
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| 643 | #define INT0_vect _VECTOR(2) |
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| 644 | |
---|
| 645 | |
---|
| 646 | /* External Interrupt Request 1 */ |
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| 647 | #define INT1_vect _VECTOR(3) |
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| 648 | |
---|
| 649 | |
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| 650 | /* External Interrupt Request 2 */ |
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| 651 | #define INT2_vect _VECTOR(4) |
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| 652 | |
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| 653 | |
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| 654 | /* External Interrupt Request 3 */ |
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| 655 | #define INT3_vect _VECTOR(5) |
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| 656 | |
---|
| 657 | |
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| 658 | /* Pin Change Interrupt 0 */ |
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| 659 | #define PCINT0_vect _VECTOR(6) |
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| 660 | |
---|
| 661 | |
---|
| 662 | /* Pin Change Interrupt 1 */ |
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| 663 | #define PCINT1_vect _VECTOR(7) |
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| 664 | |
---|
| 665 | |
---|
| 666 | /* Watchdog Timeout Interrupt */ |
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| 667 | #define WDT_vect _VECTOR(8) |
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| 668 | |
---|
| 669 | |
---|
| 670 | /* Wakeup timer overflow */ |
---|
| 671 | #define WAKE_UP_vect _VECTOR(9) |
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| 672 | |
---|
| 673 | |
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| 674 | /* Timer/Counter 1 Compare Match */ |
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| 675 | #define TIM1_COMP_vect _VECTOR(10) |
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| 676 | |
---|
| 677 | |
---|
| 678 | /* Timer/Counter 1 Overflow */ |
---|
| 679 | #define TIM1_OVF_vect _VECTOR(11) |
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| 680 | |
---|
| 681 | |
---|
| 682 | /* Timer/Counter0 Compare A Match */ |
---|
| 683 | #define TIM0_COMPA_vect _VECTOR(12) |
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| 684 | |
---|
| 685 | |
---|
| 686 | /* Timer/Counter0 Compare B Match */ |
---|
| 687 | #define TIM0_COMPB_vect _VECTOR(13) |
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| 688 | |
---|
| 689 | |
---|
| 690 | /* Timer/Counter0 Overflow */ |
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| 691 | #define TIM0_OVF_vect _VECTOR(14) |
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| 692 | |
---|
| 693 | |
---|
| 694 | /* Two-Wire Bus Connect/Disconnect */ |
---|
| 695 | #define TWI_BUS_CD_vect _VECTOR(15) |
---|
| 696 | |
---|
| 697 | |
---|
| 698 | /* Two-Wire Serial Interface */ |
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| 699 | #define TWI_vect _VECTOR(16) |
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| 700 | |
---|
| 701 | |
---|
| 702 | /* Voltage ADC Conversion Complete */ |
---|
| 703 | #define VADC_vect _VECTOR(17) |
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| 704 | |
---|
| 705 | |
---|
| 706 | /* Coulomb Counter ADC Conversion Complete */ |
---|
| 707 | #define CCADC_CONV_vect _VECTOR(18) |
---|
| 708 | |
---|
| 709 | /* Coloumb Counter ADC Regular Current */ |
---|
| 710 | #define CCADC_REG_CUR_vect _VECTOR(19) |
---|
| 711 | |
---|
| 712 | |
---|
| 713 | /* Coloumb Counter ADC Accumulator */ |
---|
| 714 | #define CCADC_ACC_vect _VECTOR(20) |
---|
| 715 | |
---|
| 716 | |
---|
| 717 | /* EEPROM Ready */ |
---|
| 718 | #define EE_READY_vect _VECTOR(21) |
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| 719 | |
---|
| 720 | |
---|
| 721 | /* Store Program Memory Ready */ |
---|
| 722 | #define SPM_READY_vect _VECTOR(22) |
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| 723 | |
---|
| 724 | #define _VECTORS_SIZE 92 |
---|
| 725 | |
---|
| 726 | /* Constants */ |
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| 727 | #define SPM_PAGESIZE 128 |
---|
| 728 | #define RAMEND 0x8FF |
---|
| 729 | #define XRAMEND RAMEND |
---|
| 730 | #define E2END 0x1FF |
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| 731 | #define E2PAGESIZE 4 |
---|
| 732 | #define FLASHEND 0x9FFF |
---|
| 733 | |
---|
| 734 | |
---|
| 735 | /* Fuses */ |
---|
| 736 | |
---|
| 737 | #define FUSE_MEMORY_SIZE 2 |
---|
| 738 | |
---|
| 739 | /* Low Fuse Byte */ |
---|
| 740 | #define FUSE_CKSEL (unsigned char)~_BV(0) |
---|
| 741 | #define FUSE_SUT0 (unsigned char)~_BV(1) |
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| 742 | #define FUSE_SUT1 (unsigned char)~_BV(2) |
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| 743 | #define FUSE_BOOTRST (unsigned char)~_BV(3) |
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| 744 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(4) |
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| 745 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(5) |
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| 746 | #define FUSE_EESAVE (unsigned char)~_BV(6) |
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| 747 | #define FUSE_WDTON (unsigned char)~_BV(7) |
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| 748 | #define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_BOOTSZ0 & FUSE_BOOTSZ1) |
---|
| 749 | |
---|
| 750 | /* High Fuse Byte */ |
---|
| 751 | #define FUSE_JTAGEN (unsigned char)~_BV(0) |
---|
| 752 | #define FUSE_OCDEN (unsigned char)~_BV(1) |
---|
| 753 | #define HFUSE_DEFAULT (FUSE_JTAGEN) |
---|
| 754 | |
---|
| 755 | |
---|
| 756 | /* Lock Bits */ |
---|
| 757 | #define __LOCK_BITS_EXIST |
---|
| 758 | #define __BOOT_LOCK_BITS_0_EXIST |
---|
| 759 | #define __BOOT_LOCK_BITS_1_EXIST |
---|
| 760 | |
---|
| 761 | |
---|
| 762 | /* Signature */ |
---|
| 763 | #define SIGNATURE_0 0x1E |
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| 764 | #define SIGNATURE_1 0x95 |
---|
| 765 | #define SIGNATURE_2 0x07 |
---|
| 766 | |
---|
| 767 | |
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| 768 | #endif /* _AVR_IOM406_H_ */ |
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