source: rtems/cpukit/score/cpu/avr/avr/iom32u6.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 27.6 KB
Line 
1/* Copyright (c) 2008 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom32u6.h - definitions for ATmega32U6 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iom32u6.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATmega32U6_H_
49#define _AVR_ATmega32U6_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINA _SFR_IO8(0x00)
55#define PINA0 0
56#define PINA1 1
57#define PINA2 2
58#define PINA3 3
59#define PINA4 4
60#define PINA5 5
61#define PINA6 6
62#define PINA7 7
63
64#define DDRA _SFR_IO8(0x01)
65#define DDA0 0
66#define DDA1 1
67#define DDA2 2
68#define DDA3 3
69#define DDA4 4
70#define DDA5 5
71#define DDA6 6
72#define DDA7 7
73
74#define PORTA _SFR_IO8(0x02)
75#define PORTA0 0
76#define PORTA1 1
77#define PORTA2 2
78#define PORTA3 3
79#define PORTA4 4
80#define PORTA5 5
81#define PORTA6 6
82#define PORTA7 7
83
84#define PINB _SFR_IO8(0x03)
85#define PINB0 0
86#define PINB1 1
87#define PINB2 2
88#define PINB3 3
89#define PINB4 4
90#define PINB5 5
91#define PINB6 6
92#define PINB7 7
93
94#define DDRB _SFR_IO8(0x04)
95#define DDB0 0
96#define DDB1 1
97#define DDB2 2
98#define DDB3 3
99#define DDB4 4
100#define DDB5 5
101#define DDB6 6
102#define DDB7 7
103
104#define PORTB _SFR_IO8(0x05)
105#define PORTB0 0
106#define PORTB1 1
107#define PORTB2 2
108#define PORTB3 3
109#define PORTB4 4
110#define PORTB5 5
111#define PORTB6 6
112#define PORTB7 7
113
114#define PINC _SFR_IO8(0x06)
115#define PINC0 0
116#define PINC1 1
117#define PINC2 2
118#define PINC3 3
119#define PINC4 4
120#define PINC5 5
121#define PINC6 6
122#define PINC7 7
123
124#define DDRC _SFR_IO8(0x07)
125#define DDC0 0
126#define DDC1 1
127#define DDC2 2
128#define DDC3 3
129#define DDC4 4
130#define DDC5 5
131#define DDC6 6
132#define DDC7 7
133
134#define PORTC _SFR_IO8(0x08)
135#define PORTC0 0
136#define PORTC1 1
137#define PORTC2 2
138#define PORTC3 3
139#define PORTC4 4
140#define PORTC5 5
141#define PORTC6 6
142#define PORTC7 7
143
144#define PIND _SFR_IO8(0x09)
145#define PIND0 0
146#define PIND1 1
147#define PIND2 2
148#define PIND3 3
149#define PIND4 4
150#define PIND5 5
151#define PIND6 6
152#define PIND7 7
153
154#define DDRD _SFR_IO8(0x0A)
155#define DDD0 0
156#define DDD1 1
157#define DDD2 2
158#define DDD3 3
159#define DDD4 4
160#define DDD5 5
161#define DDD6 6
162#define DDD7 7
163
164#define PORTD _SFR_IO8(0x0B)
165#define PORTD0 0
166#define PORTD1 1
167#define PORTD2 2
168#define PORTD3 3
169#define PORTD4 4
170#define PORTD5 5
171#define PORTD6 6
172#define PORTD7 7
173
174#define PINE _SFR_IO8(0x0C)
175#define PINE0 0
176#define PINE1 1
177#define PINE2 2
178#define PINE3 3
179#define PINE4 4
180#define PINE5 5
181#define PINE6 6
182#define PINE7 7
183
184#define DDRE _SFR_IO8(0x0D)
185#define DDE0 0
186#define DDE1 1
187#define DDE2 2
188#define DDE3 3
189#define DDE4 4
190#define DDE5 5
191#define DDE6 6
192#define DDE7 7
193
194#define PORTE _SFR_IO8(0x0E)
195#define PORTE0 0
196#define PORTE1 1
197#define PORTE2 2
198#define PORTE3 3
199#define PORTE4 4
200#define PORTE5 5
201#define PORTE6 6
202#define PORTE7 7
203
204#define PINF _SFR_IO8(0x0F)
205#define PINF0 0
206#define PINF1 1
207#define PINF2 2
208#define PINF3 3
209#define PINF4 4
210#define PINF5 5
211#define PINF6 6
212#define PINF7 7
213
214#define DDRF _SFR_IO8(0x10)
215#define DDF0 0
216#define DDF1 1
217#define DDF2 2
218#define DDF3 3
219#define DDF4 4
220#define DDF5 5
221#define DDF6 6
222#define DDF7 7
223
224#define PORTF _SFR_IO8(0x11)
225#define PORTF0 0
226#define PORTF1 1
227#define PORTF2 2
228#define PORTF3 3
229#define PORTF4 4
230#define PORTF5 5
231#define PORTF6 6
232#define PORTF7 7
233
234#define TIFR0 _SFR_IO8(0x15)
235#define TOV0 0
236#define OCF0A 1
237#define OCF0B 2
238
239#define TIFR1 _SFR_IO8(0x16)
240#define TOV1 0
241#define OCF1A 1
242#define OCF1B 2
243#define OCF1C 3
244#define ICF1 5
245
246#define TIFR2 _SFR_IO8(0x17)
247#define TOV2 0
248#define OCF2A 1
249#define OCF2B 2
250
251#define TIFR3 _SFR_IO8(0x18)
252#define TOV3 0
253#define OCF3A 1
254#define OCF3B 2
255#define OCF3C 3
256#define ICF3 5
257
258#define PCIFR _SFR_IO8(0x1B)
259#define PCIF0 0
260
261#define EIFR _SFR_IO8(0x1C)
262#define INTF0 0
263#define INTF1 1
264#define INTF2 2
265#define INTF3 3
266#define INTF4 4
267#define INTF5 5
268#define INTF6 6
269#define INTF7 7
270
271#define EIMSK _SFR_IO8(0x1D)
272#define INT0 0
273#define INT1 1
274#define INT2 2
275#define INT3 3
276#define INT4 4
277#define INT5 5
278#define INT6 6
279#define INT7 7
280
281#define GPIOR0 _SFR_IO8(0x1E)
282#define GPIOR00 0
283#define GPIOR01 1
284#define GPIOR02 2
285#define GPIOR03 3
286#define GPIOR04 4
287#define GPIOR05 5
288#define GPIOR06 6
289#define GPIOR07 7
290
291#define EECR _SFR_IO8(0x1F)
292#define EERE 0
293#define EEPE 1
294#define EEMPE 2
295#define EERIE 3
296#define EEPM0 4
297#define EEPM1 5
298
299#define EEDR _SFR_IO8(0x20)
300#define EEDR0 0
301#define EEDR1 1
302#define EEDR2 2
303#define EEDR3 3
304#define EEDR4 4
305#define EEDR5 5
306#define EEDR6 6
307#define EEDR7 7
308
309#define EEAR _SFR_IO16(0x21)
310
311#define EEARL _SFR_IO8(0x21)
312#define EEAR0 0
313#define EEAR1 1
314#define EEAR2 2
315#define EEAR3 3
316#define EEAR4 4
317#define EEAR5 5
318#define EEAR6 6
319#define EEAR7 7
320
321#define EEARH _SFR_IO8(0x22)
322#define EEAR8 0
323#define EEAR9 1
324#define EEAR10 2
325#define EEAR11 3
326
327#define GTCCR _SFR_IO8(0x23)
328#define PSRSYNC 0
329#define PSRASY 1
330#define TSM 7
331
332#define TCCR0A _SFR_IO8(0x24)
333#define WGM00 0
334#define WGM01 1
335#define COM0B0 4
336#define COM0B1 5
337#define COM0A0 6
338#define COM0A1 7
339
340#define TCCR0B _SFR_IO8(0x25)
341#define CS00 0
342#define CS01 1
343#define CS02 2
344#define WGM02 3
345#define FOC0B 6
346#define FOC0A 7
347
348#define TCNT0 _SFR_IO8(0x26)
349#define TCNT0_0 0
350#define TCNT0_1 1
351#define TCNT0_2 2
352#define TCNT0_3 3
353#define TCNT0_4 4
354#define TCNT0_5 5
355#define TCNT0_6 6
356#define TCNT0_7 7
357
358#define OCR0A _SFR_IO8(0x27)
359#define OCR0A_0 0
360#define OCR0A_1 1
361#define OCR0A_2 2
362#define OCR0A_3 3
363#define OCR0A_4 4
364#define OCR0A_5 5
365#define OCR0A_6 6
366#define OCR0A_7 7
367
368#define OCR0B _SFR_IO8(0x28)
369#define OCR0B_0 0
370#define OCR0B_1 1
371#define OCR0B_2 2
372#define OCR0B_3 3
373#define OCR0B_4 4
374#define OCR0B_5 5
375#define OCR0B_6 6
376#define OCR0B_7 7
377
378#define PLLCSR _SFR_IO8(0x29)
379#define PLOCK 0
380#define PLLE 1
381#define PLLP0 2
382#define PLLP1 3
383#define PLLP2 4
384
385#define GPIOR1 _SFR_IO8(0x2A)
386#define GPIOR10 0
387#define GPIOR11 1
388#define GPIOR12 2
389#define GPIOR13 3
390#define GPIOR14 4
391#define GPIOR15 5
392#define GPIOR16 6
393#define GPIOR17 7
394
395#define GPIOR2 _SFR_IO8(0x2B)
396#define GPIOR20 0
397#define GPIOR21 1
398#define GPIOR22 2
399#define GPIOR23 3
400#define GPIOR24 4
401#define GPIOR25 5
402#define GPIOR26 6
403#define GPIOR27 7
404
405#define SPCR _SFR_IO8(0x2C)
406#define SPR0 0
407#define SPR1 1
408#define CPHA 2
409#define CPOL 3
410#define MSTR 4
411#define DORD 5
412#define SPE 6
413#define SPIE 7
414
415#define SPSR _SFR_IO8(0x2D)
416#define SPI2X 0
417#define WCOL 6
418#define SPIF 7
419
420#define SPDR _SFR_IO8(0x2E)
421#define SPDR0 0
422#define SPDR1 1
423#define SPDR2 2
424#define SPDR3 3
425#define SPDR4 4
426#define SPDR5 5
427#define SPDR6 6
428#define SPDR7 7
429
430#define ACSR _SFR_IO8(0x30)
431#define ACIS0 0
432#define ACIS1 1
433#define ACIC 2
434#define ACIE 3
435#define ACI 4
436#define ACO 5
437#define ACBG 6
438#define ACD 7
439
440#define OCDR _SFR_IO8(0x31)
441#define OCDR0 0
442#define OCDR1 1
443#define OCDR2 2
444#define OCDR3 3
445#define OCDR4 4
446#define OCDR5 5
447#define OCDR6 6
448#define OCDR7 7
449
450#define SMCR _SFR_IO8(0x33)
451#define SE 0
452#define SM0 1
453#define SM1 2
454#define SM2 3
455
456#define MCUSR _SFR_IO8(0x34)
457#define PORF 0
458#define EXTRF 1
459#define BORF 2
460#define WDRF 3
461#define JTRF 4
462
463#define MCUCR _SFR_IO8(0x35)
464#define IVCE 0
465#define IVSEL 1
466#define PUD 4
467#define JTD 7
468
469#define SPMCSR _SFR_IO8(0x37)
470#define SPMEN 0
471#define PGERS 1
472#define PGWRT 2
473#define BLBSET 3
474#define RWWSRE 4
475#define SIGRD 5
476#define RWWSB 6
477#define SPMIE 7
478
479#define WDTCSR _SFR_MEM8(0x60)
480#define WDP0 0
481#define WDP1 1
482#define WDP2 2
483#define WDE 3
484#define WDCE 4
485#define WDP3 5
486#define WDIE 6
487#define WDIF 7
488
489#define CLKPR _SFR_MEM8(0x61)
490#define CLKPS0 0
491#define CLKPS1 1
492#define CLKPS2 2
493#define CLKPS3 3
494#define CLKPCE 7
495
496#define PRR0 _SFR_MEM8(0x64)
497#define PRADC 0
498#define PRSPI 2
499#define PRTIM1 3
500#define PRTIM0 5
501#define PRTIM2 6
502#define PRTWI 7
503
504#define PRR1 _SFR_MEM8(0x65)
505#define PRUSART1 0
506#define PRTIM3 3
507#define PRUSB 7
508
509#define OSCCAL _SFR_MEM8(0x66)
510#define CAL0 0
511#define CAL1 1
512#define CAL2 2
513#define CAL3 3
514#define CAL4 4
515#define CAL5 5
516#define CAL6 6
517#define CAL7 7
518
519#define PCICR _SFR_MEM8(0x68)
520#define PCIE0 0
521
522#define EICRA _SFR_MEM8(0x69)
523#define ISC00 0
524#define ISC01 1
525#define ISC10 2
526#define ISC11 3
527#define ISC20 4
528#define ISC21 5
529#define ISC30 6
530#define ISC31 7
531
532#define EICRB _SFR_MEM8(0x6A)
533#define ISC40 0
534#define ISC41 1
535#define ISC50 2
536#define ISC51 3
537#define ISC60 4
538#define ISC61 5
539#define ISC70 6
540#define ISC71 7
541
542#define PCMSK0 _SFR_MEM8(0x6B)
543#define PCINT0 0
544#define PCINT1 1
545#define PCINT2 2
546#define PCINT3 3
547#define PCINT4 4
548#define PCINT5 5
549#define PCINT6 6
550#define PCINT7 7
551
552#define TIMSK0 _SFR_MEM8(0x6E)
553#define TOIE0 0
554#define OCIE0A 1
555#define OCIE0B 2
556
557#define TIMSK1 _SFR_MEM8(0x6F)
558#define TOIE1 0
559#define OCIE1A 1
560#define OCIE1B 2
561#define OCIE1C 3
562#define ICIE1 5
563
564#define TIMSK2 _SFR_MEM8(0x70)
565#define TOIE2 0
566#define OCIE2A 1
567#define OCIE2B 2
568
569#define TIMSK3 _SFR_MEM8(0x71)
570#define TOIE3 0
571#define OCIE3A 1
572#define OCIE3B 2
573#define OCIE3C 3
574#define ICIE3 5
575
576#define XMCRA _SFR_MEM8(0x74)
577#define SRW00 0
578#define SRW01 1
579#define SRW10 2
580#define SRW11 3
581#define SRL0 4
582#define SRL1 5
583#define SRL2 6
584#define SRE 7
585
586#define XMCRB _SFR_MEM8(0x75)
587#define XMM0 0
588#define XMM1 1
589#define XMM2 2
590#define XMBK 7
591
592#ifndef __ASSEMBLER__
593#define ADC _SFR_MEM16(0x78)
594#endif
595#define ADCW _SFR_MEM16(0x78)
596
597#define ADCL _SFR_MEM8(0x78)
598#define ADCL0 0
599#define ADCL1 1
600#define ADCL2 2
601#define ADCL3 3
602#define ADCL4 4
603#define ADCL5 5
604#define ADCL6 6
605#define ADCL7 7
606
607#define ADCH _SFR_MEM8(0x79)
608#define ADCH0 0
609#define ADCH1 1
610#define ADCH2 2
611#define ADCH3 3
612#define ADCH4 4
613#define ADCH5 5
614#define ADCH6 6
615#define ADCH7 7
616
617#define ADCSRA _SFR_MEM8(0x7A)
618#define ADPS0 0
619#define ADPS1 1
620#define ADPS2 2
621#define ADIE 3
622#define ADIF 4
623#define ADATE 5
624#define ADSC 6
625#define ADEN 7
626
627#define ADCSRB _SFR_MEM8(0x7B)
628#define ADTS0 0
629#define ADTS1 1
630#define ADTS2 2
631#define ACME 6
632#define ADHSM 7
633
634#define ADMUX _SFR_MEM8(0x7C)
635#define MUX0 0
636#define MUX1 1
637#define MUX2 2
638#define MUX3 3
639#define MUX4 4
640#define ADLAR 5
641#define REFS0 6
642#define REFS1 7
643
644#define DIDR0 _SFR_MEM8(0x7E)
645#define ADC0D 0
646#define ADC1D 1
647#define ADC2D 2
648#define ADC3D 3
649#define ADC4D 4
650#define ADC5D 5
651#define ADC6D 6
652#define ADC7D 7
653
654#define DIDR1 _SFR_MEM8(0x7F)
655#define AIN0D 0
656#define AIN1D 1
657
658#define TCCR1A _SFR_MEM8(0x80)
659#define WGM10 0
660#define WGM11 1
661#define COM1C0 2
662#define COM1C1 3
663#define COM1B0 4
664#define COM1B1 5
665#define COM1A0 6
666#define COM1A1 7
667
668#define TCCR1B _SFR_MEM8(0x81)
669#define CS10 0
670#define CS11 1
671#define CS12 2
672#define WGM12 3
673#define WGM13 4
674#define ICES1 6
675#define ICNC1 7
676
677#define TCCR1C _SFR_MEM8(0x82)
678#define FOC1C 5
679#define FOC1B 6
680#define FOC1A 7
681
682#define TCNT1 _SFR_MEM16(0x84)
683
684#define TCNT1L _SFR_MEM8(0x84)
685#define TCNT1L0 0
686#define TCNT1L1 1
687#define TCNT1L2 2
688#define TCNT1L3 3
689#define TCNT1L4 4
690#define TCNT1L5 5
691#define TCNT1L6 6
692#define TCNT1L7 7
693
694#define TCNT1H _SFR_MEM8(0x85)
695#define TCNT1H0 0
696#define TCNT1H1 1
697#define TCNT1H2 2
698#define TCNT1H3 3
699#define TCNT1H4 4
700#define TCNT1H5 5
701#define TCNT1H6 6
702#define TCNT1H7 7
703
704#define ICR1 _SFR_MEM16(0x86)
705
706#define ICR1L _SFR_MEM8(0x86)
707#define ICR1L0 0
708#define ICR1L1 1
709#define ICR1L2 2
710#define ICR1L3 3
711#define ICR1L4 4
712#define ICR1L5 5
713#define ICR1L6 6
714#define ICR1L7 7
715
716#define ICR1H _SFR_MEM8(0x87)
717#define ICR1H0 0
718#define ICR1H1 1
719#define ICR1H2 2
720#define ICR1H3 3
721#define ICR1H4 4
722#define ICR1H5 5
723#define ICR1H6 6
724#define ICR1H7 7
725
726#define OCR1A _SFR_MEM16(0x88)
727
728#define OCR1AL _SFR_MEM8(0x88)
729#define OCR1AL0 0
730#define OCR1AL1 1
731#define OCR1AL2 2
732#define OCR1AL3 3
733#define OCR1AL4 4
734#define OCR1AL5 5
735#define OCR1AL6 6
736#define OCR1AL7 7
737
738#define OCR1AH _SFR_MEM8(0x89)
739#define OCR1AH0 0
740#define OCR1AH1 1
741#define OCR1AH2 2
742#define OCR1AH3 3
743#define OCR1AH4 4
744#define OCR1AH5 5
745#define OCR1AH6 6
746#define OCR1AH7 7
747
748#define OCR1B _SFR_MEM16(0x8A)
749
750#define OCR1BL _SFR_MEM8(0x8A)
751#define OCR1BL0 0
752#define OCR1BL1 1
753#define OCR1BL2 2
754#define OCR1BL3 3
755#define OCR1BL4 4
756#define OCR1BL5 5
757#define OCR1BL6 6
758#define OCR1BL7 7
759
760#define OCR1BH _SFR_MEM8(0x8B)
761#define OCR1BH0 0
762#define OCR1BH1 1
763#define OCR1BH2 2
764#define OCR1BH3 3
765#define OCR1BH4 4
766#define OCR1BH5 5
767#define OCR1BH6 6
768#define OCR1BH7 7
769
770#define OCR1C _SFR_MEM16(0x8C)
771
772#define OCR1CL _SFR_MEM8(0x8C)
773#define OCR1CL0 0
774#define OCR1CL1 1
775#define OCR1CL2 2
776#define OCR1CL3 3
777#define OCR1CL4 4
778#define OCR1CL5 5
779#define OCR1CL6 6
780#define OCR1CL7 7
781
782#define OCR1CH _SFR_MEM8(0x8D)
783#define OCR1CH0 0
784#define OCR1CH1 1
785#define OCR1CH2 2
786#define OCR1CH3 3
787#define OCR1CH4 4
788#define OCR1CH5 5
789#define OCR1CH6 6
790#define OCR1CH7 7
791
792#define TCCR3A _SFR_MEM8(0x90)
793#define WGM30 0
794#define WGM31 1
795#define COM3C0 2
796#define COM3C1 3
797#define COM3B0 4
798#define COM3B1 5
799#define COM3A0 6
800#define COM3A1 7
801
802#define TCCR3B _SFR_MEM8(0x91)
803#define CS30 0
804#define CS31 1
805#define CS32 2
806#define WGM32 3
807#define WGM33 4
808#define ICES3 6
809#define ICNC3 7
810
811#define TCCR3C _SFR_MEM8(0x92)
812#define FOC3C 5
813#define FOC3B 6
814#define FOC3A 7
815
816#define TCNT3 _SFR_MEM16(0x94)
817
818#define TCNT3L _SFR_MEM8(0x94)
819#define TCNT3L0 0
820#define TCNT3L1 1
821#define TCNT3L2 2
822#define TCNT3L3 3
823#define TCNT3L4 4
824#define TCNT3L5 5
825#define TCNT3L6 6
826#define TCNT3L7 7
827
828#define TCNT3H _SFR_MEM8(0x95)
829#define TCNT3H0 0
830#define TCNT3H1 1
831#define TCNT3H2 2
832#define TCNT3H3 3
833#define TCNT3H4 4
834#define TCNT3H5 5
835#define TCNT3H6 6
836#define TCNT3H7 7
837
838#define ICR3 _SFR_MEM16(0x96)
839
840#define ICR3L _SFR_MEM8(0x96)
841#define ICR3L0 0
842#define ICR3L1 1
843#define ICR3L2 2
844#define ICR3L3 3
845#define ICR3L4 4
846#define ICR3L5 5
847#define ICR3L6 6
848#define ICR3L7 7
849
850#define ICR3H _SFR_MEM8(0x97)
851#define ICR3H0 0
852#define ICR3H1 1
853#define ICR3H2 2
854#define ICR3H3 3
855#define ICR3H4 4
856#define ICR3H5 5
857#define ICR3H6 6
858#define ICR3H7 7
859
860#define OCR3A _SFR_MEM16(0x98)
861
862#define OCR3AL _SFR_MEM8(0x98)
863#define OCR3AL0 0
864#define OCR3AL1 1
865#define OCR3AL2 2
866#define OCR3AL3 3
867#define OCR3AL4 4
868#define OCR3AL5 5
869#define OCR3AL6 6
870#define OCR3AL7 7
871
872#define OCR3AH _SFR_MEM8(0x99)
873#define OCR3AH0 0
874#define OCR3AH1 1
875#define OCR3AH2 2
876#define OCR3AH3 3
877#define OCR3AH4 4
878#define OCR3AH5 5
879#define OCR3AH6 6
880#define OCR3AH7 7
881
882#define OCR3B _SFR_MEM16(0x9A)
883
884#define OCR3BL _SFR_MEM8(0x9A)
885#define OCR3BL0 0
886#define OCR3BL1 1
887#define OCR3BL2 2
888#define OCR3BL3 3
889#define OCR3BL4 4
890#define OCR3BL5 5
891#define OCR3BL6 6
892#define OCR3BL7 7
893
894#define OCR3BH _SFR_MEM8(0x9B)
895#define OCR3BH0 0
896#define OCR3BH1 1
897#define OCR3BH2 2
898#define OCR3BH3 3
899#define OCR3BH4 4
900#define OCR3BH5 5
901#define OCR3BH6 6
902#define OCR3BH7 7
903
904#define OCR3C _SFR_MEM16(0x9C)
905
906#define OCR3CL _SFR_MEM8(0x9C)
907#define OCR3CL0 0
908#define OCR3CL1 1
909#define OCR3CL2 2
910#define OCR3CL3 3
911#define OCR3CL4 4
912#define OCR3CL5 5
913#define OCR3CL6 6
914#define OCR3CL7 7
915
916#define OCR3CH _SFR_MEM8(0x9D)
917#define OCR3CH0 0
918#define OCR3CH1 1
919#define OCR3CH2 2
920#define OCR3CH3 3
921#define OCR3CH4 4
922#define OCR3CH5 5
923#define OCR3CH6 6
924#define OCR3CH7 7
925
926#define TCCR2A _SFR_MEM8(0xB0)
927#define WGM20 0
928#define WGM21 1
929#define COM2B0 4
930#define COM2B1 5
931#define COM2A0 6
932#define COM2A1 7
933
934#define TCCR2B _SFR_MEM8(0xB1)
935#define CS20 0
936#define CS21 1
937#define CS22 2
938#define WGM22 3
939#define FOC2B 6
940#define FOC2A 7
941
942#define TCNT2 _SFR_MEM8(0xB2)
943#define TCNT2_0 0
944#define TCNT2_1 1
945#define TCNT2_2 2
946#define TCNT2_3 3
947#define TCNT2_4 4
948#define TCNT2_5 5
949#define TCNT2_6 6
950#define TCNT2_7 7
951
952#define OCR2A _SFR_MEM8(0xB3)
953#define OCR2A_0 0
954#define OCR2A_1 1
955#define OCR2A_2 2
956#define OCR2A_3 3
957#define OCR2A_4 4
958#define OCR2A_5 5
959#define OCR2A_6 6
960#define OCR2A_7 7
961
962#define OCR2B _SFR_MEM8(0xB4)
963#define OCR2B_0 0
964#define OCR2B_1 1
965#define OCR2B_2 2
966#define OCR2B_3 3
967#define OCR2B_4 4
968#define OCR2B_5 5
969#define OCR2B_6 6
970#define OCR2B_7 7
971
972#define ASSR _SFR_MEM8(0xB6)
973#define TCR2BUB 0
974#define TCR2AUB 1
975#define OCR2BUB 2
976#define OCR2AUB 3
977#define TCN2UB 4
978#define AS2 5
979#define EXCLK 6
980
981#define TWBR _SFR_MEM8(0xB8)
982#define TWBR0 0
983#define TWBR1 1
984#define TWBR2 2
985#define TWBR3 3
986#define TWBR4 4
987#define TWBR5 5
988#define TWBR6 6
989#define TWBR7 7
990
991#define TWSR _SFR_MEM8(0xB9)
992#define TWPS0 0
993#define TWPS1 1
994#define TWS3 3
995#define TWS4 4
996#define TWS5 5
997#define TWS6 6
998#define TWS7 7
999
1000#define TWAR _SFR_MEM8(0xBA)
1001#define TWGCE 0
1002#define TWA0 1
1003#define TWA1 2
1004#define TWA2 3
1005#define TWA3 4
1006#define TWA4 5
1007#define TWA5 6
1008#define TWA6 7
1009
1010#define TWDR _SFR_MEM8(0xBB)
1011#define TWD0 0
1012#define TWD1 1
1013#define TWD2 2
1014#define TWD3 3
1015#define TWD4 4
1016#define TWD5 5
1017#define TWD6 6
1018#define TWD7 7
1019
1020#define TWCR _SFR_MEM8(0xBC)
1021#define TWIE 0
1022#define TWEN 2
1023#define TWWC 3
1024#define TWSTO 4
1025#define TWSTA 5
1026#define TWEA 6
1027#define TWINT 7
1028
1029#define TWAMR _SFR_MEM8(0xBD)
1030#define TWAM0 1
1031#define TWAM1 2
1032#define TWAM2 3
1033#define TWAM3 4
1034#define TWAM4 5
1035#define TWAM5 6
1036#define TWAM6 7
1037
1038#define UCSR1A _SFR_MEM8(0xC8)
1039#define MPCM1 0
1040#define U2X1 1
1041#define UPE1 2
1042#define DOR1 3
1043#define FE1 4
1044#define UDRE1 5
1045#define TXC1 6
1046#define RXC1 7
1047
1048#define UCSR1B _SFR_MEM8(0xC9)
1049#define TXB81 0
1050#define RXB81 1
1051#define UCSZ12 2
1052#define TXEN1 3
1053#define RXEN1 4
1054#define UDRIE1 5
1055#define TXCIE1 6
1056#define RXCIE1 7
1057
1058#define UCSR1C _SFR_MEM8(0xCA)
1059#define UCPOL1 0
1060#define UCSZ10 1
1061#define UCSZ11 2
1062#define USBS1 3
1063#define UPM10 4
1064#define UPM11 5
1065#define UMSEL10 6
1066#define UMSEL11 7
1067
1068#define UBRR1 _SFR_MEM16(0xCC)
1069
1070#define UBRR1L _SFR_MEM8(0xCC)
1071#define UBRR_0 0
1072#define UBRR_1 1
1073#define UBRR_2 2
1074#define UBRR_3 3
1075#define UBRR_4 4
1076#define UBRR_5 5
1077#define UBRR_6 6
1078#define UBRR_7 7
1079
1080#define UBRR1H _SFR_MEM8(0xCD)
1081#define UBRR_8 0
1082#define UBRR_9 1
1083#define UBRR_10 2
1084#define UBRR_11 3
1085
1086#define UDR1 _SFR_MEM8(0xCE)
1087#define UDR1_0 0
1088#define UDR1_1 1
1089#define UDR1_2 2
1090#define UDR1_3 3
1091#define UDR1_4 4
1092#define UDR1_5 5
1093#define UDR1_6 6
1094#define UDR1_7 7
1095
1096#define UHWCON _SFR_MEM8(0xD7)
1097#define UVREGE 0
1098#define UVCONE 4
1099#define UIDE 6
1100#define UIMOD 7
1101
1102#define USBCON _SFR_MEM8(0xD8)
1103#define VBUSTE 0
1104#define IDTE 1
1105#define OTGPADE 4
1106#define FRZCLK 5
1107#define HOST 6
1108#define USBE 7
1109
1110#define USBSTA _SFR_MEM8(0xD9)
1111#define VBUS 0
1112#define ID 1
1113#define SPEED 3
1114
1115#define USBINT _SFR_MEM8(0xDA)
1116#define VBUSTI 0
1117#define IDTI 1
1118
1119#define UDCON _SFR_MEM8(0xE0)
1120#define DETACH 0
1121#define RMWKUP 1
1122#define LSM 2
1123
1124#define UDINT _SFR_MEM8(0xE1)
1125#define SUSPI 0
1126#define SOFI 2
1127#define EORSTI 3
1128#define WAKEUPI 4
1129#define EORSMI 5
1130#define UPRSMI 6
1131
1132#define UDIEN _SFR_MEM8(0xE2)
1133#define SUSPE 0
1134#define SOFE 2
1135#define EORSTE 3
1136#define WAKEUPE 4
1137#define EORSME 5
1138#define UPRSME 6
1139
1140#define UDADDR _SFR_MEM8(0xE3)
1141#define UADD0 0
1142#define UADD1 1
1143#define UADD2 2
1144#define UADD3 3
1145#define UADD4 4
1146#define UADD5 5
1147#define UADD6 6
1148#define ADDEN 7
1149
1150#define UDFNUM _SFR_MEM16(0xE4)
1151
1152#define UDFNUML _SFR_MEM8(0xE4)
1153#define UDFNUML_0 0
1154#define UDFNUML_1 1
1155#define UDFNUML_2 2
1156#define UDFNUML_3 3
1157#define UDFNUML_4 4
1158#define UDFNUML_5 5
1159#define UDFNUML_6 6
1160#define UDFNUML_7 7
1161
1162#define UDFNUMH _SFR_MEM8(0xE5)
1163#define UDFNUMH_0 0
1164#define UDFNUMH_1 1
1165#define UDFNUMH_2 2
1166
1167#define UDMFN _SFR_MEM8(0xE6)
1168#define FNCERR 4
1169
1170#define UEINTX _SFR_MEM8(0xE8)
1171#define TXINI 0
1172#define STALLEDI 1
1173#define RXOUTI 2
1174#define RXSTPI 3
1175#define NAKOUTI 4
1176#define RWAL 5
1177#define NAKINI 6
1178#define FIFOCON 7
1179
1180#define UENUM _SFR_MEM8(0xE9)
1181#define UENUM_0 0
1182#define UENUM_1 1
1183#define UENUM_2 2
1184
1185#define UERST _SFR_MEM8(0xEA)
1186#define EPRST0 0
1187#define EPRST1 1
1188#define EPRST2 2
1189#define EPRST3 3
1190#define EPRST4 4
1191#define EPRST5 5
1192#define EPRST6 6
1193
1194#define UECONX _SFR_MEM8(0xEB)
1195#define EPEN 0
1196#define RSTDT 3
1197#define STALLRQC 4
1198#define STALLRQ 5
1199
1200#define UECFG0X _SFR_MEM8(0xEC)
1201#define EPDIR 0
1202#define EPTYPE0 6
1203#define EPTYPE1 7
1204
1205#define UECFG1X _SFR_MEM8(0xED)
1206#define ALLOC 1
1207#define EPBK0 2
1208#define EPBK1 3
1209#define EPSIZE0 4
1210#define EPSIZE1 5
1211#define EPSIZE2 6
1212
1213#define UESTA0X _SFR_MEM8(0xEE)
1214#define NBUSYBK0 0
1215#define NBUSYBK1 1
1216#define DTSEQ0 2
1217#define DTSEQ1 3
1218#define UNDERFI 5
1219#define OVERFI 6
1220#define CFGOK 7
1221
1222#define UESTA1X _SFR_MEM8(0xEF)
1223#define CURRBK0 0
1224#define CURRBK1 1
1225#define CTRLDIR 2
1226
1227#define UEIENX _SFR_MEM8(0xF0)
1228#define TXINE 0
1229#define STALLEDE 1
1230#define RXOUTE 2
1231#define RXSTPE 3
1232#define NAKOUTE 4
1233#define NAKINE 6
1234#define FLERRE 7
1235
1236#define UEDATX _SFR_MEM8(0xF1)
1237#define UEDATX_0 0
1238#define UEDATX_1 1
1239#define UEDATX_2 2
1240#define UEDATX_3 3
1241#define UEDATX_4 4
1242#define UEDATX_5 5
1243#define UEDATX_6 6
1244#define UEDATX_7 7
1245
1246#define UEBCLX _SFR_MEM8(0xF2)
1247#define UEBCLX_0 0
1248#define UEBCLX_1 1
1249#define UEBCLX_2 2
1250#define UEBCLX_3 3
1251#define UEBCLX_4 4
1252#define UEBCLX_5 5
1253#define UEBCLX_6 6
1254#define UEBCLX_7 7
1255
1256#define UEBCHX _SFR_MEM8(0xF3)
1257#define UEBCHX_0 0
1258#define UEBCHX_1 1
1259#define UEBCHX_2 2
1260
1261#define UEINT _SFR_MEM8(0xF4)
1262#define EPINT0 0
1263#define EPINT1 1
1264#define EPINT2 2
1265#define EPINT3 3
1266#define EPINT4 4
1267#define EPINT5 5
1268#define EPINT6 6
1269
1270
1271/* Interrupt vectors */
1272/* Vector 0 is the reset vector */
1273#define INT0_vect_num  1
1274#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
1275#define INT1_vect_num  2
1276#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
1277#define INT2_vect_num  3
1278#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
1279#define INT3_vect_num  4
1280#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
1281#define INT4_vect_num  5
1282#define INT4_vect      _VECTOR(5)  /* External Interrupt Request 4 */
1283#define INT5_vect_num  6
1284#define INT5_vect      _VECTOR(6)  /* External Interrupt Request 5 */
1285#define INT6_vect_num  7
1286#define INT6_vect      _VECTOR(7)  /* External Interrupt Request 6 */
1287#define INT7_vect_num  8
1288#define INT7_vect      _VECTOR(8)  /* External Interrupt Request 7 */
1289#define PCINT0_vect_num  9
1290#define PCINT0_vect      _VECTOR(9)  /* Pin Change Interrupt Request 0 */
1291#define USB_GEN_vect_num  10
1292#define USB_GEN_vect      _VECTOR(10)  /* USB General Interrupt Request */
1293#define USB_COM_vect_num  11
1294#define USB_COM_vect      _VECTOR(11)  /* USB Endpoint/Pipe Interrupt Communication Request */
1295#define WDT_vect_num  12
1296#define WDT_vect      _VECTOR(12)  /* Watchdog Time-out Interrupt */
1297#define TIMER2_COMPA_vect_num  13
1298#define TIMER2_COMPA_vect      _VECTOR(13)  /* Timer/Counter2 Compare Match A */
1299#define TIMER2_COMPB_vect_num  14
1300#define TIMER2_COMPB_vect      _VECTOR(14)  /* Timer/Counter2 Compare Match B */
1301#define TIMER2_OVF_vect_num  15
1302#define TIMER2_OVF_vect      _VECTOR(15)  /* Timer/Counter2 Overflow */
1303#define TIMER1_CAPT_vect_num  16
1304#define TIMER1_CAPT_vect      _VECTOR(16)  /* Timer/Counter1 Capture Event */
1305#define TIMER1_COMPA_vect_num  17
1306#define TIMER1_COMPA_vect      _VECTOR(17)  /* Timer/Counter1 Compare Match A */
1307#define TIMER1_COMPB_vect_num  18
1308#define TIMER1_COMPB_vect      _VECTOR(18)  /* Timer/Counter1 Compare Match B */
1309#define TIMER1_COMPC_vect_num  19
1310#define TIMER1_COMPC_vect      _VECTOR(19)  /* Timer/Counter1 Compare Match C */
1311#define TIMER1_OVF_vect_num  20
1312#define TIMER1_OVF_vect      _VECTOR(20)  /* Timer/Counter1 Overflow */
1313#define TIMER0_COMPA_vect_num  21
1314#define TIMER0_COMPA_vect      _VECTOR(21)  /* Timer/Counter0 Compare Match A */
1315#define TIMER0_COMPB_vect_num  22
1316#define TIMER0_COMPB_vect      _VECTOR(22)  /* Timer/Counter0 Compare Match B */
1317#define TIMER0_OVF_vect_num  23
1318#define TIMER0_OVF_vect      _VECTOR(23)  /* Timer/Counter0 Overflow */
1319#define SPI_STC_vect_num  24
1320#define SPI_STC_vect      _VECTOR(24)  /* SPI Serial Transfer Complete */
1321#define USART1_RX_vect_num  25
1322#define USART1_RX_vect      _VECTOR(25)  /* USART1, Rx Complete */
1323#define USART1_UDRE_vect_num  26
1324#define USART1_UDRE_vect      _VECTOR(26)  /* USART1 Data register Empty */
1325#define USART1_TX_vect_num  27
1326#define USART1_TX_vect      _VECTOR(27)  /* USART1, Tx Complete */
1327#define ANALOG_COMP_vect_num  28
1328#define ANALOG_COMP_vect      _VECTOR(28)  /* Analog Comparator */
1329#define ADC_vect_num  29
1330#define ADC_vect      _VECTOR(29)  /* ADC Conversion Complete */
1331#define EE_READY_vect_num  30
1332#define EE_READY_vect      _VECTOR(30)  /* EEPROM Ready */
1333#define TIMER3_CAPT_vect_num  31
1334#define TIMER3_CAPT_vect      _VECTOR(31)  /* Timer/Counter3 Capture Event */
1335#define TIMER3_COMPA_vect_num  32
1336#define TIMER3_COMPA_vect      _VECTOR(32)  /* Timer/Counter3 Compare Match A */
1337#define TIMER3_COMPB_vect_num  33
1338#define TIMER3_COMPB_vect      _VECTOR(33)  /* Timer/Counter3 Compare Match B */
1339#define TIMER3_COMPC_vect_num  34
1340#define TIMER3_COMPC_vect      _VECTOR(34)  /* Timer/Counter3 Compare Match C */
1341#define TIMER3_OVF_vect_num  35
1342#define TIMER3_OVF_vect      _VECTOR(35)  /* Timer/Counter3 Overflow */
1343#define TWI_vect_num  36
1344#define TWI_vect      _VECTOR(36)  /* 2-wire Serial Interface         */
1345#define SPM_READY_vect_num  37
1346#define SPM_READY_vect      _VECTOR(37)  /* Store Program Memory Read */
1347
1348#define _VECTOR_SIZE 4 /* Size of individual vector. */
1349#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
1350
1351
1352/* Constants */
1353#define SPM_PAGESIZE (128)
1354#define RAMSTART     (0x100)
1355#define RAMSIZE      (2560)
1356#define RAMEND       (RAMSTART + RAMSIZE - 1)
1357#define XRAMSTART    (0x2200)
1358#define XRAMSIZE     (65536)
1359#define XRAMEND      (XRAMSIZE - 1)
1360#define E2END        (0x3FF)
1361#define E2PAGESIZE   (4)
1362#define FLASHEND     (0x7FFF)
1363
1364
1365/* Fuses */
1366#define FUSE_MEMORY_SIZE 3
1367
1368/* Low Fuse Byte */
1369#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
1370#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
1371#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
1372#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
1373#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
1374#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
1375#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
1376#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
1377#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
1378
1379/* High Fuse Byte */
1380#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
1381#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
1382#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
1383#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1384#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
1385#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1386#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
1387#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
1388#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1389
1390/* Extended Fuse Byte */
1391#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
1392#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
1393#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
1394#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
1395#define EFUSE_DEFAULT (0xFF)
1396
1397
1398/* Lock Bits */
1399#define __LOCK_BITS_EXIST
1400#define __BOOT_LOCK_BITS_0_EXIST
1401#define __BOOT_LOCK_BITS_1_EXIST
1402
1403
1404/* Signature */
1405#define SIGNATURE_0 0x1E
1406#define SIGNATURE_1 0x95
1407#define SIGNATURE_2 0x88
1408
1409
1410#endif /* _AVR_ATmega32U6_H_ */
1411
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