source: rtems/cpukit/score/cpu/avr/avr/iom32u4.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 28.4 KB
Line 
1/* Copyright (c) 2008 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE.
30*/
31
32/* $Id$ */
33
34/* avr/iom32u4.h - definitions for ATmega32U4. */
35
36/* This file should only be included from <avr/io.h>, never directly. */
37
38#ifndef _AVR_IO_H_
39#  error "Include <avr/io.h> instead of this file."
40#endif
41
42#ifndef _AVR_IOXXX_H_
43#  define _AVR_IOXXX_H_ "iom32u4.h"
44#else
45#  error "Attempt to include more than one <avr/ioXXX.h> file."
46#endif
47
48
49#ifndef _AVR_IOM32U4_H_
50#define _AVR_IOM32U4_H_ 1
51
52
53/* Registers and associated bit numbers */
54
55#define PINB _SFR_IO8(0x03)
56#define PINB0 0
57#define PINB1 1
58#define PINB2 2
59#define PINB3 3
60#define PINB4 4
61#define PINB5 5
62#define PINB6 6
63#define PINB7 7
64
65#define DDRB _SFR_IO8(0x04)
66#define DDB0 0
67#define DDB1 1
68#define DDB2 2
69#define DDB3 3
70#define DDB4 4
71#define DDB5 5
72#define DDB6 6
73#define DDB7 7
74
75#define PORTB _SFR_IO8(0x05)
76#define PORTB0 0
77#define PORTB1 1
78#define PORTB2 2
79#define PORTB3 3
80#define PORTB4 4
81#define PORTB5 5
82#define PORTB6 6
83#define PORTB7 7
84
85#define PINC _SFR_IO8(0x06)
86#define PINC6 6
87#define PINC7 7
88
89#define DDRC _SFR_IO8(0x07)
90#define DDC6 6
91#define DDC7 7
92
93#define PORTC _SFR_IO8(0x08)
94#define PORTC6 6
95#define PORTC7 7
96
97#define PIND _SFR_IO8(0x09)
98#define PIND0 0
99#define PIND1 1
100#define PIND2 2
101#define PIND3 3
102#define PIND4 4
103#define PIND5 5
104#define PIND6 6
105#define PIND7 7
106
107#define DDRD _SFR_IO8(0x0A)
108#define DDD0 0
109#define DDD1 1
110#define DDD2 2
111#define DDD3 3
112#define DDD4 4
113#define DDD5 5
114#define DDD6 6
115#define DDD7 7
116
117#define PORTD _SFR_IO8(0x0B)
118#define PORTD0 0
119#define PORTD1 1
120#define PORTD2 2
121#define PORTD3 3
122#define PORTD4 4
123#define PORTD5 5
124#define PORTD6 6
125#define PORTD7 7
126
127#define PINE _SFR_IO8(0x0C)
128#define PINE2 2
129#define PINE6 6
130
131#define DDRE _SFR_IO8(0x0D)
132#define DDE2 2
133#define DDE6 6
134
135#define PORTE _SFR_IO8(0x0E)
136#define PORTE2 2
137#define PORTE6 6
138
139#define PINF _SFR_IO8(0x0F)
140#define PINF0 0
141#define PINF1 1
142#define PINF4 4
143#define PINF5 5
144#define PINF6 6
145#define PINF7 7
146
147#define DDRF _SFR_IO8(0x10)
148#define DDF0 0
149#define DDF1 1
150#define DDF4 4
151#define DDF5 5
152#define DDF6 6
153#define DDF7 7
154
155#define PORTF _SFR_IO8(0x11)
156#define PORTF0 0
157#define PORTF1 1
158#define PORTF4 4
159#define PORTF5 5
160#define PORTF6 6
161#define PORTF7 7
162
163#define TIFR0 _SFR_IO8(0x15)
164#define TOV0 0
165#define OCF0A 1
166#define OCF0B 2
167
168#define TIFR1 _SFR_IO8(0x16)
169#define TOV1 0
170#define OCF1A 1
171#define OCF1B 2
172#define OCF1C 3
173#define ICF1 5
174
175#define TIFR2 _SFR_IO8(0x17)
176#define TOV2 0
177#define OCF2A 1
178#define OCF2B 2
179
180#define TIFR3 _SFR_IO8(0x18)
181#define TOV3 0
182#define OCF3A 1
183#define OCF3B 2
184#define OCF3C 3
185#define ICF3 5
186
187#define TIFR4 _SFR_IO8(0x19)
188#define TOV4 2
189#define OCF4B 5
190#define OCF4A 6
191#define OCF4D 7
192
193#define TIFR5 _SFR_IO8(0x1A)
194
195#define PCIFR _SFR_IO8(0x1B)
196#define PCIF0 0
197
198#define EIFR _SFR_IO8(0x1C)
199#define INTF0 0
200#define INTF1 1
201#define INTF2 2
202#define INTF3 3
203#define INTF4 4
204#define INTF5 5
205#define INTF6 6
206#define INTF7 7
207
208#define EIMSK _SFR_IO8(0x1D)
209#define INT0 0
210#define INT1 1
211#define INT2 2
212#define INT3 3
213#define INT4 4
214#define INT5 5
215#define INT6 6
216#define INT7 7
217
218#define GPIOR0 _SFR_IO8(0x1E)
219#define GPIOR00 0
220#define GPIOR01 1
221#define GPIOR02 2
222#define GPIOR03 3
223#define GPIOR04 4
224#define GPIOR05 5
225#define GPIOR06 6
226#define GPIOR07 7
227
228#define EECR _SFR_IO8(0x1F)
229#define EERE 0
230#define EEPE 1
231#define EEMPE 2
232#define EERIE 3
233#define EEPM0 4
234#define EEPM1 5
235
236#define EEDR _SFR_IO8(0x20)
237#define EEDR0 0
238#define EEDR1 1
239#define EEDR2 2
240#define EEDR3 3
241#define EEDR4 4
242#define EEDR5 5
243#define EEDR6 6
244#define EEDR7 7
245
246#define EEAR _SFR_IO16(0x21)
247
248#define EEARL _SFR_IO8(0x21)
249#define EEAR0 0
250#define EEAR1 1
251#define EEAR2 2
252#define EEAR3 3
253#define EEAR4 4
254#define EEAR5 5
255#define EEAR6 6
256#define EEAR7 7
257
258#define EEARH _SFR_IO8(0x22)
259#define EEAR8 0
260#define EEAR9 1
261#define EEAR10 2
262#define EEAR11 3
263
264#define GTCCR _SFR_IO8(0x23)
265#define PSRSYNC 0
266#define PSRASY 1
267#define TSM 7
268
269#define TCCR0A _SFR_IO8(0x24)
270#define WGM00 0
271#define WGM01 1
272#define COM0B0 4
273#define COM0B1 5
274#define COM0A0 6
275#define COM0A1 7
276
277#define TCCR0B _SFR_IO8(0x25)
278#define CS00 0
279#define CS01 1
280#define CS02 2
281#define WGM02 3
282#define FOC0B 6
283#define FOC0A 7
284
285#define TCNT0 _SFR_IO8(0x26)
286#define TCNT0_0 0
287#define TCNT0_1 1
288#define TCNT0_2 2
289#define TCNT0_3 3
290#define TCNT0_4 4
291#define TCNT0_5 5
292#define TCNT0_6 6
293#define TCNT0_7 7
294
295#define OCR0A _SFR_IO8(0x27)
296#define OCR0A_0 0
297#define OCR0A_1 1
298#define OCR0A_2 2
299#define OCR0A_3 3
300#define OCR0A_4 4
301#define OCR0A_5 5
302#define OCR0A_6 6
303#define OCR0A_7 7
304
305#define OCR0B _SFR_IO8(0x28)
306#define OCR0B_0 0
307#define OCR0B_1 1
308#define OCR0B_2 2
309#define OCR0B_3 3
310#define OCR0B_4 4
311#define OCR0B_5 5
312#define OCR0B_6 6
313#define OCR0B_7 7
314
315#define PLLCSR _SFR_IO8(0x29)
316#define PLOCK 0
317#define PLLE 1
318#define PINDIV 4
319
320#define GPIOR1 _SFR_IO8(0x2A)
321#define GPIOR10 0
322#define GPIOR11 1
323#define GPIOR12 2
324#define GPIOR13 3
325#define GPIOR14 4
326#define GPIOR15 5
327#define GPIOR16 6
328#define GPIOR17 7
329
330#define GPIOR2 _SFR_IO8(0x2B)
331#define GPIOR20 0
332#define GPIOR21 1
333#define GPIOR22 2
334#define GPIOR23 3
335#define GPIOR24 4
336#define GPIOR25 5
337#define GPIOR26 6
338#define GPIOR27 7
339
340#define SPCR _SFR_IO8(0x2C)
341#define SPR0 0
342#define SPR1 1
343#define CPHA 2
344#define CPOL 3
345#define MSTR 4
346#define DORD 5
347#define SPE 6
348#define SPIE 7
349
350#define SPSR _SFR_IO8(0x2D)
351#define SPI2X 0
352#define WCOL 6
353#define SPIF 7
354
355#define SPDR _SFR_IO8(0x2E)
356#define SPDR0 0
357#define SPDR1 1
358#define SPDR2 2
359#define SPDR3 3
360#define SPDR4 4
361#define SPDR5 5
362#define SPDR6 6
363#define SPDR7 7
364
365#define ACSR _SFR_IO8(0x30)
366#define ACIS0 0
367#define ACIS1 1
368#define ACIC 2
369#define ACIE 3
370#define ACI 4
371#define ACO 5
372#define ACBG 6
373#define ACD 7
374
375#define OCDR _SFR_IO8(0x31)
376#define OCDR0 0
377#define OCDR1 1
378#define OCDR2 2
379#define OCDR3 3
380#define OCDR4 4
381#define OCDR5 5
382#define OCDR6 6
383#define OCDR7 7
384
385#define PLLFRQ _SFR_IO8(0x32)
386#define PDIV0 0
387#define PDIV1 1
388#define PDIV2 2
389#define PDIV3 3
390#define PLLTM0 4
391#define PLLTM1 5
392#define PLLUSB 6
393#define PINMUX 7
394
395#define SMCR _SFR_IO8(0x33)
396#define SE 0
397#define SM0 1
398#define SM1 2
399#define SM2 3
400
401#define MCUSR _SFR_IO8(0x34)
402#define PORF 0
403#define EXTRF 1
404#define BORF 2
405#define WDRF 3
406#define JTRF 4
407
408#define MCUCR _SFR_IO8(0x35)
409#define IVCE 0
410#define IVSEL 1
411#define PUD 4
412#define JTD 7
413
414#define SPMCSR _SFR_IO8(0x37)
415#define SPMEN 0
416#define PGERS 1
417#define PGWRT 2
418#define BLBSET 3
419#define RWWSRE 4
420#define SIGRD 5
421#define RWWSB 6
422#define SPMIE 7
423
424#define RAMPZ _SFR_IO8(0x3B)
425#define RAMPZ0 0
426
427#define EIND _SFR_IO8(0x3C)
428#define EIND0 0
429
430#define WDTCSR _SFR_MEM8(0x60)
431#define WDP0 0
432#define WDP1 1
433#define WDP2 2
434#define WDE 3
435#define WDCE 4
436#define WDP3 5
437#define WDIE 6
438#define WDIF 7
439
440#define CLKPR _SFR_MEM8(0x61)
441#define CLKPS0 0
442#define CLKPS1 1
443#define CLKPS2 2
444#define CLKPS3 3
445#define CLKPCE 7
446
447#define PRR0 _SFR_MEM8(0x64)
448#define PRADC 0
449#define PRUSART0 1
450#define PRSPI 2
451#define PRTIM1 3
452#define PRTIM0 5
453#define PRTIM2 6
454#define PRTWI 7
455
456#define PRR1 _SFR_MEM8(0x65)
457#define PRUSART1 0
458#define PRTIM3 3
459#define PRUSB 7
460
461#define OSCCAL _SFR_MEM8(0x66)
462#define CAL0 0
463#define CAL1 1
464#define CAL2 2
465#define CAL3 3
466#define CAL4 4
467#define CAL5 5
468#define CAL6 6
469#define CAL7 7
470
471#define RCCTRL _SFR_MEM8(0x67)
472#define RCFREQ 0
473
474#define PCICR _SFR_MEM8(0x68)
475#define PCIE0 0
476
477#define EICRA _SFR_MEM8(0x69)
478#define ISC00 0
479#define ISC01 1
480#define ISC10 2
481#define ISC11 3
482#define ISC20 4
483#define ISC21 5
484#define ISC30 6
485#define ISC31 7
486
487#define EICRB _SFR_MEM8(0x6A)
488#define ISC40 0
489#define ISC41 1
490#define ISC50 2
491#define ISC51 3
492#define ISC60 4
493#define ISC61 5
494#define ISC70 6
495#define ISC71 7
496
497#define PCMSK0 _SFR_MEM8(0x6B)
498#define PCINT0 0
499#define PCINT1 1
500#define PCINT2 2
501#define PCINT3 3
502#define PCINT4 4
503#define PCINT5 5
504#define PCINT6 6
505#define PCINT7 7
506
507#define PCMSK1 _SFR_MEM8(0x6C)
508
509#define PCMSK2 _SFR_MEM8(0x6D)
510
511#define TIMSK0 _SFR_MEM8(0x6E)
512#define TOIE0 0
513#define OCIE0A 1
514#define OCIE0B 2
515
516#define TIMSK1 _SFR_MEM8(0x6F)
517#define TOIE1 0
518#define OCIE1A 1
519#define OCIE1B 2
520#define OCIE1C 3
521#define ICIE1 5
522
523#define TIMSK2 _SFR_MEM8(0x70)
524#define TOIE2 0
525#define OCIE2A 1
526#define OCIE2B 2
527
528#define TIMSK3 _SFR_MEM8(0x71)
529#define TOIE3 0
530#define OCIE3A 1
531#define OCIE3B 2
532#define OCIE3C 3
533#define ICIE3 5
534
535#define TIMSK4 _SFR_MEM8(0x72)
536#define TOIE4 2
537#define OCIE4B 5
538#define OCIE4A 6
539#define OCIE4D 7
540
541#define TIMSK5 _SFR_MEM8(0x73)
542
543#define ADC _SFR_MEM16(0x78)
544
545#define ADCL _SFR_MEM8(0x78)
546#define ADCL0 0
547#define ADCL1 1
548#define ADCL2 2
549#define ADCL3 3
550#define ADCL4 4
551#define ADCL5 5
552#define ADCL6 6
553#define ADCL7 7
554
555#define ADCH _SFR_MEM8(0x79)
556#define ADCH0 0
557#define ADCH1 1
558#define ADCH2 2
559#define ADCH3 3
560#define ADCH4 4
561#define ADCH5 5
562#define ADCH6 6
563#define ADCH7 7
564
565#define ADCSRA _SFR_MEM8(0x7A)
566#define ADPS0 0
567#define ADPS1 1
568#define ADPS2 2
569#define ADIE 3
570#define ADIF 4
571#define ADATE 5
572#define ADSC 6
573#define ADEN 7
574
575#define ADCSRB _SFR_MEM8(0x7B)
576#define ADTS0 0
577#define ADTS1 1
578#define ADTS2 2
579#define ADTS3 4
580#define MUX5 5
581#define ACME 6
582#define ADHSM 7
583
584#define ADMUX _SFR_MEM8(0x7C)
585#define MUX0 0
586#define MUX1 1
587#define MUX2 2
588#define MUX3 3
589#define MUX4 4
590#define ADLAR 5
591#define REFS0 6
592#define REFS1 7
593
594#define DIDR2 _SFR_MEM8(0x7D)
595#define ADC8D 0
596#define ADC9D 1
597#define ADC10D 2
598#define ADC11D 3
599#define ADC12D 4
600#define ADC13D 5
601
602#define DIDR0 _SFR_MEM8(0x7E)
603#define ADC0D 0
604#define ADC1D 1
605#define ADC2D 2
606#define ADC3D 3
607#define ADC4D 4
608#define ADC5D 5
609#define ADC6D 6
610#define ADC7D 7
611
612#define DIDR1 _SFR_MEM8(0x7F)
613#define AIN0D 0
614#define AIN1D 1
615
616#define TCCR1A _SFR_MEM8(0x80)
617#define WGM10 0
618#define WGM11 1
619#define COM1C0 2
620#define COM1C1 3
621#define COM1B0 4
622#define COM1B1 5
623#define COM1A0 6
624#define COM1A1 7
625
626#define TCCR1B _SFR_MEM8(0x81)
627#define CS10 0
628#define CS11 1
629#define CS12 2
630#define WGM12 3
631#define WGM13 4
632#define ICES1 6
633#define ICNC1 7
634
635#define TCCR1C _SFR_MEM8(0x82)
636#define FOC1C 5
637#define FOC1B 6
638#define FOC1A 7
639
640#define TCNT1 _SFR_MEM16(0x84)
641
642#define TCNT1L _SFR_MEM8(0x84)
643#define TCNT1L0 0
644#define TCNT1L1 1
645#define TCNT1L2 2
646#define TCNT1L3 3
647#define TCNT1L4 4
648#define TCNT1L5 5
649#define TCNT1L6 6
650#define TCNT1L7 7
651
652#define TCNT1H _SFR_MEM8(0x85)
653#define TCNT1H0 0
654#define TCNT1H1 1
655#define TCNT1H2 2
656#define TCNT1H3 3
657#define TCNT1H4 4
658#define TCNT1H5 5
659#define TCNT1H6 6
660#define TCNT1H7 7
661
662#define ICR1 _SFR_MEM16(0x86)
663
664#define ICR1L _SFR_MEM8(0x86)
665#define ICR1L0 0
666#define ICR1L1 1
667#define ICR1L2 2
668#define ICR1L3 3
669#define ICR1L4 4
670#define ICR1L5 5
671#define ICR1L6 6
672#define ICR1L7 7
673
674#define ICR1H _SFR_MEM8(0x87)
675#define ICR1H0 0
676#define ICR1H1 1
677#define ICR1H2 2
678#define ICR1H3 3
679#define ICR1H4 4
680#define ICR1H5 5
681#define ICR1H6 6
682#define ICR1H7 7
683
684#define OCR1A _SFR_MEM16(0x88)
685
686#define OCR1AL _SFR_MEM8(0x88)
687#define OCR1AL0 0
688#define OCR1AL1 1
689#define OCR1AL2 2
690#define OCR1AL3 3
691#define OCR1AL4 4
692#define OCR1AL5 5
693#define OCR1AL6 6
694#define OCR1AL7 7
695
696#define OCR1AH _SFR_MEM8(0x89)
697#define OCR1AH0 0
698#define OCR1AH1 1
699#define OCR1AH2 2
700#define OCR1AH3 3
701#define OCR1AH4 4
702#define OCR1AH5 5
703#define OCR1AH6 6
704#define OCR1AH7 7
705
706#define OCR1B _SFR_MEM16(0x8A)
707
708#define OCR1BL _SFR_MEM8(0x8A)
709#define OCR1BL0 0
710#define OCR1BL1 1
711#define OCR1BL2 2
712#define OCR1BL3 3
713#define OCR1BL4 4
714#define OCR1BL5 5
715#define OCR1BL6 6
716#define OCR1BL7 7
717
718#define OCR1BH _SFR_MEM8(0x8B)
719#define OCR1BH0 0
720#define OCR1BH1 1
721#define OCR1BH2 2
722#define OCR1BH3 3
723#define OCR1BH4 4
724#define OCR1BH5 5
725#define OCR1BH6 6
726#define OCR1BH7 7
727
728#define OCR1C _SFR_MEM16(0x8C)
729
730#define OCR1CL _SFR_MEM8(0x8C)
731#define OCR1CL0 0
732#define OCR1CL1 1
733#define OCR1CL2 2
734#define OCR1CL3 3
735#define OCR1CL4 4
736#define OCR1CL5 5
737#define OCR1CL6 6
738#define OCR1CL7 7
739
740#define OCR1CH _SFR_MEM8(0x8D)
741#define OCR1CH0 0
742#define OCR1CH1 1
743#define OCR1CH2 2
744#define OCR1CH3 3
745#define OCR1CH4 4
746#define OCR1CH5 5
747#define OCR1CH6 6
748#define OCR1CH7 7
749
750#define TCCR3A _SFR_MEM8(0x90)
751#define WGM30 0
752#define WGM31 1
753#define COM3C0 2
754#define COM3C1 3
755#define COM3B0 4
756#define COM3B1 5
757#define COM3A0 6
758#define COM3A1 7
759
760#define TCCR3B _SFR_MEM8(0x91)
761#define CS30 0
762#define CS31 1
763#define CS32 2
764#define WGM32 3
765#define WGM33 4
766#define ICES3 6
767#define ICNC3 7
768
769#define TCCR3C _SFR_MEM8(0x92)
770#define FOC3C 5
771#define FOC3B 6
772#define FOC3A 7
773
774#define TCNT3 _SFR_MEM16(0x94)
775
776#define TCNT3L _SFR_MEM8(0x94)
777#define TCNT3L0 0
778#define TCNT3L1 1
779#define TCNT3L2 2
780#define TCNT3L3 3
781#define TCNT3L4 4
782#define TCNT3L5 5
783#define TCNT3L6 6
784#define TCNT3L7 7
785
786#define TCNT3H _SFR_MEM8(0x95)
787#define TCNT3H0 0
788#define TCNT3H1 1
789#define TCNT3H2 2
790#define TCNT3H3 3
791#define TCNT3H4 4
792#define TCNT3H5 5
793#define TCNT3H6 6
794#define TCNT3H7 7
795
796#define ICR3 _SFR_MEM16(0x96)
797
798#define ICR3L _SFR_MEM8(0x96)
799#define ICR3L0 0
800#define ICR3L1 1
801#define ICR3L2 2
802#define ICR3L3 3
803#define ICR3L4 4
804#define ICR3L5 5
805#define ICR3L6 6
806#define ICR3L7 7
807
808#define ICR3H _SFR_MEM8(0x97)
809#define ICR3H0 0
810#define ICR3H1 1
811#define ICR3H2 2
812#define ICR3H3 3
813#define ICR3H4 4
814#define ICR3H5 5
815#define ICR3H6 6
816#define ICR3H7 7
817
818#define OCR3A _SFR_MEM16(0x98)
819
820#define OCR3AL _SFR_MEM8(0x98)
821#define OCR3AL0 0
822#define OCR3AL1 1
823#define OCR3AL2 2
824#define OCR3AL3 3
825#define OCR3AL4 4
826#define OCR3AL5 5
827#define OCR3AL6 6
828#define OCR3AL7 7
829
830#define OCR3AH _SFR_MEM8(0x99)
831#define OCR3AH0 0
832#define OCR3AH1 1
833#define OCR3AH2 2
834#define OCR3AH3 3
835#define OCR3AH4 4
836#define OCR3AH5 5
837#define OCR3AH6 6
838#define OCR3AH7 7
839
840#define OCR3B _SFR_MEM16(0x9A)
841
842#define OCR3BL _SFR_MEM8(0x9A)
843#define OCR3BL0 0
844#define OCR3BL1 1
845#define OCR3BL2 2
846#define OCR3BL3 3
847#define OCR3BL4 4
848#define OCR3BL5 5
849#define OCR3BL6 6
850#define OCR3BL7 7
851
852#define OCR3BH _SFR_MEM8(0x9B)
853#define OCR3BH0 0
854#define OCR3BH1 1
855#define OCR3BH2 2
856#define OCR3BH3 3
857#define OCR3BH4 4
858#define OCR3BH5 5
859#define OCR3BH6 6
860#define OCR3BH7 7
861
862#define OCR3C _SFR_MEM16(0x9C)
863
864#define OCR3CL _SFR_MEM8(0x9C)
865#define OCR3CL0 0
866#define OCR3CL1 1
867#define OCR3CL2 2
868#define OCR3CL3 3
869#define OCR3CL4 4
870#define OCR3CL5 5
871#define OCR3CL6 6
872#define OCR3CL7 7
873
874#define OCR3CH _SFR_MEM8(0x9D)
875#define OCR3CH0 0
876#define OCR3CH1 1
877#define OCR3CH2 2
878#define OCR3CH3 3
879#define OCR3CH4 4
880#define OCR3CH5 5
881#define OCR3CH6 6
882#define OCR3CH7 7
883
884#define UHCON _SFR_MEM8(0x9E)
885
886#define UHINT _SFR_MEM8(0x9F)
887
888#define UHIEN _SFR_MEM8(0xA0)
889
890#define UHADDR _SFR_MEM8(0xA1)
891
892#define UHFNUM _SFR_MEM16(0xA2)
893
894#define UHFNUML _SFR_MEM8(0xA2)
895
896#define UHFNUMH _SFR_MEM8(0xA3)
897
898#define UHFLEN _SFR_MEM8(0xA4)
899
900#define UPINRQX _SFR_MEM8(0xA5)
901
902#define UPINTX _SFR_MEM8(0xA6)
903
904#define UPNUM _SFR_MEM8(0xA7)
905
906#define UPRST _SFR_MEM8(0xA8)
907
908#define UPCONX _SFR_MEM8(0xA9)
909
910#define UPCFG0X _SFR_MEM8(0xAA)
911
912#define UPCFG1X _SFR_MEM8(0xAB)
913
914#define UPSTAX _SFR_MEM8(0xAC)
915
916#define UPCFG2X _SFR_MEM8(0xAD)
917
918#define UPIENX _SFR_MEM8(0xAE)
919
920#define UPDATX _SFR_MEM8(0xAF)
921
922#define TCCR2A _SFR_MEM8(0xB0)
923#define WGM20 0
924#define WGM21 1
925#define COM2B0 4
926#define COM2B1 5
927#define COM2A0 6
928#define COM2A1 7
929
930#define TCCR2B _SFR_MEM8(0xB1)
931#define CS20 0
932#define CS21 1
933#define CS22 2
934#define WGM22 3
935#define FOC2B 6
936#define FOC2A 7
937
938#define TCNT2 _SFR_MEM8(0xB2)
939#define TCNT2_0 0
940#define TCNT2_1 1
941#define TCNT2_2 2
942#define TCNT2_3 3
943#define TCNT2_4 4
944#define TCNT2_5 5
945#define TCNT2_6 6
946#define TCNT2_7 7
947
948#define OCR2A _SFR_MEM8(0xB3)
949#define OCR2_0 0
950#define OCR2_1 1
951#define OCR2_2 2
952#define OCR2_3 3
953#define OCR2_4 4
954#define OCR2_5 5
955#define OCR2_6 6
956#define OCR2_7 7
957
958#define OCR2B _SFR_MEM8(0xB4)
959#define OCR2_0 0
960#define OCR2_1 1
961#define OCR2_2 2
962#define OCR2_3 3
963#define OCR2_4 4
964#define OCR2_5 5
965#define OCR2_6 6
966#define OCR2_7 7
967
968#define TWBR _SFR_MEM8(0xB8)
969#define TWBR0 0
970#define TWBR1 1
971#define TWBR2 2
972#define TWBR3 3
973#define TWBR4 4
974#define TWBR5 5
975#define TWBR6 6
976#define TWBR7 7
977
978#define TWSR _SFR_MEM8(0xB9)
979#define TWPS0 0
980#define TWPS1 1
981#define TWS3 3
982#define TWS4 4
983#define TWS5 5
984#define TWS6 6
985#define TWS7 7
986
987#define TWAR _SFR_MEM8(0xBA)
988#define TWGCE 0
989#define TWA0 1
990#define TWA1 2
991#define TWA2 3
992#define TWA3 4
993#define TWA4 5
994#define TWA5 6
995#define TWA6 7
996
997#define TWDR _SFR_MEM8(0xBB)
998#define TWD0 0
999#define TWD1 1
1000#define TWD2 2
1001#define TWD3 3
1002#define TWD4 4
1003#define TWD5 5
1004#define TWD6 6
1005#define TWD7 7
1006
1007#define TWCR _SFR_MEM8(0xBC)
1008#define TWIE 0
1009#define TWEN 2
1010#define TWWC 3
1011#define TWSTO 4
1012#define TWSTA 5
1013#define TWEA 6
1014#define TWINT 7
1015
1016#define TWAMR _SFR_MEM8(0xBD)
1017#define TWAM0 1
1018#define TWAM1 2
1019#define TWAM2 3
1020#define TWAM3 4
1021#define TWAM4 5
1022#define TWAM5 6
1023#define TWAM6 7
1024
1025#define TCNT4 _SFR_MEM16(0xBE)
1026
1027#define TCNT4L _SFR_MEM8(0xBE)
1028#define TC40 0
1029#define TC41 1
1030#define TC42 2
1031#define TC43 3
1032#define TC44 4
1033#define TC45 5
1034#define TC46 6
1035#define TC47 7
1036
1037#define TCNT4H _SFR_MEM8(0xBF)  /* Alias for naming consistency. */
1038#define TC4H _SFR_MEM8(0xBF)    /* Per XML device file. */
1039#define TC48 0
1040#define TC49 1
1041#define TC410 2
1042
1043#define TCCR4A _SFR_MEM8(0xC0)
1044#define PWM4B 0
1045#define PWM4A 1
1046#define FOC4B 2
1047#define FOC4A 3
1048#define COM4B0 4
1049#define COM4B1 5
1050#define COM4A0 6
1051#define COM4A1 7
1052
1053#define TCCR4B _SFR_MEM8(0xC1)
1054#define CS40 0
1055#define CS41 1
1056#define CS42 2
1057#define CS43 3
1058#define DTPS40 4
1059#define DTPS41 5
1060#define PSR4 6
1061#define PWM4X 7
1062
1063#define TCCR4C _SFR_MEM8(0xC2)
1064#define PWM4D 0
1065#define FOC4D 1
1066#define COM4D0 2
1067#define COM4D1 3
1068#define COM4B0S 4
1069#define COM4B1S 5
1070#define COM4A0S 6
1071#define COM4A1S 7
1072
1073#define TCCR4D _SFR_MEM8(0xC3)
1074#define WGM40 0
1075#define WGM41 1
1076#define FPF4 2
1077#define FPAC4 3
1078#define FPES4 4
1079#define FPNC4 5
1080#define FPEN4 6
1081#define FPIE4 7
1082
1083#define TCCR4E _SFR_MEM8(0xC4)
1084#define OC4OE0 0
1085#define OC4OE1 1
1086#define OC4OE2 2
1087#define OC4OE3 3
1088#define OC4OE4 4
1089#define OC4OE5 5
1090#define ENHC4 6
1091#define TLOCK4 7
1092
1093#define CLKSEL0 _SFR_MEM8(0xC5)
1094#define CLKS 0
1095#define EXTE 2
1096#define RCE 3
1097#define EXSUT0 4
1098#define EXSUT1 5
1099#define RCSUT0 6
1100#define RCSUT1 7
1101
1102#define CLKSEL1 _SFR_MEM8(0xC6)
1103#define EXCKSEL0 0
1104#define EXCKSEL1 1
1105#define EXCKSEL2 2
1106#define EXCKSEL3 3
1107#define RCCKSEL0 4
1108#define RCCKSEL1 5
1109#define RCCKSEL2 6
1110#define RCCKSEL3 7
1111
1112#define CLKSTA _SFR_MEM8(0xC7)
1113#define EXTON 0
1114#define RCON 1
1115
1116#define UCSR1A _SFR_MEM8(0xC8)
1117#define MPCM1 0
1118#define U2X1 1
1119#define UPE1 2
1120#define DOR1 3
1121#define FE1 4
1122#define UDRE1 5
1123#define TXC1 6
1124#define RXC1 7
1125
1126#define UCSR1B _SFR_MEM8(0xC9)
1127#define TXB81 0
1128#define RXB81 1
1129#define UCSZ12 2
1130#define TXEN1 3
1131#define RXEN1 4
1132#define UDRIE1 5
1133#define TXCIE1 6
1134#define RXCIE1 7
1135
1136#define UCSR1C _SFR_MEM8(0xCA)
1137#define UCPOL1 0
1138#define UCSZ10 1
1139#define UCSZ11 2
1140#define USBS1 3
1141#define UPM10 4
1142#define UPM11 5
1143#define UMSEL10 6
1144#define UMSEL11 7
1145
1146#define UBRR1 _SFR_MEM16(0xCC)
1147
1148#define UBRR1L _SFR_MEM8(0xCC)
1149
1150#define UBRR1H _SFR_MEM8(0xCD)
1151
1152#define UDR1 _SFR_MEM8(0xCE)
1153#define UDR1_0 0
1154#define UDR1_1 1
1155#define UDR1_2 2
1156#define UDR1_3 3
1157#define UDR1_4 4
1158#define UDR1_5 5
1159#define UDR1_6 6
1160#define UDR1_7 7
1161
1162#define OCR4A _SFR_MEM8(0xCF)
1163#define OCR4A0 0
1164#define OCR4A1 1
1165#define OCR4A2 2
1166#define OCR4A3 3
1167#define OCR4A4 4
1168#define OCR4A5 5
1169#define OCR4A6 6
1170#define OCR4A7 7
1171
1172#define OCR4B _SFR_MEM8(0xD0)
1173#define OCR4B0 0
1174#define OCR4B1 1
1175#define OCR4B2 2
1176#define OCR4B3 3
1177#define OCR4B4 4
1178#define OCR4B5 5
1179#define OCR4B6 6
1180#define OCR4B7 7
1181
1182#define OCR4C _SFR_MEM8(0xD1)
1183#define OCR4C0 0
1184#define OCR4C1 1
1185#define OCR4C2 2
1186#define OCR4C3 3
1187#define OCR4C4 4
1188#define OCR4C5 5
1189#define OCR4C6 6
1190#define OCR4C7 7
1191
1192#define OCR4D _SFR_MEM8(0xD2)
1193#define OCR4D0 0
1194#define OCR4D1 1
1195#define OCR4D2 2
1196#define OCR4D3 3
1197#define OCR4D4 4
1198#define OCR4D5 5
1199#define OCR4D6 6
1200#define OCR4D7 7
1201
1202#define DT4 _SFR_MEM8(0xD4)
1203#define DT4L0 0
1204#define DT4L1 1
1205#define DT4L2 2
1206#define DT4L3 3
1207#define DT4L4 4
1208#define DT4L5 5
1209#define DT4L6 6
1210#define DT4L7 7
1211
1212#define UHWCON _SFR_MEM8(0xD7)
1213#define UVREGE 0
1214
1215#define USBCON _SFR_MEM8(0xD8)
1216#define VBUSTE 0
1217#define OTGPADE 4
1218#define FRZCLK 5
1219#define USBE 7
1220
1221#define USBSTA _SFR_MEM8(0xD9)
1222#define VBUS 0
1223#define SPEED 3
1224
1225#define USBINT _SFR_MEM8(0xDA)
1226#define VBUSTI 0
1227
1228#define OTGCON _SFR_MEM8(0xDD)
1229
1230#define OTGIEN _SFR_MEM8(0xDE)
1231
1232#define OTGINT _SFR_MEM8(0xDF)
1233
1234#define UDCON _SFR_MEM8(0xE0)
1235#define DETACH 0
1236#define RMWKUP 1
1237#define LSM 2
1238#define RSTCPU 3
1239
1240#define UDINT _SFR_MEM8(0xE1)
1241#define SUSPI 0
1242#define SOFI 2
1243#define EORSTI 3
1244#define WAKEUPI 4
1245#define EORSMI 5
1246#define UPRSMI 6
1247
1248#define UDIEN _SFR_MEM8(0xE2)
1249#define SUSPE 0
1250#define SOFE 2
1251#define EORSTE 3
1252#define WAKEUPE 4
1253#define EORSME 5
1254#define UPRSME 6
1255
1256#define UDADDR _SFR_MEM8(0xE3)
1257#define UADD0 0
1258#define UADD1 1
1259#define UADD2 2
1260#define UADD3 3
1261#define UADD4 4
1262#define UADD5 5
1263#define UADD6 6
1264#define ADDEN 7
1265
1266#define UDFNUM _SFR_MEM16(0xE4)
1267
1268#define UDFNUML _SFR_MEM8(0xE4)
1269#define FNUM0 0
1270#define FNUM1 1
1271#define FNUM2 2
1272#define FNUM3 3
1273#define FNUM4 4
1274#define FNUM5 5
1275#define FNUM6 6
1276#define FNUM7 7
1277
1278#define UDFNUMH _SFR_MEM8(0xE5)
1279#define FNUM8 0
1280#define FNUM9 1
1281#define FNUM10 2
1282
1283#define UDMFN _SFR_MEM8(0xE6)
1284#define FNCERR 4
1285
1286#define UDTST _SFR_MEM8(0xE7)
1287
1288#define UEINTX _SFR_MEM8(0xE8)
1289#define TXINI 0
1290#define STALLEDI 1
1291#define RXOUTI 2
1292#define RXSTPI 3
1293#define NAKOUTI 4
1294#define RWAL 5
1295#define NAKINI 6
1296#define FIFOCON 7
1297
1298#define UENUM _SFR_MEM8(0xE9)
1299#define UENUM_0 0
1300#define UENUM_1 1
1301#define UENUM_2 2
1302
1303#define UERST _SFR_MEM8(0xEA)
1304#define EPRST0 0
1305#define EPRST1 1
1306#define EPRST2 2
1307#define EPRST3 3
1308#define EPRST4 4
1309#define EPRST5 5
1310#define EPRST6 6
1311
1312#define UECONX _SFR_MEM8(0xEB)
1313#define EPEN 0
1314#define RSTDT 3
1315#define STALLRQC 4
1316#define STALLRQ 5
1317
1318#define UECFG0X _SFR_MEM8(0xEC)
1319#define EPDIR 0
1320#define EPTYPE0 6
1321#define EPTYPE1 7
1322
1323#define UECFG1X _SFR_MEM8(0xED)
1324#define ALLOC 1
1325#define EPBK0 2
1326#define EPBK1 3
1327#define EPSIZE0 4
1328#define EPSIZE1 5
1329#define EPSIZE2 6
1330
1331#define UESTA0X _SFR_MEM8(0xEE)
1332#define NBUSYBK0 0
1333#define NBUSYBK1 1
1334#define DTSEQ0 2
1335#define DTSEQ1 3
1336#define UNDERFI 5
1337#define OVERFI 6
1338#define CFGOK 7
1339
1340#define UESTA1X _SFR_MEM8(0xEF)
1341#define CURRBK0 0
1342#define CURRBK1 1
1343#define CTRLDIR 2
1344
1345#define UEIENX _SFR_MEM8(0xF0)
1346#define TXINE 0
1347#define STALLEDE 1
1348#define RXOUTE 2
1349#define RXSTPE 3
1350#define NAKOUTE 4
1351#define NAKINE 6
1352#define FLERRE 7
1353
1354#define UEDATX _SFR_MEM8(0xF1)
1355#define DAT0 0
1356#define DAT1 1
1357#define DAT2 2
1358#define DAT3 3
1359#define DAT4 4
1360#define DAT5 5
1361#define DAT6 6
1362#define DAT7 7
1363
1364#define UEBCX _SFR_MEM16(0xF2)
1365
1366#define UEBCLX _SFR_MEM8(0xF2)
1367#define BYCT0 0
1368#define BYCT1 1
1369#define BYCT2 2
1370#define BYCT3 3
1371#define BYCT4 4
1372#define BYCT5 5
1373#define BYCT6 6
1374#define BYCT7 7
1375
1376#define UEBCHX _SFR_MEM8(0xF3)
1377
1378#define UEINT _SFR_MEM8(0xF4)
1379#define EPINT0 0
1380#define EPINT1 1
1381#define EPINT2 2
1382#define EPINT3 3
1383#define EPINT4 4
1384#define EPINT5 5
1385#define EPINT6 6
1386
1387#define UPERRX _SFR_MEM8(0xF5)
1388
1389#define UPBCLX _SFR_MEM8(0xF6)
1390
1391#define UPBCHX _SFR_MEM8(0xF7)
1392
1393#define UPINT _SFR_MEM8(0xF8)
1394
1395#define OTGTCON _SFR_MEM8(0xF9)
1396
1397
1398
1399/* Interrupt Vectors */
1400/* Interrupt Vector 0 is the reset vector. */
1401#define INT0_vect           _VECTOR(1)  /* External Interrupt Request 0 */
1402#define INT1_vect           _VECTOR(2)  /* External Interrupt Request 1 */
1403#define INT2_vect           _VECTOR(3)  /* External Interrupt Request 2 */
1404#define INT3_vect           _VECTOR(4)  /* External Interrupt Request 3 */
1405#define INT6_vect           _VECTOR(7)  /* External Interrupt Request 6 */
1406#define PCINT0_vect         _VECTOR(9)  /* Pin Change Interrupt Request 0 */
1407#define USB_GEN_vect        _VECTOR(10)  /* USB General Interrupt Request */
1408#define USB_COM_vect        _VECTOR(11)  /* USB Endpoint/Pipe Interrupt Communication Request */
1409#define WDT_vect            _VECTOR(12)  /* Watchdog Time-out Interrupt */
1410#define TIMER1_CAPT_vect    _VECTOR(16)  /* Timer/Counter1 Capture Event */
1411#define TIMER1_COMPA_vect   _VECTOR(17)  /* Timer/Counter1 Compare Match A */
1412#define TIMER1_COMPB_vect   _VECTOR(18)  /* Timer/Counter1 Compare Match B */
1413#define TIMER1_COMPC_vect   _VECTOR(19)  /* Timer/Counter1 Compare Match C */
1414#define TIMER1_OVF_vect     _VECTOR(20)  /* Timer/Counter1 Overflow */
1415#define TIMER0_COMPA_vect   _VECTOR(21)  /* Timer/Counter0 Compare Match A */
1416#define TIMER0_COMPB_vect   _VECTOR(22)  /* Timer/Counter0 Compare Match B */
1417#define TIMER0_OVF_vect     _VECTOR(23)  /* Timer/Counter0 Overflow */
1418#define SPI_STC_vect        _VECTOR(24)  /* SPI Serial Transfer Complete */
1419#define USART1_RX_vect      _VECTOR(25)  /* USART1, Rx Complete */
1420#define USART1_UDRE_vect    _VECTOR(26)  /* USART1 Data register Empty */
1421#define USART1_TX_vect      _VECTOR(27)  /* USART1, Tx Complete */
1422#define ANALOG_COMP_vect    _VECTOR(28)  /* Analog Comparator */
1423#define ADC_vect            _VECTOR(29)  /* ADC Conversion Complete */
1424#define EE_READY_vect       _VECTOR(30)  /* EEPROM Ready */
1425#define TIMER3_CAPT_vect    _VECTOR(31)  /* Timer/Counter3 Capture Event */
1426#define TIMER3_COMPA_vect   _VECTOR(32)  /* Timer/Counter3 Compare Match A */
1427#define TIMER3_COMPB_vect   _VECTOR(33)  /* Timer/Counter3 Compare Match B */
1428#define TIMER3_COMPC_vect   _VECTOR(34)  /* Timer/Counter3 Compare Match C */
1429#define TIMER3_OVF_vect     _VECTOR(35)  /* Timer/Counter3 Overflow */
1430#define TWI_vect            _VECTOR(36)  /* 2-wire Serial Interface         */
1431#define SPM_READY_vect      _VECTOR(37)  /* Store Program Memory Read */
1432#define TIMER4_COMPA_vect   _VECTOR(38)  /* Timer/Counter4 Compare Match A */
1433#define TIMER4_COMPB_vect   _VECTOR(39)  /* Timer/Counter4 Compare Match B */
1434#define TIMER4_COMPD_vect   _VECTOR(40)  /* Timer/Counter4 Compare Match D */
1435#define TIMER4_OVF_vect     _VECTOR(41)  /* Timer/Counter4 Overflow */
1436#define TIMER4_FPF_vect     _VECTOR(42)  /* Timer/Counter4 Fault Protection Interrupt */
1437
1438#define _VECTORS_SIZE (43 * 4)
1439
1440
1441
1442/* Constants */
1443#define SPM_PAGESIZE (128)
1444#define RAMSTART     (0x100)
1445#define RAMSIZE      (0xA00)
1446#define RAMEND       (RAMSTART + RAMSIZE - 1)  /* Last On-Chip SRAM Location */
1447#define XRAMSTART    (0x2200)
1448#define XRAMSIZE     (0x10000)
1449#define XRAMEND      (XRAMSIZE - 1)
1450#define E2END        (0x3FF)
1451#define E2PAGESIZE   (4)
1452#define FLASHEND     (0x7FFF)
1453
1454
1455
1456/* Fuses */
1457#define FUSE_MEMORY_SIZE 3
1458
1459/* Low Fuse Byte */
1460#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
1461#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
1462#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
1463#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
1464#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
1465#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
1466#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
1467#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
1468#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT1 & FUSE_CKDIV8)
1469
1470/* High Fuse Byte */
1471#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
1472#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
1473#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
1474#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1475#define FUSE_WDTON   (unsigned char)~_BV(4)  /* Watchdog timer always on */
1476#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1477#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
1478#define FUSE_OCDEN   (unsigned char)~_BV(7)  /* Enable OCD */
1479#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN)
1480
1481/* Extended Fuse Byte */
1482#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
1483#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
1484#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
1485#define FUSE_HWBE      (unsigned char)~_BV(3)  /* Hardware Boot Enable */
1486#define EFUSE_DEFAULT (0xFF)
1487
1488
1489
1490/* Lock Bits */
1491#define __LOCK_BITS_EXIST
1492#define __BOOT_LOCK_BITS_0_EXIST
1493#define __BOOT_LOCK_BITS_1_EXIST
1494
1495
1496
1497/* Signature */
1498#define SIGNATURE_0 0x1E
1499#define SIGNATURE_1 0x95
1500#define SIGNATURE_2 0x87
1501
1502
1503
1504#endif  /* _AVR_IOM32U4_H_ */
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