source: rtems/cpukit/score/cpu/avr/avr/iom32hvb.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 17.5 KB
Line 
1/* Copyright (c) 2007 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE.
30*/
31
32/* $Id$ */
33
34/* avr/iom32hvb.h - definitions for ATmega32HVB. */
35
36/* This file should only be included from <avr/io.h>, never directly. */
37
38#ifndef _AVR_IO_H_
39#  error "Include <avr/io.h> instead of this file."
40#endif
41
42#ifndef _AVR_IOXXX_H_
43#  define _AVR_IOXXX_H_ "iom32hvb.h"
44#else
45#  error "Attempt to include more than one <avr/ioXXX.h> file."
46#endif
47
48
49#ifndef _AVR_IOM32HVB_H_
50#define _AVR_IOM32HVB_H_ 1
51
52/* Registers and associated bit numbers */
53
54#define PINA _SFR_IO8(0x00)
55#define PINA0 0
56#define PINA1 1
57#define PINA2 2
58#define PINA3 3
59
60#define DDRA _SFR_IO8(0x01)
61#define DDA0 0
62#define DDA1 1
63#define DDA2 2
64#define DDA3 3
65
66#define PORTA _SFR_IO8(0x02)
67#define PORTA0 0
68#define PORTA1 1
69#define PORTA2 2
70#define PORTA3 3
71
72#define PINB _SFR_IO8(0x03)
73#define PINB0 0
74#define PINB1 1
75#define PINB2 2
76#define PINB3 3
77#define PINB4 4
78#define PINB5 5
79#define PINB6 6
80#define PINB7 7
81
82#define DDRB _SFR_IO8(0x04)
83#define DDB0 0
84#define DDB1 1
85#define DDB2 2
86#define DDB3 3
87#define DDB4 4
88#define DDB5 5
89#define DDB6 6
90#define DDB7 7
91
92#define PORTB _SFR_IO8(0x05)
93#define PORTB0 0
94#define PORTB1 1
95#define PORTB2 2
96#define PORTB3 3
97#define PORTB4 4
98#define PORTB5 5
99#define PORTB6 6
100#define PORTB7 7
101
102#define PINC _SFR_IO8(0x06)
103#define PINC0 0
104#define PINC1 1
105#define PINC2 2
106#define PINC3 3
107#define PINC4 4
108
109#define PORTC _SFR_IO8(0x08)
110#define PORTC0 0
111#define PORTC1 1
112#define PORTC2 2
113#define PORTC3 3
114#define PORTC4 4
115#define PORTC5 5
116
117#define TIFR0 _SFR_IO8(0x15)
118#define TOV0 0
119#define OCF0A 1
120#define OCF0B 2
121#define ICF0 3
122
123#define TIFR1 _SFR_IO8(0x16)
124#define TOV1 0
125#define OCF1A 1
126#define OCF1B 2
127#define ICF1 3
128
129#define OSICSR _SFR_IO8(0x17)
130#define OSIEN 0
131#define OSIST 1
132#define OSISEL0 4
133
134#define PCIFR _SFR_IO8(0x1B)
135#define PCIF0 0
136#define PCIF1 1
137
138#define EIFR _SFR_IO8(0x1C)
139#define INTF0 0
140#define INTF1 1
141#define INTF2 2
142#define INTF3 3
143
144#define EIMSK _SFR_IO8(0x1D)
145#define INT0 0
146#define INT1 1
147#define INT2 2
148#define INT3 3
149
150#define GPIOR0 _SFR_IO8(0x1E)
151#define GPIOR00 0
152#define GPIOR01 1
153#define GPIOR02 2
154#define GPIOR03 3
155#define GPIOR04 4
156#define GPIOR05 5
157#define GPIOR06 6
158#define GPIOR07 7
159
160#define EECR _SFR_IO8(0x1F)
161#define EERE 0
162#define EEPE 1
163#define EEMPE 2
164#define EERIE 3
165#define EEPM0 4
166#define EEPM1 5
167
168#define EEDR _SFR_IO8(0x20)
169#define EEDR0 0
170#define EEDR1 1
171#define EEDR2 2
172#define EEDR3 3
173#define EEDR4 4
174#define EEDR5 5
175#define EEDR6 6
176#define EEDR7 7
177
178#define EEAR _SFR_IO16(0x21)
179
180#define EEARL _SFR_IO8(0x21)
181#define EEAR0 0
182#define EEAR1 1
183#define EEAR2 2
184#define EEAR3 3
185#define EEAR4 4
186#define EEAR5 5
187#define EEAR6 6
188#define EEAR7 7
189
190#define EEARH _SFR_IO8(0x22)
191#define EEAR8 0
192#define EEAR9 1
193
194#define GTCCR _SFR_IO8(0x23)
195#define PSRSYNC 0
196#define TSM 7
197
198#define TCCR0A _SFR_IO8(0x24)
199#define WGM00 0
200#define ICS0 3
201#define ICES0 4
202#define ICNC0 5
203#define ICEN0 6
204#define TCW0 7
205
206#define TCCR0B _SFR_IO8(0x25)
207#define CS00 0
208#define CS01 1
209#define CS02 2
210
211#define TCNT0 _SFR_IO16(0x26)
212
213#define TCNT0L _SFR_IO8(0x26)
214#define TCNT0L0 0
215#define TCNT0L1 1
216#define TCNT0L2 2
217#define TCNT0L3 3
218#define TCNT0L4 4
219#define TCNT0L5 5
220#define TCNT0L6 6
221#define TCNT0L7 7
222
223#define TCNT0H _SFR_IO8(0x27)
224#define TCNT0H0 0
225#define TCNT0H1 1
226#define TCNT0H2 2
227#define TCNT0H3 3
228#define TCNT0H4 4
229#define TCNT0H5 5
230#define TCNT0H6 6
231#define TCNT0H7 7
232
233#define OCR0A _SFR_IO8(0x28)
234#define OCR0A0 0
235#define OCR0A1 1
236#define OCR0A2 2
237#define OCR0A3 3
238#define OCR0A4 4
239#define OCR0A5 5
240#define OCR0A6 6
241#define OCR0A7 7
242
243#define OCR0B _SFR_IO8(0x29)
244#define OCR0B0 0
245#define OCR0B1 1
246#define OCR0B2 2
247#define OCR0B3 3
248#define OCR0B4 4
249#define OCR0B5 5
250#define OCR0B6 6
251#define OCR0B7 7
252
253#define GPIOR1 _SFR_IO8(0x2A)
254#define GPIOR10 0
255#define GPIOR11 1
256#define GPIOR12 2
257#define GPIOR13 3
258#define GPIOR14 4
259#define GPIOR15 5
260#define GPIOR16 6
261#define GPIOR17 7
262
263#define GPIOR2 _SFR_IO8(0x2B)
264#define GPIOR20 0
265#define GPIOR21 1
266#define GPIOR22 2
267#define GPIOR23 3
268#define GPIOR24 4
269#define GPIOR25 5
270#define GPIOR26 6
271#define GPIOR27 7
272
273#define SPCR _SFR_IO8(0x2C)
274#define SPR0 0
275#define SPR1 1
276#define CPHA 2
277#define CPOL 3
278#define MSTR 4
279#define DORD 5
280#define SPE 6
281#define SPIE 7
282
283#define SPSR _SFR_IO8(0x2D)
284#define SPI2X 0
285#define WCOL 6
286#define SPIF 7
287
288#define SPDR _SFR_IO8(0x2E)
289#define SPDR0 0
290#define SPDR1 1
291#define SPDR2 2
292#define SPDR3 3
293#define SPDR4 4
294#define SPDR5 5
295#define SPDR6 6
296#define SPDR7 7
297
298#define SMCR _SFR_IO8(0x33)
299#define SE 0
300#define SM0 1
301#define SM1 2
302#define SM2 3
303
304#define MCUSR _SFR_IO8(0x34)
305#define PORF 0
306#define EXTRF 1
307#define BODRF 2
308#define WDRF 3
309#define OCDRF 4
310
311#define MCUCR _SFR_IO8(0x35)
312#define IVCE 0
313#define IVSEL 1
314#define PUD 4
315#define CKOE 5
316
317#define SPMCSR _SFR_IO8(0x37)
318#define SPMEN 0
319#define PGERS 1
320#define PGWRT 2
321#define LBSET 3
322#define RWWSRE 4
323#define SIGRD 5
324#define RWWSB 6
325#define SPMIE 7
326
327#define WDTCSR _SFR_MEM8(0x60)
328#define WDP0 0
329#define WDP1 1
330#define WDP2 2
331#define WDE 3
332#define WDCE 4
333#define WDP3 5
334#define WDIE 6
335#define WDIF 7
336
337#define CLKPR _SFR_MEM8(0x61)
338#define CLKPS0 0
339#define CLKPS1 1
340#define CLKPCE 7
341
342#define PRR0 _SFR_MEM8(0x64)
343#define PRVADC 0
344#define PRTIM0 1
345#define PRTIM1 2
346#define PRSPI 3
347#define PRVRM 5
348#define PRTWI 6
349
350#define FOSCCAL _SFR_MEM8(0x66)
351#define FCAL0 0
352#define FCAL1 1
353#define FCAL2 2
354#define FCAL3 3
355#define FCAL4 4
356#define FCAL5 5
357#define FCAL6 6
358#define FCAL7 7
359
360#define PCICR _SFR_MEM8(0x68)
361#define PCIE0 0
362#define PCIE1 1
363
364#define EICRA _SFR_MEM8(0x69)
365#define ISC00 0
366#define ISC01 1
367#define ISC10 2
368#define ISC11 3
369#define ISC20 4
370#define ISC21 5
371#define ISC30 6
372#define ISC31 7
373
374#define PCMSK0 _SFR_MEM8(0x6B)
375#define PCINT0 0
376#define PCINT1 1
377#define PCINT2 2
378#define PCINT3 3
379
380#define PCMSK1 _SFR_MEM8(0x6C)
381#define PCINT4 0
382#define PCINT5 1
383#define PCINT6 2
384#define PCINT7 3
385#define PCINT8 4
386#define PCINT9 5
387#define PCINT10 6
388#define PCINT11 7
389
390#define TIMSK0 _SFR_MEM8(0x6E)
391#define TOIE0 0
392#define OCIE0A 1
393#define OCIE0B 2
394#define ICIE0 3
395
396#define TIMSK1 _SFR_MEM8(0x6F)
397#define TOIE1 0
398#define OCIE1A 1
399#define OCIE1B 2
400#define ICIE1 3
401
402#define VADC _SFR_MEM16(0x78)
403
404#define VADCL _SFR_MEM8(0x78)
405#define VADC0 0
406#define VADC1 1
407#define VADC2 2
408#define VADC3 3
409#define VADC4 4
410#define VADC5 5
411#define VADC6 6
412#define VADC7 7
413
414#define VADCH _SFR_MEM8(0x79)
415#define VADC8 0
416#define VADC9 1
417#define VADC10 2
418#define VADC11 3
419
420#define VADCSR _SFR_MEM8(0x7A)
421#define VADCCIE 0
422#define VADCCIF 1
423#define VADSC 2
424#define VADEN 3
425
426#define VADMUX _SFR_MEM8(0x7C)
427#define VADMUX0 0
428#define VADMUX1 1
429#define VADMUX2 2
430#define VADMUX3 3
431
432#define DIDR0 _SFR_MEM8(0x7E)
433#define PA0DID 0
434#define PA1DID 1
435
436#define TCCR1A _SFR_MEM8(0x80)
437#define WGM10 0
438#define ICS1 3
439#define ICES1 4
440#define ICNC1 5
441#define ICEN1 6
442#define TCW1 7
443
444#define TCCR1B _SFR_MEM8(0x81)
445#define CS10 0
446#define CS11 1
447#define CS12 2
448
449#define TCNT1 _SFR_MEM16(0x84)
450
451#define TCNT1L _SFR_MEM8(0x84)
452#define TCNT1L0 0
453#define TCNT1L1 1
454#define TCNT1L2 2
455#define TCNT1L3 3
456#define TCNT1L4 4
457#define TCNT1L5 5
458#define TCNT1L6 6
459#define TCNT1L7 7
460
461#define TCNT1H _SFR_MEM8(0x85)
462#define TCNT1H0 0
463#define TCNT1H1 1
464#define TCNT1H2 2
465#define TCNT1H3 3
466#define TCNT1H4 4
467#define TCNT1H5 5
468#define TCNT1H6 6
469#define TCNT1H7 7
470
471#define OCR1A _SFR_MEM8(0x88)
472#define OCR1A0 0
473#define OCR1A1 1
474#define OCR1A2 2
475#define OCR1A3 3
476#define OCR1A4 4
477#define OCR1A5 5
478#define OCR1A6 6
479#define OCR1A7 7
480
481#define OCR1B _SFR_MEM8(0x89)
482#define OCR1B0 0
483#define OCR1B1 1
484#define OCR1B2 2
485#define OCR1B3 3
486#define OCR1B4 4
487#define OCR1B5 5
488#define OCR1B6 6
489#define OCR1B7 7
490
491#define TWBR _SFR_MEM8(0xB8)
492#define TWBR0 0
493#define TWBR1 1
494#define TWBR2 2
495#define TWBR3 3
496#define TWBR4 4
497#define TWBR5 5
498#define TWBR6 6
499#define TWBR7 7
500
501#define TWSR _SFR_MEM8(0xB9)
502#define TWPS0 0
503#define TWPS1 1
504#define TWS3 3
505#define TWS4 4
506#define TWS5 5
507#define TWS6 6
508#define TWS7 7
509
510#define TWAR _SFR_MEM8(0xBA)
511#define TWGCE 0
512#define TWA0 1
513#define TWA1 2
514#define TWA2 3
515#define TWA3 4
516#define TWA4 5
517#define TWA5 6
518#define TWA6 7
519
520#define TWDR _SFR_MEM8(0xBB)
521#define TWD0 0
522#define TWD1 1
523#define TWD2 2
524#define TWD3 3
525#define TWD4 4
526#define TWD5 5
527#define TWD6 6
528#define TWD7 7
529
530#define TWCR _SFR_MEM8(0xBC)
531#define TWIE 0
532#define TWEN 2
533#define TWWC 3
534#define TWSTO 4
535#define TWSTA 5
536#define TWEA 6
537#define TWINT 7
538
539#define TWAMR _SFR_MEM8(0xBD)
540#define TWAM0 0
541#define TWAM1 1
542#define TWAM2 2
543#define TWAM3 3
544#define TWAM4 4
545#define TWAM5 5
546#define TWAM6 6
547
548#define TWBCSR _SFR_MEM8(0xBE)
549#define TWBCIP 0
550#define TWBDT0 1
551#define TWBDT1 2
552#define TWBCIE 6
553#define TWBCIF 7
554
555#define ROCR _SFR_MEM8(0xC8)
556#define ROCWIE 0
557#define ROCWIF 1
558#define ROCD 4
559#define ROCS 7
560
561#define BGCCR _SFR_MEM8(0xD0)
562#define BGCC0 0
563#define BGCC1 1
564#define BGCC2 2
565#define BGCC3 3
566#define BGCC4 4
567#define BGCC5 5
568
569#define BGCRR _SFR_MEM8(0xD1)
570#define BGCR0 0
571#define BGCR1 1
572#define BGCR2 2
573#define BGCR3 3
574#define BGCR4 4
575#define BGCR5 5
576#define BGCR6 6
577#define BGCR7 7
578
579#define BGCSR _SFR_MEM8(0xD2)
580#define BGSCDIE 0
581#define BGSCDIF 1
582#define BGSCDE 4
583#define BGD 5
584
585#define CHGDCSR _SFR_MEM8(0xD4)
586#define CHGDIE 0
587#define CHGDIF 1
588#define CHGDISC0 2
589#define CHGDISC1 3
590#define BATTPVL 4
591
592#define CADAC _SFR_MEM32(0xE0)
593
594#define CADAC0 _SFR_MEM8(0xE0)
595#define CADAC00 0
596#define CADAC01 1
597#define CADAC02 2
598#define CADAC03 3
599#define CADAC04 4
600#define CADAC05 5
601#define CADAC06 6
602#define CADAC07 7
603
604#define CADAC1 _SFR_MEM8(0xE1)
605#define CADAC08 0
606#define CADAC09 1
607#define CADAC10 2
608#define CADAC11 3
609#define CADAC12 4
610#define CADAC13 5
611#define CADAC14 6
612#define CADAC15 7
613
614#define CADAC2 _SFR_MEM8(0xE2)
615#define CADAC16 0
616#define CADAC17 1
617#define CADAC18 2
618#define CADAC19 3
619#define CADAC20 4
620#define CADAC21 5
621#define CADAC22 6
622#define CADAC23 7
623
624#define CADAC3 _SFR_MEM8(0xE3)
625#define CADAC24 0
626#define CADAC25 1
627#define CADAC26 2
628#define CADAC27 3
629#define CADAC28 4
630#define CADAC29 5
631#define CADAC30 6
632#define CADAC31 7
633
634#define CADIC _SFR_MEM16(0xE4)
635
636#define CADICL _SFR_MEM8(0xE4)
637#define CADICL0 0
638#define CADICL1 1
639#define CADICL2 2
640#define CADICL3 3
641#define CADICL4 4
642#define CADICL5 5
643#define CADICL6 6
644#define CADICL7 7
645
646#define CADICH _SFR_MEM8(0xE5)
647#define CADICH0 0
648#define CADICH1 1
649#define CADICH2 2
650#define CADICH3 3
651#define CADICH4 4
652#define CADICH5 5
653#define CADICH6 6
654#define CADICH7 7
655
656#define CADCSRA _SFR_MEM8(0xE6)
657#define CADSE 0
658#define CADSI0 1
659#define CADSI1 2
660#define CADAS0 3
661#define CADAS1 4
662#define CADUB 5
663#define CADPOL 6
664#define CADEN 7
665
666#define CADCSRB _SFR_MEM8(0xE7)
667#define CADICIF 0
668#define CADRCIF 1
669#define CADACIF 2
670#define CADICIE 4
671#define CADRCIE 5
672#define CADACIE 6
673
674#define CADCSRC _SFR_MEM8(0xE8)
675#define CADVSE 0
676
677#define CADRCC _SFR_MEM8(0xE9)
678#define CADRCC0 0
679#define CADRCC1 1
680#define CADRCC2 2
681#define CADRCC3 3
682#define CADRCC4 4
683#define CADRCC5 5
684#define CADRCC6 6
685#define CADRCC7 7
686
687#define CADRDC _SFR_MEM8(0xEA)
688#define CADRDC0 0
689#define CADRDC1 1
690#define CADRDC2 2
691#define CADRDC3 3
692#define CADRDC4 4
693#define CADRDC5 5
694#define CADRDC6 6
695#define CADRDC7 7
696
697#define FCSR _SFR_MEM8(0xF0)
698#define CFE 0
699#define DFE 1
700#define CPS 2
701#define DUVRD 3
702
703#define CBCR _SFR_MEM8(0xF1)
704#define CBE1 0
705#define CBE2 1
706#define CBE3 2
707#define CBE4 3
708
709#define BPIMSK _SFR_MEM8(0xF2)
710#define CHCIE 0
711#define DHCIE 1
712#define COCIE 2
713#define DOCIE 3
714#define SCIE 4
715
716#define BPIFR _SFR_MEM8(0xF3)
717#define CHCIF 0
718#define DHCIF 1
719#define COCIF 2
720#define DOCIF 3
721#define SCIF 4
722
723#define BPSCD _SFR_MEM8(0xF5)
724#define SCDL0 0
725#define SCDL1 1
726#define SCDL2 2
727#define SCDL3 3
728#define SCDL4 4
729#define SCDL5 5
730#define SCDL6 6
731#define SCDL7 7
732
733#define BPDOCD _SFR_MEM8(0xF6)
734#define DOCDL0 0
735#define DOCDL1 1
736#define DOCDL2 2
737#define DOCDL3 3
738#define DOCDL4 4
739#define DOCDL5 5
740#define DOCDL6 6
741#define DOCDL7 7
742
743#define BPCOCD _SFR_MEM8(0xF7)
744#define COCDL0 0
745#define COCDL1 1
746#define COCDL2 2
747#define COCDL3 3
748#define COCDL4 4
749#define COCDL5 5
750#define COCDL6 6
751#define COCDL7 7
752
753#define BPDHCD _SFR_MEM8(0xF8)
754#define DHCDL0 0
755#define DHCDL1 1
756#define DHCDL2 2
757#define DHCDL3 3
758#define DHCDL4 4
759#define DHCDL5 5
760#define DHCDL6 6
761#define DHCDL7 7
762
763#define BPCHCD _SFR_MEM8(0xF9)
764#define CHCDL0 0
765#define CHCDL1 1
766#define CHCDL2 2
767#define CHCDL3 3
768#define CHCDL4 4
769#define CHCDL5 5
770#define CHCDL6 6
771#define CHCDL7 7
772
773#define BPSCTR _SFR_MEM8(0xFA)
774#define SCPT0 0
775#define SCPT1 1
776#define SCPT2 2
777#define SCPT3 3
778#define SCPT4 4
779#define SCPT5 5
780#define SCPT6 6
781
782#define BPOCTR _SFR_MEM8(0xFB)
783#define OCPT0 0
784#define OCPT1 1
785#define OCPT2 2
786#define OCPT3 3
787#define OCPT4 4
788#define OCPT5 5
789
790#define BPHCTR _SFR_MEM8(0xFC)
791#define HCPT0 0
792#define HCPT1 1
793#define HCPT2 2
794#define HCPT3 3
795#define HCPT4 4
796#define HCPT5 5
797
798#define BPCR _SFR_MEM8(0xFD)
799#define CHCD 0
800#define DHCD 1
801#define COCD 2
802#define DOCD 3
803#define SCD 4
804#define EPID 5
805
806#define BPPLR _SFR_MEM8(0xFE)
807#define BPPL 0
808#define BPPLE 1
809
810
811
812/* Interrupt Vectors */
813/* Interrupt Vector 0 is the reset vector. */
814
815#define BPINT_vect         _VECTOR(1)  /* Battery Protection Interrupt */
816#define VREGMON_vect       _VECTOR(2)  /* Voltage regulator monitor interrupt */
817#define INT0_vect          _VECTOR(3)  /* External Interrupt Request 0 */
818#define INT1_vect          _VECTOR(4)  /* External Interrupt Request 1 */
819#define INT2_vect          _VECTOR(5)  /* External Interrupt Request 2 */
820#define INT3_vect          _VECTOR(6)  /* External Interrupt Request 3 */
821#define PCINT0_vect        _VECTOR(7)  /* Pin Change Interrupt 0 */
822#define PCINT1_vect        _VECTOR(8)  /* Pin Change Interrupt 1 */
823#define WDT_vect           _VECTOR(9)  /* Watchdog Timeout Interrupt */
824#define BGSCD_vect         _VECTOR(10)  /* Bandgap Buffer Short Circuit Detected */
825#define CHDET_vect         _VECTOR(11)  /* Charger Detect */
826#define TIMER1_IC_vect     _VECTOR(12)  /* Timer 1 Input capture */
827#define TIMER1_COMPA_vect  _VECTOR(13)  /* Timer 1 Compare Match A */
828#define TIMER1_COMPB_vect  _VECTOR(14)  /* Timer 1 Compare Match B */
829#define TIMER1_OVF_vect    _VECTOR(15)  /* Timer 1 overflow */
830#define TIMER0_IC_vect     _VECTOR(16)  /* Timer 0 Input Capture */
831#define TIMER0_COMPA_vect  _VECTOR(17)  /* Timer 0 Comapre Match A */
832#define TIMER0_COMPB_vect  _VECTOR(18)  /* Timer 0 Compare Match B */
833#define TIMER0_OVF_vect    _VECTOR(19)  /* Timer 0 Overflow */
834#define TWIBUSCD_vect      _VECTOR(20)  /* Two-Wire Bus Connect/Disconnect */
835#define TWI_vect           _VECTOR(21)  /* Two-Wire Serial Interface */
836#define SPI_STC_vect       _VECTOR(22)  /* SPI Serial transfer complete */
837#define VADC_vect          _VECTOR(23)  /* Voltage ADC Conversion Complete */
838#define CCADC_CONV_vect    _VECTOR(24)  /* Coulomb Counter ADC Conversion Complete */
839#define CCADC_REG_CUR_vect _VECTOR(25)  /* Coloumb Counter ADC Regular Current */
840#define CCADC_ACC_vect     _VECTOR(26)  /* Coloumb Counter ADC Accumulator */
841#define EE_READY_vect      _VECTOR(27)  /* EEPROM Ready */
842#define SPM_vect           _VECTOR(28)  /* SPM Ready */
843
844#define _VECTORS_SIZE (29 * 4)
845
846
847/* Constants */
848#define SPM_PAGESIZE 64
849#define RAMEND       0x8FF     /* Last On-Chip SRAM Location */
850#define XRAMSIZE     0
851#define XRAMEND      RAMEND
852#define E2END        0x3FF
853#define FLASHEND     0x7FFF
854
855
856/* Fuses */
857
858#define FUSE_MEMORY_SIZE 2
859
860/* Low Fuse Byte */
861#define FUSE_WDTON   (unsigned char)~_BV(7)  /* Watchdog Timer Always On */
862#define FUSE_EESAVE  (unsigned char)~_BV(6)  /* EEPROM memory is preserved through chip erase */
863#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
864#define FUSE_SUT2    (unsigned char)~_BV(4)  /* Select start-up time */
865#define FUSE_SUT1    (unsigned char)~_BV(3)  /* Select start-up time */
866#define FUSE_SUT0    (unsigned char)~_BV(2)  /* Select start-up time */
867#define FUSE_OSCSEL1 (unsigned char)~_BV(1)  /* Oscillator Select */
868#define FUSE_OSCSEL0 (unsigned char)~_BV(0)  /* Oscillator Select */
869#define LFUSE_DEFAULT (FUSE_OSCSEL0 & FUSE_SPIEN)
870
871/* High Fuse Byte */
872#define FUSE_BOOTRST   (unsigned char)~_BV(0)  /* Select Reset Vector */
873#define FUSE_BOOTSZ0   (unsigned char)~_BV(1)  /* Select Boot Size */
874#define FUSE_BOOTSZ1   (unsigned char)~_BV(2)  /* Select Boot Size */
875#define FUSE_DWEN      (unsigned char)~_BV(3)  /* Enable debugWire */
876#define FUSE_DUVRDINIT (unsigned char)~_BV(4)  /* Reset Value of DUVRDRegister */
877#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_DUVRDINIT)
878
879
880
881/* Lock Bits */
882#define __LOCK_BITS_EXIST
883
884
885#endif  /* _AVR_IOM32HVB_H_ */
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