source: rtems/cpukit/score/cpu/avr/avr/iom32c1.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 25.2 KB
RevLine 
[04a62dce]1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom32c1.h - definitions for ATmega32C1 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iom32c1.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATmega32C1_H_
49#define _AVR_ATmega32C1_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINB _SFR_IO8(0x03)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59#define PINB4 4
60#define PINB5 5
61#define PINB6 6
62#define PINB7 7
63
64#define DDRB _SFR_IO8(0x04)
65#define DDB0 0
66#define DDB1 1
67#define DDB2 2
68#define DDB3 3
69#define DDB4 4
70#define DDB5 5
71#define DDB6 6
72#define DDB7 7
73
74#define PORTB _SFR_IO8(0x05)
75#define PORTB0 0
76#define PORTB1 1
77#define PORTB2 2
78#define PORTB3 3
79#define PORTB4 4
80#define PORTB5 5
81#define PORTB6 6
82#define PORTB7 7
83
84#define PINC _SFR_IO8(0x06)
85#define PINC0 0
86#define PINC1 1
87#define PINC2 2
88#define PINC3 3
89#define PINC4 4
90#define PINC5 5
91#define PINC6 6
92#define PINC7 7
93
94#define DDRC _SFR_IO8(0x07)
95#define DDC0 0
96#define DDC1 1
97#define DDC2 2
98#define DDC3 3
99#define DDC4 4
100#define DDC5 5
101#define DDC6 6
102#define DDC7 7
103
104#define PORTC _SFR_IO8(0x08)
105#define PORTC0 0
106#define PORTC1 1
107#define PORTC2 2
108#define PORTC3 3
109#define PORTC4 4
110#define PORTC5 5
111#define PORTC6 6
112#define PORTC7 7
113
114#define PIND _SFR_IO8(0x09)
115#define PIND0 0
116#define PIND1 1
117#define PIND2 2
118#define PIND3 3
119#define PIND4 4
120#define PIND5 5
121#define PIND6 6
122#define PIND7 7
123
124#define DDRD _SFR_IO8(0x0A)
125#define DDD0 0
126#define DDD1 1
127#define DDD2 2
128#define DDD3 3
129#define DDD4 4
130#define DDD5 5
131#define DDD6 6
132#define DDD7 7
133
134#define PORTD _SFR_IO8(0x0B)
135#define PORTD0 0
136#define PORTD1 1
137#define PORTD2 2
138#define PORTD3 3
139#define PORTD4 4
140#define PORTD5 5
141#define PORTD6 6
142#define PORTD7 7
143
144#define PINE _SFR_IO8(0x0C)
145#define PINE0 0
146#define PINE1 1
147#define PINE2 2
148
149#define DDRE _SFR_IO8(0x0D)
150#define DDE0 0
151#define DDE1 1
152#define DDE2 2
153
154#define PORTE _SFR_IO8(0x0E)
155#define PORTE0 0
156#define PORTE1 1
157#define PORTE2 2
158
159#define TIFR0 _SFR_IO8(0x15)
160#define TOV0 0
161#define OCF0A 1
162#define OCF0B 2
163
164#define TIFR1 _SFR_IO8(0x16)
165#define TOV1 0
166#define OCF1A 1
167#define OCF1B 2
168#define ICF1 5
169
170#define GPIOR1 _SFR_IO8(0x19)
171#define GPIOR10 0
172#define GPIOR11 1
173#define GPIOR12 2
174#define GPIOR13 3
175#define GPIOR14 4
176#define GPIOR15 5
177#define GPIOR16 6
178#define GPIOR17 7
179
180#define GPIOR2 _SFR_IO8(0x1A)
181#define GPIOR20 0
182#define GPIOR21 1
183#define GPIOR22 2
184#define GPIOR23 3
185#define GPIOR24 4
186#define GPIOR25 5
187#define GPIOR26 6
188#define GPIOR27 7
189
190#define PCIFR _SFR_IO8(0x1B)
191#define PCIF0 0
192#define PCIF1 1
193#define PCIF2 2
194#define PCIF3 3
195
196#define EIFR _SFR_IO8(0x1C)
197#define INTF0 0
198#define INTF1 1
199#define INTF2 2
200#define INTF3 3
201
202#define EIMSK _SFR_IO8(0x1D)
203#define INT0 0
204#define INT1 1
205#define INT2 2
206#define INT3 3
207
208#define GPIOR0 _SFR_IO8(0x1E)
209#define GPIOR00 0
210#define GPIOR01 1
211#define GPIOR02 2
212#define GPIOR03 3
213#define GPIOR04 4
214#define GPIOR05 5
215#define GPIOR06 6
216#define GPIOR07 7
217
218#define EECR _SFR_IO8(0x1F)
219#define EERE 0
220#define EEWE 1
221#define EEMWE 2
222#define EERIE 3
223#define EEPM0 4
224#define EEPM1 5
225
226#define EEDR _SFR_IO8(0x20)
227#define EEDR0 0
228#define EEDR1 1
229#define EEDR2 2
230#define EEDR3 3
231#define EEDR4 4
232#define EEDR5 5
233#define EEDR6 6
234#define EEDR7 7
235
236#define EEAR _SFR_IO16(0x21)
237
238#define EEARL _SFR_IO8(0x21)
239#define EEAR0 0
240#define EEAR1 1
241#define EEAR2 2
242#define EEAR3 3
243#define EEAR4 4
244#define EEAR5 5
245#define EEAR6 6
246#define EEAR7 7
247
248#define EEARH _SFR_IO8(0x22)
249#define EEAR8 0
250#define EEAR9 1
251
252#define GTCCR _SFR_IO8(0x23)
253#define PSR10 0
254#define PSRSYNC 0
255#define ICPSEL1 6
256#define TSM 7
257
258#define TCCR0A _SFR_IO8(0x24)
259#define WGM00 0
260#define WGM01 1
261#define COM0B0 4
262#define COM0B1 5
263#define COM0A0 6
264#define COM0A1 7
265
266#define TCCR0B _SFR_IO8(0x25)
267#define CS00 0
268#define CS01 1
269#define CS02 2
270#define WGM02 3
271#define FOC0B 6
272#define FOC0A 7
273
274#define TCNT0 _SFR_IO8(0x26)
275#define TCNT0_0 0
276#define TCNT0_1 1
277#define TCNT0_2 2
278#define TCNT0_3 3
279#define TCNT0_4 4
280#define TCNT0_5 5
281#define TCNT0_6 6
282#define TCNT0_7 7
283
284#define OCR0A _SFR_IO8(0x27)
285#define OCR0A_0 0
286#define OCR0A_1 1
287#define OCR0A_2 2
288#define OCR0A_3 3
289#define OCR0A_4 4
290#define OCR0A_5 5
291#define OCR0A_6 6
292#define OCR0A_7 7
293
294#define OCR0B _SFR_IO8(0x28)
295#define OCR0B_0 0
296#define OCR0B_1 1
297#define OCR0B_2 2
298#define OCR0B_3 3
299#define OCR0B_4 4
300#define OCR0B_5 5
301#define OCR0B_6 6
302#define OCR0B_7 7
303
304#define PLLCSR _SFR_IO8(0x29)
305#define PLOCK 0
306#define PLLE 1
307#define PLLF 2
308
309#define SPCR _SFR_IO8(0x2C)
310#define SPR0 0
311#define SPR1 1
312#define CPHA 2
313#define CPOL 3
314#define MSTR 4
315#define DORD 5
316#define SPE 6
317#define SPIE 7
318
319#define SPSR _SFR_IO8(0x2D)
320#define SPI2X 0
321#define WCOL 6
322#define SPIF 7
323
324#define SPDR _SFR_IO8(0x2E)
325#define SPDR0 0
326#define SPDR1 1
327#define SPDR2 2
328#define SPDR3 3
329#define SPDR4 4
330#define SPDR5 5
331#define SPDR6 6
332#define SPDR7 7
333
334#define ACSR _SFR_IO8(0x30)
335#define AC0O 0
336#define AC1O 1
337#define AC2O 2
338#define AC3O 3
339#define AC0IF 4
340#define AC1IF 5
341#define AC2IF 6
342#define AC3IF 7
343
344#define DWDR _SFR_IO8(0x31)
345
346#define SMCR _SFR_IO8(0x33)
347#define SE 0
348#define SM0 1
349#define SM1 2
350#define SM2 3
351
352#define MCUSR _SFR_IO8(0x34)
353#define PORF 0
354#define EXTRF 1
355#define BORF 2
356#define WDRF 3
357
358#define MCUCR _SFR_IO8(0x35)
359#define IVCE 0
360#define IVSEL 1
361#define PUD 4
362#define SPIPS 7
363
364#define SPMCSR _SFR_IO8(0x37)
365#define SPMEN 0
366#define PGERS 1
367#define PGWRT 2
368#define BLBSET 3
369#define RWWSRE 4
370#define SIGRD 5
371#define RWWSB 6
372#define SPMIE 7
373
374#define WDTCSR _SFR_MEM8(0x60)
375#define WDP0 0
376#define WDP1 1
377#define WDP2 2
378#define WDE 3
379#define WDCE 4
380#define WDP3 5
381#define WDIE 6
382#define WDIF 7
383
384#define CLKPR _SFR_MEM8(0x61)
385#define CLKPS0 0
386#define CLKPS1 1
387#define CLKPS2 2
388#define CLKPS3 3
389#define CLKPCE 7
390
391#define PRR _SFR_MEM8(0x64)
392#define PRADC 0
393#define PRLIN 1
394#define PRSPI 2
395#define PRTIM0 3
396#define PRTIM1 4
397#define PRPSC 5
398#define PRCAN 6
399
400#define OSCCAL _SFR_MEM8(0x66)
401#define CAL0 0
402#define CAL1 1
403#define CAL2 2
404#define CAL3 3
405#define CAL4 4
406#define CAL5 5
407#define CAL6 6
408
409#define PCICR _SFR_MEM8(0x68)
410#define PCIE0 0
411#define PCIE1 1
412#define PCIE2 2
413#define PCIE3 3
414
415#define EICRA _SFR_MEM8(0x69)
416#define ISC00 0
417#define ISC01 1
418#define ISC10 2
419#define ISC11 3
420#define ISC20 4
421#define ISC21 5
422#define ISC30 6
423#define ISC31 7
424
425#define PCMSK0 _SFR_MEM8(0x6A)
426#define PCINT0 0
427#define PCINT1 1
428#define PCINT2 2
429#define PCINT3 3
430#define PCINT4 4
431#define PCINT5 5
432#define PCINT6 6
433#define PCINT7 7
434
435#define PCMSK1 _SFR_MEM8(0x6B)
436#define PCINT8 0
437#define PCINT9 1
438#define PCINT10 2
439#define PCINT11 3
440#define PCINT12 4
441#define PCINT13 5
442#define PCINT14 6
443#define PCINT15 7
444
445#define PCMSK2 _SFR_MEM8(0x6C)
446#define PCINT16 0
447#define PCINT17 1
448#define PCINT18 2
449#define PCINT19 3
450#define PCINT20 4
451#define PCINT21 5
452#define PCINT22 6
453#define PCINT23 7
454
455#define PCMSK3 _SFR_MEM8(0x6D)
456#define PCINT24 0
457#define PCINT25 1
458#define PCINT26 2
459
460#define TIMSK0 _SFR_MEM8(0x6E)
461#define TOIE0 0
462#define OCIE0A 1
463#define OCIE0B 2
464
465#define TIMSK1 _SFR_MEM8(0x6F)
466#define TOIE1 0
467#define OCIE1A 1
468#define OCIE1B 2
469#define ICIE1 5
470
471#define AMP0CSR _SFR_MEM8(0x75)
472#define AMP0TS0 0
473#define AMP0TS1 1
474#define AMP0TS2 2
475#define AMPCMP0 3
476#define AMP0G0 4
477#define AMP0G1 5
478#define AMP0IS 6
479#define AMP0EN 7
480
481#define AMP1CSR _SFR_MEM8(0x76)
482#define AMP1TS0 0
483#define AMP1TS1 1
484#define AMP1TS2 2
485#define AMPCMP1 3
486#define AMP1G0 4
487#define AMP1G1 5
488#define AMP1IS 6
489#define AMP1EN 7
490
491#define AMP2CSR _SFR_MEM8(0x77)
492#define AMP2TS0 0
493#define AMP2TS1 1
494#define AMP2TS2 2
495#define AMPCMP2 3
496#define AMP2G0 4
497#define AMP2G1 5
498#define AMP2IS 6
499#define AMP2EN 7
500
501#ifndef __ASSEMBLER__
502#define ADC _SFR_MEM16(0x78)
503#endif
504#define ADCW _SFR_MEM16(0x78)
505
506#define ADCL _SFR_MEM8(0x78)
507#define ADCL0 0
508#define ADCL1 1
509#define ADCL2 2
510#define ADCL3 3
511#define ADCL4 4
512#define ADCL5 5
513#define ADCL6 6
514#define ADCL7 7
515
516#define ADCH _SFR_MEM8(0x79)
517#define ADCH0 0
518#define ADCH1 1
519#define ADCH2 2
520#define ADCH3 3
521#define ADCH4 4
522#define ADCH5 5
523#define ADCH6 6
524#define ADCH7 7
525
526#define ADCSRA _SFR_MEM8(0x7A)
527#define ADPS0 0
528#define ADPS1 1
529#define ADPS2 2
530#define ADIE 3
531#define ADIF 4
532#define ADATE 5
533#define ADSC 6
534#define ADEN 7
535
536#define ADCSRB _SFR_MEM8(0x7B)
537#define ADTS0 0
538#define ADTS1 1
539#define ADTS2 2
540#define ADTS3 3
541#define AREFEN 5
542#define ISRCEN 6
543#define ADHSM 7
544
545#define ADMUX _SFR_MEM8(0x7C)
546#define MUX0 0
547#define MUX1 1
548#define MUX2 2
549#define MUX3 3
550#define MUX4 4
551#define ADLAR 5
552#define REFS0 6
553#define REFS1 7
554
555#define DIDR0 _SFR_MEM8(0x7E)
556#define ADC0D 0
557#define ADC1D 1
558#define ADC2D 2
559#define ADC3D 3
560#define ADC4D 4
561#define ADC5D 5
562#define ADC6D 6
563#define ADC7D 7
564
565#define DIDR1 _SFR_MEM8(0x7F)
566#define ADC8D 0
567#define ADC9D 1
568#define ADC10D 2
569#define AMP0ND 3
570#define AMP0PD 4
571#define ACMP0D 5
572#define AMP2PD 6
573
574#define TCCR1A _SFR_MEM8(0x80)
575#define WGM10 0
576#define WGM11 1
577#define COM1B0 4
578#define COM1B1 5
579#define COM1A0 6
580#define COM1A1 7
581
582#define TCCR1B _SFR_MEM8(0x81)
583#define CS10 0
584#define CS11 1
585#define CS12 2
586#define WGM12 3
587#define WGM13 4
588#define ICES1 6
589#define ICNC1 7
590
591#define TCCR1C _SFR_MEM8(0x82)
592#define FOC1B 6
593#define FOC1A 7
594
595#define TCNT1 _SFR_MEM16(0x84)
596
597#define TCNT1L _SFR_MEM8(0x84)
598#define TCNT1L0 0
599#define TCNT1L1 1
600#define TCNT1L2 2
601#define TCNT1L3 3
602#define TCNT1L4 4
603#define TCNT1L5 5
604#define TCNT1L6 6
605#define TCNT1L7 7
606
607#define TCNT1H _SFR_MEM8(0x85)
608#define TCNT1H0 0
609#define TCNT1H1 1
610#define TCNT1H2 2
611#define TCNT1H3 3
612#define TCNT1H4 4
613#define TCNT1H5 5
614#define TCNT1H6 6
615#define TCNT1H7 7
616
617#define ICR1 _SFR_MEM16(0x86)
618
619#define ICR1L _SFR_MEM8(0x86)
620#define ICR1L0 0
621#define ICR1L1 1
622#define ICR1L2 2
623#define ICR1L3 3
624#define ICR1L4 4
625#define ICR1L5 5
626#define ICR1L6 6
627#define ICR1L7 7
628
629#define ICR1H _SFR_MEM8(0x87)
630#define ICR1H0 0
631#define ICR1H1 1
632#define ICR1H2 2
633#define ICR1H3 3
634#define ICR1H4 4
635#define ICR1H5 5
636#define ICR1H6 6
637#define ICR1H7 7
638
639#define OCR1A _SFR_MEM16(0x88)
640
641#define OCR1AL _SFR_MEM8(0x88)
642#define OCR1AL0 0
643#define OCR1AL1 1
644#define OCR1AL2 2
645#define OCR1AL3 3
646#define OCR1AL4 4
647#define OCR1AL5 5
648#define OCR1AL6 6
649#define OCR1AL7 7
650
651#define OCR1AH _SFR_MEM8(0x89)
652#define OCR1AH0 0
653#define OCR1AH1 1
654#define OCR1AH2 2
655#define OCR1AH3 3
656#define OCR1AH4 4
657#define OCR1AH5 5
658#define OCR1AH6 6
659#define OCR1AH7 7
660
661#define OCR1B _SFR_MEM16(0x8A)
662
663#define OCR1BL _SFR_MEM8(0x8A)
664#define OCR1BL0 0
665#define OCR1BL1 1
666#define OCR1BL2 2
667#define OCR1BL3 3
668#define OCR1BL4 4
669#define OCR1BL5 5
670#define OCR1BL6 6
671#define OCR1BL7 7
672
673#define OCR1BH _SFR_MEM8(0x8B)
674#define OCR1BH0 0
675#define OCR1BH1 1
676#define OCR1BH2 2
677#define OCR1BH3 3
678#define OCR1BH4 4
679#define OCR1BH5 5
680#define OCR1BH6 6
681#define OCR1BH7 7
682
683#define DACON _SFR_MEM8(0x90)
684#define DAEN 0
685#define DALA 2
686#define DATS0 4
687#define DATS1 5
688#define DATS2 6
689#define DAATE 7
690
691#define DAC _SFR_MEM16(0x91)
692
693#define DACL _SFR_MEM8(0x91)
694#define DACL0 0
695#define DACL1 1
696#define DACL2 2
697#define DACL3 3
698#define DACL4 4
699#define DACL5 5
700#define DACL6 6
701#define DACL7 7
702
703#define DACH _SFR_MEM8(0x92)
704#define DACH0 0
705#define DACH1 1
706#define DACH2 2
707#define DACH3 3
708#define DACH4 4
709#define DACH5 5
710#define DACH6 6
711#define DACH7 7
712
713#define AC0CON _SFR_MEM8(0x94)
714#define AC0M0 0
715#define AC0M1 1
716#define AC0M2 2
717#define ACCKSEL 3
718#define AC0IS0 4
719#define AC0IS1 5
720#define AC0IE 6
721#define AC0EN 7
722
723#define AC1CON _SFR_MEM8(0x95)
724#define AC1M0 0
725#define AC1M1 1
726#define AC1M2 2
727#define AC1ICE 3
728#define AC1IS0 4
729#define AC1IS1 5
730#define AC1IE 6
731#define AC1EN 7
732
733#define AC2CON _SFR_MEM8(0x96)
734#define AC2M0 0
735#define AC2M1 1
736#define AC2M2 2
737#define AC2IS0 4
738#define AC2IS1 5
739#define AC2IE 6
740#define AC2EN 7
741
742#define AC3CON _SFR_MEM8(0x97)
743#define AC3M0 0
744#define AC3M1 1
745#define AC3M2 2
746#define AC3IS0 4
747#define AC3IS1 5
748#define AC3IE 6
749#define AC3EN 7
750
751#define LINCR _SFR_MEM8(0xC8)
752#define LCMD0 0
753#define LCMD1 1
754#define LCMD2 2
755#define LENA 3
756#define LCONF0 4
757#define LCONF1 5
758#define LIN13 6
759#define LSWRES 7
760
761#define LINSIR _SFR_MEM8(0xC9)
762#define LRXOK 0
763#define LTXOK 1
764#define LIDOK 2
765#define LERR 3
766#define LBUSY 4
767#define LIDST0 5
768#define LIDST1 6
769#define LIDST2 7
770
771#define LINENIR _SFR_MEM8(0xCA)
772#define LENRXOK 0
773#define LENTXOK 1
774#define LENIDOK 2
775#define LENERR 3
776
777#define LINERR _SFR_MEM8(0xCB)
778#define LBERR 0
779#define LCERR 1
780#define LPERR 2
781#define LSERR 3
782#define LFERR 4
783#define LOVERR 5
784#define LTOERR 6
785#define LABORT 7
786
787#define LINBTR _SFR_MEM8(0xCC)
788#define LBT0 0
789#define LBT1 1
790#define LBT2 2
791#define LBT3 3
792#define LBT4 4
793#define LBT5 5
794#define LDISR 7
795
796#define LINBRR _SFR_MEM16(0xCD)
797
798#define LINBRRL _SFR_MEM8(0xCD)
799#define LDIV0 0
800#define LDIV1 1
801#define LDIV2 2
802#define LDIV3 3
803#define LDIV4 4
804#define LDIV5 5
805#define LDIV6 6
806#define LDIV7 7
807
808#define LINBRRH _SFR_MEM8(0xCE)
809#define LDIV8 0
810#define LDIV9 1
811#define LDIV10 2
812#define LDIV11 3
813
814#define LINDLR _SFR_MEM8(0xCF)
815#define LRXDL0 0
816#define LRXDL1 1
817#define LRXDL2 2
818#define LRXDL3 3
819#define LTXDL0 4
820#define LTXDL1 5
821#define LTXDL2 6
822#define LTXDL3 7
823
824#define LINIDR _SFR_MEM8(0xD0)
825#define LID0 0
826#define LID1 1
827#define LID2 2
828#define LID3 3
829#define LID4 4
830#define LID5 5
831#define LP0 6
832#define LP1 7
833
834#define LINSEL _SFR_MEM8(0xD1)
835#define LINDX0 0
836#define LINDX1 1
837#define LINDX2 2
838#define LAINC 3
839
840#define LINDAT _SFR_MEM8(0xD2)
841#define LDATA0 0
842#define LDATA1 1
843#define LDATA2 2
844#define LDATA3 3
845#define LDATA4 4
846#define LDATA5 5
847#define LDATA6 6
848#define LDATA7 7
849
850#define CANGCON _SFR_MEM8(0xD8)
851#define SWRES 0
852#define ENASTB 1
853#define TEST 2
854#define LISTEN 3
855#define SYNTTC 4
856#define TTC 5
857#define OVRQ 6
858#define ABRQ 7
859
860#define CANGSTA _SFR_MEM8(0xD9)
861#define ERRP 0
862#define BOFF 1
863#define ENFG 2
864#define RXBSY 3
865#define TXBSY 4
866#define OVFG 6
867
868#define CANGIT _SFR_MEM8(0xDA)
869#define AERG 0
870#define FERG 1
871#define CERG 2
872#define SERG 3
873#define BXOK 4
874#define OVRTIM 5
875#define BOFFIT 6
876#define CANIT 7
877
878#define CANGIE _SFR_MEM8(0xDB)
879#define ENOVRT 0
880#define ENERG 1
881#define ENBX 2
882#define ENERR 3
883#define ENTX 4
884#define ENRX 5
885#define ENBOFF 6
886#define ENIT 7
887
888#define CANEN2 _SFR_MEM8(0xDC)
889#define ENMOB0 0
890#define ENMOB1 1
891#define ENMOB2 2
892#define ENMOB3 3
893#define ENMOB4 4
894#define ENMOB5 5
895
896#define CANEN1 _SFR_MEM8(0xDD)
897
898#define CANIE2 _SFR_MEM8(0xDE)
899#define IEMOB0 0
900#define IEMOB1 1
901#define IEMOB2 2
902#define IEMOB3 3
903#define IEMOB4 4
904#define IEMOB5 5
905
906#define CANIE1 _SFR_MEM8(0xDF)
907
908#define CANSIT2 _SFR_MEM8(0xE0)
909#define SIT0 0
910#define SIT1 1
911#define SIT2 2
912#define SIT3 3
913#define SIT4 4
914#define SIT5 5
915
916#define CANSIT1 _SFR_MEM8(0xE1)
917
918#define CANBT1 _SFR_MEM8(0xE2)
919#define BRP0 1
920#define BRP1 2
921#define BRP2 3
922#define BRP3 4
923#define BRP4 5
924#define BRP5 6
925
926#define CANBT2 _SFR_MEM8(0xE3)
927#define PRS0 1
928#define PRS1 2
929#define PRS2 3
930#define SJW0 5
931#define SJW1 6
932
933#define CANBT3 _SFR_MEM8(0xE4)
934#define SMP 0
935#define PHS10 1
936#define PHS11 2
937#define PHS12 3
938#define PHS20 4
939#define PHS21 5
940#define PHS22 6
941
942#define CANTCON _SFR_MEM8(0xE5)
943#define TPRSC0 0
944#define TPRSC1 1
945#define TPRSC2 2
946#define TPRSC3 3
947#define TPRSC4 4
948#define TPRSC5 5
949#define TPRSC6 6
950#define TPRSC7 7
951
952#define CANTIM _SFR_MEM16(0xE6)
953
954#define CANTIML _SFR_MEM8(0xE6)
955#define CANTIM0 0
956#define CANTIM1 1
957#define CANTIM2 2
958#define CANTIM3 3
959#define CANTIM4 4
960#define CANTIM5 5
961#define CANTIM6 6
962#define CANTIM7 7
963
964#define CANTIMH _SFR_MEM8(0xE7)
965#define CANTIM8 0
966#define CANTIM9 1
967#define CANTIM10 2
968#define CANTIM11 3
969#define CANTIM12 4
970#define CANTIM13 5
971#define CANTIM14 6
972#define CANTIM15 7
973
974#define CANTTC _SFR_MEM16(0xE8)
975
976#define CANTTCL _SFR_MEM8(0xE8)
977#define TIMTCC0 0
978#define TIMTCC1 1
979#define TIMTCC2 2
980#define TIMTCC3 3
981#define TIMTCC4 4
982#define TIMTCC5 5
983#define TIMTCC6 6
984#define TIMTCC7 7
985
986#define CANTTCH _SFR_MEM8(0xE9)
987#define TIMTCC8 0
988#define TIMTCC9 1
989#define TIMTCC10 2
990#define TIMTCC11 3
991#define TIMTCC12 4
992#define TIMTCC13 5
993#define TIMTCC14 6
994#define TIMTCC15 7
995
996#define CANTEC _SFR_MEM8(0xEA)
997#define TEC0 0
998#define TEC1 1
999#define TEC2 2
1000#define TEC3 3
1001#define TEC4 4
1002#define TEC5 5
1003#define TEC6 6
1004#define TEC7 7
1005
1006#define CANREC _SFR_MEM8(0xEB)
1007#define REC0 0
1008#define REC1 1
1009#define REC2 2
1010#define REC3 3
1011#define REC4 4
1012#define REC5 5
1013#define REC6 6
1014#define REC7 7
1015
1016#define CANHPMOB _SFR_MEM8(0xEC)
1017#define CGP0 0
1018#define CGP1 1
1019#define CGP2 2
1020#define CGP3 3
1021#define HPMOB0 4
1022#define HPMOB1 5
1023#define HPMOB2 6
1024#define HPMOB3 7
1025
1026#define CANPAGE _SFR_MEM8(0xED)
1027#define INDX0 0
1028#define INDX1 1
1029#define INDX2 2
1030#define AINC 3
1031#define MOBNB0 4
1032#define MOBNB1 5
1033#define MOBNB2 6
1034#define MOBNB3 7
1035
1036#define CANSTMOB _SFR_MEM8(0xEE)
1037#define AERR 0
1038#define FERR 1
1039#define CERR 2
1040#define SERR 3
1041#define BERR 4
1042#define RXOK 5
1043#define TXOK 6
1044#define DLCW 7
1045
1046#define CANCDMOB _SFR_MEM8(0xEF)
1047#define DLC0 0
1048#define DLC1 1
1049#define DLC2 2
1050#define DLC3 3
1051#define IDE 4
1052#define RPLV 5
1053#define CONMOB0 6
1054#define CONMOB1 7
1055
1056#define CANIDT4 _SFR_MEM8(0xF0)
1057#define RB0TAG 0
1058#define RB1TAG 1
1059#define RTRTAG 2
1060#define IDT0 3
1061#define IDT1 4
1062#define IDT2 5
1063#define IDT3 6
1064#define IDT4 7
1065
1066#define CANIDT3 _SFR_MEM8(0xF1)
1067#define IDT5 0
1068#define IDT6 1
1069#define IDT7 2
1070#define IDT8 3
1071#define IDT9 4
1072#define IDT10 5
1073#define IDT11 6
1074#define IDT12 7
1075
1076#define CANIDT2 _SFR_MEM8(0xF2)
1077#define IDT13 0
1078#define IDT14 1
1079#define IDT15 2
1080#define IDT16 3
1081#define IDT17 4
1082#define IDT18 5
1083#define IDT19 6
1084#define IDT20 7
1085
1086#define CANIDT1 _SFR_MEM8(0xF3)
1087#define IDT21 0
1088#define IDT22 1
1089#define IDT23 2
1090#define IDT24 3
1091#define IDT25 4
1092#define IDT26 5
1093#define IDT27 6
1094#define IDT28 7
1095
1096#define CANIDM4 _SFR_MEM8(0xF4)
1097#define IDEMSK 0
1098#define RTRMSK 2
1099#define IDMSK0 3
1100#define IDMSK1 4
1101#define IDMSK2 5
1102#define IDMSK3 6
1103#define IDMSK4 7
1104
1105#define CANIDM3 _SFR_MEM8(0xF5)
1106#define IDMSK5 0
1107#define IDMSK6 1
1108#define IDMSK7 2
1109#define IDMSK8 3
1110#define IDMSK9 4
1111#define IDMSK10 5
1112#define IDMSK11 6
1113#define IDMSK12 7
1114
1115#define CANIDM2 _SFR_MEM8(0xF6)
1116#define IDMSK13 0
1117#define IDMSK14 1
1118#define IDMSK15 2
1119#define IDMSK16 3
1120#define IDMSK17 4
1121#define IDMSK18 5
1122#define IDMSK19 6
1123#define IDMSK20 7
1124
1125#define CANIDM1 _SFR_MEM8(0xF7)
1126#define IDMSK21 0
1127#define IDMSK22 1
1128#define IDMSK23 2
1129#define IDMSK24 3
1130#define IDMSK25 4
1131#define IDMSK26 5
1132#define IDMSK27 6
1133#define IDMSK28 7
1134
1135#define CANSTM _SFR_MEM16(0xF8)
1136
1137#define CANSTML _SFR_MEM8(0xF8)
1138#define TIMSTM0 0
1139#define TIMSTM1 1
1140#define TIMSTM2 2
1141#define TIMSTM3 3
1142#define TIMSTM4 4
1143#define TIMSTM5 5
1144#define TIMSTM6 6
1145#define TIMSTM7 7
1146
1147#define CANSTMH _SFR_MEM8(0xF9)
1148#define TIMSTM8 0
1149#define TIMSTM9 1
1150#define TIMSTM10 2
1151#define TIMSTM11 3
1152#define TIMSTM12 4
1153#define TIMSTM13 5
1154#define TIMSTM14 6
1155#define TIMSTM15 7
1156
1157#define CANMSG _SFR_MEM8(0xFA)
1158#define MSG0 0
1159#define MSG1 1
1160#define MSG2 2
1161#define MSG3 3
1162#define MSG4 4
1163#define MSG5 5
1164#define MSG6 6
1165#define MSG7 7
1166
1167
1168/* Interrupt vectors */
1169/* Vector 0 is the reset vector */
1170#define ANACOMP0_vect_num  1
1171#define ANACOMP0_vect      _VECTOR(1)  /* Analog Comparator 0 */
1172#define ANACOMP1_vect_num  2
1173#define ANACOMP1_vect      _VECTOR(2)  /* Analog Comparator 1 */
1174#define ANACOMP2_vect_num  3
1175#define ANACOMP2_vect      _VECTOR(3)  /* Analog Comparator 2 */
1176#define ANACOMP3_vect_num  4
1177#define ANACOMP3_vect      _VECTOR(4)  /* Analog Comparator 3 */
1178#define PSC_FAULT_vect_num  5
1179#define PSC_FAULT_vect      _VECTOR(5)  /* PSC Fault */
1180#define PSC_EC_vect_num  6
1181#define PSC_EC_vect      _VECTOR(6)  /* PSC End of Cycle */
1182#define INT0_vect_num  7
1183#define INT0_vect      _VECTOR(7)  /* External Interrupt Request 0 */
1184#define INT1_vect_num  8
1185#define INT1_vect      _VECTOR(8)  /* External Interrupt Request 1 */
1186#define INT2_vect_num  9
1187#define INT2_vect      _VECTOR(9)  /* External Interrupt Request 2 */
1188#define INT3_vect_num  10
1189#define INT3_vect      _VECTOR(10)  /* External Interrupt Request 3 */
1190#define TIMER1_CAPT_vect_num  11
1191#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
1192#define TIMER1_COMPA_vect_num  12
1193#define TIMER1_COMPA_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match A */
1194#define TIMER1_COMPB_vect_num  13
1195#define TIMER1_COMPB_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match B */
1196#define TIMER1_OVF_vect_num  14
1197#define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
1198#define TIMER0_COMPA_vect_num  15
1199#define TIMER0_COMPA_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match A */
1200#define TIMER0_COMPB_vect_num  16
1201#define TIMER0_COMPB_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match B */
1202#define TIMER0_OVF_vect_num  17
1203#define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
1204#define CAN_INT_vect_num  18
1205#define CAN_INT_vect      _VECTOR(18)  /* CAN MOB, Burst, General Errors */
1206#define CAN_TOVF_vect_num  19
1207#define CAN_TOVF_vect      _VECTOR(19)  /* CAN Timer Overflow */
1208#define LIN_TC_vect_num  20
1209#define LIN_TC_vect      _VECTOR(20)  /* LIN Transfer Complete */
1210#define LIN_ERR_vect_num  21
1211#define LIN_ERR_vect      _VECTOR(21)  /* LIN Error */
1212#define PCINT0_vect_num  22
1213#define PCINT0_vect      _VECTOR(22)  /* Pin Change Interrupt Request 0 */
1214#define PCINT1_vect_num  23
1215#define PCINT1_vect      _VECTOR(23)  /* Pin Change Interrupt Request 1 */
1216#define PCINT2_vect_num  24
1217#define PCINT2_vect      _VECTOR(24)  /* Pin Change Interrupt Request 2 */
1218#define PCINT3_vect_num  25
1219#define PCINT3_vect      _VECTOR(25)  /* Pin Change Interrupt Request 3 */
1220#define SPI_STC_vect_num  26
1221#define SPI_STC_vect      _VECTOR(26)  /* SPI Serial Transfer Complete */
1222#define ADC_vect_num  27
1223#define ADC_vect      _VECTOR(27)  /* ADC Conversion Complete */
1224#define WDT_vect_num  28
1225#define WDT_vect      _VECTOR(28)  /* Watchdog Time-Out Interrupt */
1226#define EE_READY_vect_num  29
1227#define EE_READY_vect      _VECTOR(29)  /* EEPROM Ready */
1228#define SPM_READY_vect_num  30
1229#define SPM_READY_vect      _VECTOR(30)  /* Store Program Memory Read */
1230
1231#define _VECTOR_SIZE 4 /* Size of individual vector. */
1232#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
1233
1234
1235/* Constants */
1236#define SPM_PAGESIZE (128)
1237#define RAMSTART     (0x0100)
1238#define RAMSIZE      (2048)
1239#define RAMEND       (RAMSTART + RAMSIZE - 1)
1240#define XRAMSTART    (0x0)
1241#define XRAMSIZE     (0)
1242#define XRAMEND      (RAMEND)
1243#define E2END        (0x3FF)
1244#define E2PAGESIZE   (4)
1245#define FLASHEND     (0x7FFF)
1246
1247
1248/* Fuses */
1249#define FUSE_MEMORY_SIZE 3
1250
1251/* Low Fuse Byte */
1252#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
1253#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
1254#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
1255#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
1256#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
1257#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
1258#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
1259#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
1260#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
1261
1262/* High Fuse Byte */
1263#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
1264#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
1265#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
1266#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1267#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
1268#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1269#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
1270#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
1271#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1272
1273/* Extended Fuse Byte */
1274#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector Trigger Level */
1275#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector Trigger Level */
1276#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector Trigger Level */
1277#define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
1278#define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
1279#define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
1280#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
1281
1282
1283/* Lock Bits */
1284#define __LOCK_BITS_EXIST
1285#define __BOOT_LOCK_BITS_0_EXIST
1286#define __BOOT_LOCK_BITS_1_EXIST
1287
1288
1289/* Signature */
1290#define SIGNATURE_0 0x1E
1291#define SIGNATURE_1 0x95
1292#define SIGNATURE_2 0x86
1293
1294
1295#endif /* _AVR_ATmega32C1_H_ */
1296
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