[04a62dce] | 1 | /* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/iom3250.h - definitions for ATmega3250 and ATmega3250P. */ |
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| 34 | |
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| 35 | #ifndef _AVR_IOM3250_H_ |
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| 36 | #define _AVR_IOM3250_H_ 1 |
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| 37 | |
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| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 39 | |
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| 40 | #ifndef _AVR_IO_H_ |
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| 41 | # error "Include <avr/io.h> instead of this file." |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifndef _AVR_IOXXX_H_ |
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| 45 | # define _AVR_IOXXX_H_ "iom3250.h" |
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| 46 | #else |
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| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 48 | #endif |
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| 49 | |
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| 50 | /* Registers and associated bit numbers */ |
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| 51 | |
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| 52 | #define PINA _SFR_IO8(0x00) |
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| 53 | #define PINA7 7 |
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| 54 | #define PINA6 6 |
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| 55 | #define PINA5 5 |
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| 56 | #define PINA4 4 |
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| 57 | #define PINA3 3 |
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| 58 | #define PINA2 2 |
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| 59 | #define PINA1 1 |
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| 60 | #define PINA0 0 |
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| 61 | |
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| 62 | #define DDRA _SFR_IO8(0x01) |
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| 63 | #define DDA7 7 |
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| 64 | #define DDA6 6 |
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| 65 | #define DDA5 5 |
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| 66 | #define DDA4 4 |
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| 67 | #define DDA3 3 |
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| 68 | #define DDA2 2 |
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| 69 | #define DDA1 1 |
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| 70 | #define DDA0 0 |
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| 71 | |
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| 72 | #define PORTA _SFR_IO8(0x02) |
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| 73 | #define PA7 7 |
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| 74 | #define PA6 6 |
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| 75 | #define PA5 5 |
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| 76 | #define PA4 4 |
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| 77 | #define PA3 3 |
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| 78 | #define PA2 2 |
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| 79 | #define PA1 1 |
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| 80 | #define PA0 0 |
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| 81 | |
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| 82 | #define PINB _SFR_IO8(0x03) |
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| 83 | #define PINB7 7 |
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| 84 | #define PINB6 6 |
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| 85 | #define PINB5 5 |
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| 86 | #define PINB4 4 |
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| 87 | #define PINB3 3 |
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| 88 | #define PINB2 2 |
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| 89 | #define PINB1 1 |
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| 90 | #define PINB0 0 |
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| 91 | |
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| 92 | #define DDRB _SFR_IO8(0x04) |
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| 93 | #define DDB7 7 |
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| 94 | #define DDB6 6 |
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| 95 | #define DDB5 5 |
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| 96 | #define DDB4 4 |
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| 97 | #define DDB3 3 |
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| 98 | #define DDB2 2 |
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| 99 | #define DDB1 1 |
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| 100 | #define DDB0 0 |
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| 101 | |
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| 102 | #define PORTB _SFR_IO8(0x05) |
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| 103 | #define PB7 7 |
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| 104 | #define PB6 6 |
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| 105 | #define PB5 5 |
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| 106 | #define PB4 4 |
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| 107 | #define PB3 3 |
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| 108 | #define PB2 2 |
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| 109 | #define PB1 1 |
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| 110 | #define PB0 0 |
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| 111 | |
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| 112 | #define PINC _SFR_IO8(0x06) |
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| 113 | #define PINC7 7 |
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| 114 | #define PINC6 6 |
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| 115 | #define PINC5 5 |
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| 116 | #define PINC4 4 |
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| 117 | #define PINC3 3 |
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| 118 | #define PINC2 2 |
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| 119 | #define PINC1 1 |
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| 120 | #define PINC0 0 |
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| 121 | |
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| 122 | #define DDRC _SFR_IO8(0x07) |
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| 123 | #define DDC7 7 |
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| 124 | #define DDC6 6 |
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| 125 | #define DDC5 5 |
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| 126 | #define DDC4 4 |
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| 127 | #define DDC3 3 |
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| 128 | #define DDC2 2 |
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| 129 | #define DDC1 1 |
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| 130 | #define DDC0 0 |
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| 131 | |
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| 132 | #define PORTC _SFR_IO8(0x08) |
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| 133 | #define PC7 7 |
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| 134 | #define PC6 6 |
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| 135 | #define PC5 5 |
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| 136 | #define PC4 4 |
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| 137 | #define PC3 3 |
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| 138 | #define PC2 2 |
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| 139 | #define PC1 1 |
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| 140 | #define PC0 0 |
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| 141 | |
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| 142 | #define PIND _SFR_IO8(0x09) |
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| 143 | #define PIND7 7 |
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| 144 | #define PIND6 6 |
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| 145 | #define PIND5 5 |
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| 146 | #define PIND4 4 |
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| 147 | #define PIND3 3 |
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| 148 | #define PIND2 2 |
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| 149 | #define PIND1 1 |
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| 150 | #define PIND0 0 |
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| 151 | |
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| 152 | #define DDRD _SFR_IO8(0x0A) |
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| 153 | #define DDD7 7 |
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| 154 | #define DDD6 6 |
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| 155 | #define DDD5 5 |
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| 156 | #define DDD4 4 |
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| 157 | #define DDD3 3 |
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| 158 | #define DDD2 2 |
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| 159 | #define DDD1 1 |
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| 160 | #define DDD0 0 |
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| 161 | |
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| 162 | #define PORTD _SFR_IO8(0x0B) |
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| 163 | #define PD7 7 |
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| 164 | #define PD6 6 |
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| 165 | #define PD5 5 |
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| 166 | #define PD4 4 |
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| 167 | #define PD3 3 |
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| 168 | #define PD2 2 |
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| 169 | #define PD1 1 |
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| 170 | #define PD0 0 |
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| 171 | |
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| 172 | #define PINE _SFR_IO8(0x0C) |
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| 173 | #define PINE7 7 |
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| 174 | #define PINE6 6 |
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| 175 | #define PINE5 5 |
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| 176 | #define PINE4 4 |
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| 177 | #define PINE3 3 |
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| 178 | #define PINE2 2 |
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| 179 | #define PINE1 1 |
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| 180 | #define PINE0 0 |
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| 181 | |
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| 182 | #define DDRE _SFR_IO8(0x0D) |
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| 183 | #define DDE7 7 |
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| 184 | #define DDE6 6 |
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| 185 | #define DDE5 5 |
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| 186 | #define DDE4 4 |
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| 187 | #define DDE3 3 |
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| 188 | #define DDE2 2 |
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| 189 | #define DDE1 1 |
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| 190 | #define DDE0 0 |
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| 191 | |
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| 192 | #define PORTE _SFR_IO8(0x0E) |
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| 193 | #define PE7 7 |
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| 194 | #define PE6 6 |
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| 195 | #define PE5 5 |
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| 196 | #define PE4 4 |
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| 197 | #define PE3 3 |
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| 198 | #define PE2 2 |
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| 199 | #define PE1 1 |
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| 200 | #define PE0 0 |
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| 201 | |
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| 202 | #define PINF _SFR_IO8(0x0F) |
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| 203 | #define PINF7 7 |
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| 204 | #define PINF6 6 |
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| 205 | #define PINF5 5 |
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| 206 | #define PINF4 4 |
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| 207 | #define PINF3 3 |
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| 208 | #define PINF2 2 |
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| 209 | #define PINF1 1 |
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| 210 | #define PINF0 0 |
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| 211 | |
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| 212 | #define DDRF _SFR_IO8(0x10) |
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| 213 | #define DDF7 7 |
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| 214 | #define DDF6 6 |
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| 215 | #define DDF5 5 |
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| 216 | #define DDF4 4 |
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| 217 | #define DDF3 3 |
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| 218 | #define DDF2 2 |
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| 219 | #define DDF1 1 |
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| 220 | #define DDF0 0 |
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| 221 | |
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| 222 | #define PORTF _SFR_IO8(0x11) |
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| 223 | #define PF7 7 |
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| 224 | #define PF6 6 |
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| 225 | #define PF5 5 |
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| 226 | #define PF4 4 |
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| 227 | #define PF3 3 |
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| 228 | #define PF2 2 |
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| 229 | #define PF1 1 |
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| 230 | #define PF0 0 |
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| 231 | |
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| 232 | #define PING _SFR_IO8(0x12) |
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| 233 | #define PING5 5 |
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| 234 | #define PING4 4 |
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| 235 | #define PING3 3 |
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| 236 | #define PING2 2 |
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| 237 | #define PING1 1 |
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| 238 | #define PING0 0 |
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| 239 | |
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| 240 | #define DDRG _SFR_IO8(0x13) |
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| 241 | #define DDG4 4 |
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| 242 | #define DDG3 3 |
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| 243 | #define DDG2 2 |
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| 244 | #define DDG1 1 |
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| 245 | #define DDG0 0 |
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| 246 | |
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| 247 | #define PORTG _SFR_IO8(0x14) |
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| 248 | #define PG4 4 |
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| 249 | #define PG3 3 |
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| 250 | #define PG2 2 |
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| 251 | #define PG1 1 |
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| 252 | #define PG0 0 |
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| 253 | |
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| 254 | #define TIFR0 _SFR_IO8(0x15) |
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| 255 | #define TOV0 0 |
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| 256 | #define OCF0A 1 |
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| 257 | |
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| 258 | #define TIFR1 _SFR_IO8(0x16) |
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| 259 | #define TOV1 0 |
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| 260 | #define OCF1A 1 |
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| 261 | #define OCF1B 2 |
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| 262 | #define ICF1 5 |
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| 263 | |
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| 264 | #define TIFR2 _SFR_IO8(0x17) |
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| 265 | #define TOV2 0 |
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| 266 | #define OCF2A 1 |
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| 267 | |
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| 268 | /* Reserved [0x18..0x1B] */ |
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| 269 | |
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| 270 | #define EIFR _SFR_IO8(0x1C) |
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| 271 | #define INTF0 0 |
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| 272 | #define PCIF0 4 |
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| 273 | #define PCIF1 5 |
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| 274 | #define PCIF2 6 |
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| 275 | #define PCIF3 7 |
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| 276 | |
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| 277 | #define EIMSK _SFR_IO8(0x1D) |
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| 278 | #define INT0 0 |
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| 279 | #define PCIE0 4 |
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| 280 | #define PCIE1 5 |
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| 281 | #define PCIE2 6 |
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| 282 | #define PCIE3 7 |
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| 283 | |
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| 284 | #define GPIOR0 _SFR_IO8(0x1E) |
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| 285 | |
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| 286 | #define EECR _SFR_IO8(0x1F) |
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| 287 | #define EERE 0 |
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| 288 | #define EEWE 1 |
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| 289 | #define EEMWE 2 |
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| 290 | #define EERIE 3 |
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| 291 | |
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| 292 | #define EEDR _SFR_IO8(0X20) |
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| 293 | |
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| 294 | /* Combine EEARL and EEARH */ |
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| 295 | #define EEAR _SFR_IO16(0x21) |
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| 296 | #define EEARL _SFR_IO8(0x21) |
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| 297 | #define EEARH _SFR_IO8(0X22) |
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| 298 | |
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| 299 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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| 300 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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| 301 | subroutines. |
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| 302 | First two letters: EECR address. |
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| 303 | Second two letters: EEDR address. |
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| 304 | Last two letters: EEAR address. */ |
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| 305 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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| 306 | |
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| 307 | #define GTCCR _SFR_IO8(0x23) |
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| 308 | #define PSR10 0 |
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| 309 | #define PSR2 1 |
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| 310 | #define TSM 7 |
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| 311 | |
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| 312 | #define TCCR0A _SFR_IO8(0x24) |
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| 313 | #define CS00 0 |
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| 314 | #define CS01 1 |
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| 315 | #define CS02 2 |
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| 316 | #define WGM01 3 |
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| 317 | #define COM0A0 4 |
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| 318 | #define COM0A1 5 |
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| 319 | #define WGM00 6 |
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| 320 | #define FOC0A 7 |
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| 321 | |
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| 322 | /* Reserved [0x25] */ |
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| 323 | |
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| 324 | #define TCNT0 _SFR_IO8(0X26) |
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| 325 | |
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| 326 | #define OCR0A _SFR_IO8(0X27) |
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| 327 | |
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| 328 | /* Reserved [0x28..0x29] */ |
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| 329 | |
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| 330 | #define GPIOR1 _SFR_IO8(0x2A) |
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| 331 | |
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| 332 | #define GPIOR2 _SFR_IO8(0x2B) |
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| 333 | |
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| 334 | #define SPCR _SFR_IO8(0x2C) |
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| 335 | #define SPR0 0 |
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| 336 | #define SPR1 1 |
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| 337 | #define CPHA 2 |
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| 338 | #define CPOL 3 |
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| 339 | #define MSTR 4 |
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| 340 | #define DORD 5 |
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| 341 | #define SPE 6 |
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| 342 | #define SPIE 7 |
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| 343 | |
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| 344 | #define SPSR _SFR_IO8(0x2D) |
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| 345 | #define SPI2X 0 |
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| 346 | #define WCOL 6 |
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| 347 | #define SPIF 7 |
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| 348 | |
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| 349 | #define SPDR _SFR_IO8(0X2E) |
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| 350 | |
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| 351 | /* Reserved [0x2F] */ |
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| 352 | |
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| 353 | #define ACSR _SFR_IO8(0x30) |
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| 354 | #define ACIS0 0 |
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| 355 | #define ACIS1 1 |
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| 356 | #define ACIC 2 |
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| 357 | #define ACIE 3 |
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| 358 | #define ACI 4 |
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| 359 | #define ACO 5 |
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| 360 | #define ACBG 6 |
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| 361 | #define ACD 7 |
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| 362 | |
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| 363 | #define OCDR _SFR_IO8(0x31) |
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| 364 | #define OCDR0 0 |
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| 365 | #define OCDR1 1 |
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| 366 | #define OCDR2 2 |
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| 367 | #define OCDR3 3 |
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| 368 | #define OCDR4 4 |
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| 369 | #define OCDR5 5 |
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| 370 | #define OCDR6 6 |
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| 371 | #define OCDR7 7 |
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| 372 | #define IDRD 7 |
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| 373 | |
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| 374 | /* Reserved [0x32] */ |
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| 375 | |
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| 376 | #define SMCR _SFR_IO8(0x33) |
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| 377 | #define SE 0 |
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| 378 | #define SM0 1 |
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| 379 | #define SM1 2 |
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| 380 | #define SM2 3 |
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| 381 | |
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| 382 | #define MCUSR _SFR_IO8(0x34) |
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| 383 | #define PORF 0 |
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| 384 | #define EXTRF 1 |
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| 385 | #define BORF 2 |
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| 386 | #define WDRF 3 |
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| 387 | #define JTRF 4 |
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| 388 | |
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| 389 | #define MCUCR _SFR_IO8(0X35) |
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| 390 | #define IVCE 0 |
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| 391 | #define IVSEL 1 |
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| 392 | #define PUD 4 |
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| 393 | #if defined(__AVR_ATmega3250P__) |
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| 394 | #define BODSE 5 |
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| 395 | #define BODS 6 |
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| 396 | #endif |
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| 397 | #define JTD 7 |
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| 398 | |
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| 399 | /* Reserved [0x36] */ |
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| 400 | |
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| 401 | #define SPMCSR _SFR_IO8(0x37) |
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| 402 | #define SPMEN 0 |
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| 403 | #define PGERS 1 |
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| 404 | #define PGWRT 2 |
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| 405 | #define BLBSET 3 |
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| 406 | #define RWWSRE 4 |
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| 407 | #define RWWSB 6 |
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| 408 | #define SPMIE 7 |
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| 409 | |
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| 410 | /* Reserved [0x38..0x3C] */ |
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| 411 | |
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| 412 | /* SP [0x3D..0x3E] */ |
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| 413 | /* SREG [0x3F] */ |
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| 414 | |
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| 415 | #define WDTCR _SFR_MEM8(0x60) |
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| 416 | #define WDP0 0 |
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| 417 | #define WDP1 1 |
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| 418 | #define WDP2 2 |
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| 419 | #define WDE 3 |
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| 420 | #define WDCE 4 |
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| 421 | |
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| 422 | #define CLKPR _SFR_MEM8(0x61) |
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| 423 | #define CLKPS0 0 |
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| 424 | #define CLKPS1 1 |
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| 425 | #define CLKPS2 2 |
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| 426 | #define CLKPS3 3 |
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| 427 | #define CLKPCE 7 |
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| 428 | |
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| 429 | /* Reserved [0x62..0x63] */ |
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| 430 | |
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| 431 | #define PRR _SFR_MEM8(0x64) |
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| 432 | #define PRADC 0 |
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| 433 | #define PRUSART0 1 |
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| 434 | #define PRSPI 2 |
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| 435 | #define PRTIM1 3 |
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| 436 | |
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| 437 | /* Reserved [0x65] */ |
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| 438 | |
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| 439 | #define OSCCAL _SFR_MEM8(0x66) |
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| 440 | |
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| 441 | /* Reserved [0x67..0x68] */ |
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| 442 | |
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| 443 | #define EICRA _SFR_MEM8(0x69) |
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| 444 | #define ISC00 0 |
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| 445 | #define ISC01 1 |
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| 446 | |
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| 447 | /* Reserved [0x6A] */ |
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| 448 | |
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| 449 | #define PCMSK0 _SFR_MEM8(0x6B) |
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| 450 | #define PCINT0 0 |
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| 451 | #define PCINT1 1 |
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| 452 | #define PCINT2 2 |
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| 453 | #define PCINT3 3 |
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| 454 | #define PCINT4 4 |
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| 455 | #define PCINT5 5 |
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| 456 | #define PCINT6 6 |
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| 457 | #define PCINT7 7 |
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| 458 | |
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| 459 | #define PCMSK1 _SFR_MEM8(0x6C) |
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| 460 | #define PCINT8 0 |
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| 461 | #define PCINT9 1 |
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| 462 | #define PCINT10 2 |
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| 463 | #define PCINT11 3 |
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| 464 | #define PCINT12 4 |
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| 465 | #define PCINT13 5 |
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| 466 | #define PCINT14 6 |
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| 467 | #define PCINT15 7 |
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| 468 | |
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| 469 | #define PCMSK2 _SFR_MEM8(0x6D) |
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| 470 | #define PCINT16 0 |
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| 471 | #define PCINT17 1 |
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| 472 | #define PCINT18 2 |
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| 473 | #define PCINT19 3 |
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| 474 | #define PCINT20 4 |
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| 475 | #define PCINT21 5 |
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| 476 | #define PCINT22 6 |
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| 477 | #define PCINT23 7 |
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| 478 | |
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| 479 | #define TIMSK0 _SFR_MEM8(0x6E) |
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| 480 | #define TOIE0 0 |
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| 481 | #define OCIE0A 1 |
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| 482 | |
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| 483 | #define TIMSK1 _SFR_MEM8(0x6F) |
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| 484 | #define TOIE1 0 |
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| 485 | #define OCIE1A 1 |
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| 486 | #define OCIE1B 2 |
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| 487 | #define ICIE1 5 |
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| 488 | |
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| 489 | #define TIMSK2 _SFR_MEM8(0x70) |
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| 490 | #define TOIE2 0 |
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| 491 | #define OCIE2A 1 |
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| 492 | |
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| 493 | /* Reserved [0x71..0x72] */ |
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| 494 | |
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| 495 | #define PCMSK3 _SFR_MEM8(0x73) |
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| 496 | #define PCINT24 0 |
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| 497 | #define PCINT25 1 |
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| 498 | #define PCINT26 2 |
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| 499 | #define PCINT27 3 |
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| 500 | #define PCINT28 4 |
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| 501 | #define PCINT29 5 |
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| 502 | #define PCINT30 6 |
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| 503 | |
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| 504 | /* Reserved [0x74..0x77] */ |
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| 505 | |
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| 506 | /* Combine ADCL and ADCH */ |
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| 507 | #ifndef __ASSEMBLER__ |
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| 508 | #define ADC _SFR_MEM16(0x78) |
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| 509 | #endif |
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| 510 | #define ADCW _SFR_MEM16(0x78) |
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| 511 | #define ADCL _SFR_MEM8(0x78) |
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| 512 | #define ADCH _SFR_MEM8(0x79) |
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| 513 | |
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| 514 | #define ADCSRA _SFR_MEM8(0x7A) |
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| 515 | #define ADPS0 0 |
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| 516 | #define ADPS1 1 |
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| 517 | #define ADPS2 2 |
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| 518 | #define ADIE 3 |
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| 519 | #define ADIF 4 |
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| 520 | #define ADATE 5 |
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| 521 | #define ADSC 6 |
---|
| 522 | #define ADEN 7 |
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| 523 | |
---|
| 524 | #define ADCSRB _SFR_MEM8(0x7B) |
---|
| 525 | #define ADTS0 0 |
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| 526 | #define ADTS1 1 |
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| 527 | #define ADTS2 2 |
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| 528 | #define ACME 6 |
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| 529 | |
---|
| 530 | #define ADMUX _SFR_MEM8(0x7C) |
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| 531 | #define MUX0 0 |
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| 532 | #define MUX1 1 |
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| 533 | #define MUX2 2 |
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| 534 | #define MUX3 3 |
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| 535 | #define MUX4 4 |
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| 536 | #define ADLAR 5 |
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| 537 | #define REFS0 6 |
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| 538 | #define REFS1 7 |
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| 539 | |
---|
| 540 | /* Reserved [0x7D] */ |
---|
| 541 | |
---|
| 542 | #define DIDR0 _SFR_MEM8(0x7E) |
---|
| 543 | #define ADC0D 0 |
---|
| 544 | #define ADC1D 1 |
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| 545 | #define ADC2D 2 |
---|
| 546 | #define ADC3D 3 |
---|
| 547 | #define ADC4D 4 |
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| 548 | #define ADC5D 5 |
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| 549 | #define ADC6D 6 |
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| 550 | #define ADC7D 7 |
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| 551 | |
---|
| 552 | #define DIDR1 _SFR_MEM8(0x7F) |
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| 553 | #define AIN0D 0 |
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| 554 | #define AIN1D 1 |
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| 555 | |
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| 556 | #define TCCR1A _SFR_MEM8(0X80) |
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| 557 | #define WGM10 0 |
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| 558 | #define WGM11 1 |
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| 559 | #define COM1B0 4 |
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| 560 | #define COM1B1 5 |
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| 561 | #define COM1A0 6 |
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| 562 | #define COM1A1 7 |
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| 563 | |
---|
| 564 | #define TCCR1B _SFR_MEM8(0X81) |
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| 565 | #define CS10 0 |
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| 566 | #define CS11 1 |
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| 567 | #define CS12 2 |
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| 568 | #define WGM12 3 |
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| 569 | #define WGM13 4 |
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| 570 | #define ICES1 6 |
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| 571 | #define ICNC1 7 |
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| 572 | |
---|
| 573 | #define TCCR1C _SFR_MEM8(0x82) |
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| 574 | #define FOC1B 6 |
---|
| 575 | #define FOC1A 7 |
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| 576 | |
---|
| 577 | /* Reserved [0x83] */ |
---|
| 578 | |
---|
| 579 | /* Combine TCNT1L and TCNT1H */ |
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| 580 | #define TCNT1 _SFR_MEM16(0x84) |
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| 581 | |
---|
| 582 | #define TCNT1L _SFR_MEM8(0x84) |
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| 583 | #define TCNT1H _SFR_MEM8(0x85) |
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| 584 | |
---|
| 585 | /* Combine ICR1L and ICR1H */ |
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| 586 | #define ICR1 _SFR_MEM16(0x86) |
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| 587 | |
---|
| 588 | #define ICR1L _SFR_MEM8(0x86) |
---|
| 589 | #define ICR1H _SFR_MEM8(0x87) |
---|
| 590 | |
---|
| 591 | /* Combine OCR1AL and OCR1AH */ |
---|
| 592 | #define OCR1A _SFR_MEM16(0x88) |
---|
| 593 | |
---|
| 594 | #define OCR1AL _SFR_MEM8(0x88) |
---|
| 595 | #define OCR1AH _SFR_MEM8(0x89) |
---|
| 596 | |
---|
| 597 | /* Combine OCR1BL and OCR1BH */ |
---|
| 598 | #define OCR1B _SFR_MEM16(0x8A) |
---|
| 599 | |
---|
| 600 | #define OCR1BL _SFR_MEM8(0x8A) |
---|
| 601 | #define OCR1BH _SFR_MEM8(0x8B) |
---|
| 602 | |
---|
| 603 | /* Reserved [0x8C..0xAF] */ |
---|
| 604 | |
---|
| 605 | #define TCCR2A _SFR_MEM8(0xB0) |
---|
| 606 | #define CS20 0 |
---|
| 607 | #define CS21 1 |
---|
| 608 | #define CS22 2 |
---|
| 609 | #define WGM21 3 |
---|
| 610 | #define COM2A0 4 |
---|
| 611 | #define COM2A1 5 |
---|
| 612 | #define WGM20 6 |
---|
| 613 | #define FOC2A 7 |
---|
| 614 | |
---|
| 615 | /* Reserved [0xB1] */ |
---|
| 616 | |
---|
| 617 | #define TCNT2 _SFR_MEM8(0xB2) |
---|
| 618 | |
---|
| 619 | #define OCR2A _SFR_MEM8(0xB3) |
---|
| 620 | |
---|
| 621 | /* Reserved [0xB4..0xB5] */ |
---|
| 622 | |
---|
| 623 | #define ASSR _SFR_MEM8(0xB6) |
---|
| 624 | #define TCR2UB 0 |
---|
| 625 | #define OCR2UB 1 |
---|
| 626 | #define TCN2UB 2 |
---|
| 627 | #define AS2 3 |
---|
| 628 | #define EXCLK 4 |
---|
| 629 | |
---|
| 630 | /* Reserved [0xB7] */ |
---|
| 631 | |
---|
| 632 | #define USICR _SFR_MEM8(0xB8) |
---|
| 633 | #define USITC 0 |
---|
| 634 | #define USICLK 1 |
---|
| 635 | #define USICS0 2 |
---|
| 636 | #define USICS1 3 |
---|
| 637 | #define USIWM0 4 |
---|
| 638 | #define USIWM1 5 |
---|
| 639 | #define USIOIE 6 |
---|
| 640 | #define USISIE 7 |
---|
| 641 | |
---|
| 642 | #define USISR _SFR_MEM8(0xB9) |
---|
| 643 | #define USICNT0 0 |
---|
| 644 | #define USICNT1 1 |
---|
| 645 | #define USICNT2 2 |
---|
| 646 | #define USICNT3 3 |
---|
| 647 | #define USIDC 4 |
---|
| 648 | #define USIPF 5 |
---|
| 649 | #define USIOIF 6 |
---|
| 650 | #define USISIF 7 |
---|
| 651 | |
---|
| 652 | #define USIDR _SFR_MEM8(0xBA) |
---|
| 653 | |
---|
| 654 | /* Reserved [0xBB..0xBF] */ |
---|
| 655 | |
---|
| 656 | #define UCSR0A _SFR_MEM8(0xC0) |
---|
| 657 | #define MPCM0 0 |
---|
| 658 | #define U2X0 1 |
---|
| 659 | #define UPE0 2 |
---|
| 660 | #define DOR0 3 |
---|
| 661 | #define FE0 4 |
---|
| 662 | #define UDRE0 5 |
---|
| 663 | #define TXC0 6 |
---|
| 664 | #define RXC0 7 |
---|
| 665 | |
---|
| 666 | #define UCSR0B _SFR_MEM8(0XC1) |
---|
| 667 | #define TXB80 0 |
---|
| 668 | #define RXB80 1 |
---|
| 669 | #define UCSZ02 2 |
---|
| 670 | #define TXEN0 3 |
---|
| 671 | #define RXEN0 4 |
---|
| 672 | #define UDRIE0 5 |
---|
| 673 | #define TXCIE0 6 |
---|
| 674 | #define RXCIE0 7 |
---|
| 675 | |
---|
| 676 | #define UCSR0C _SFR_MEM8(0xC2) |
---|
| 677 | #define UCPOL0 0 |
---|
| 678 | #define UCSZ00 1 |
---|
| 679 | #define UCSZ01 2 |
---|
| 680 | #define USBS0 3 |
---|
| 681 | #define UPM00 4 |
---|
| 682 | #define UPM01 5 |
---|
| 683 | #define UMSEL0 6 |
---|
| 684 | |
---|
| 685 | /* Reserved [0xC3] */ |
---|
| 686 | |
---|
| 687 | /* Combine UBRR0L and UBRR0H */ |
---|
| 688 | #define UBRR0 _SFR_MEM16(0xC4) |
---|
| 689 | |
---|
| 690 | #define UBRR0L _SFR_MEM8(0xC4) |
---|
| 691 | #define UBRR0H _SFR_MEM8(0xC5) |
---|
| 692 | |
---|
| 693 | #define UDR0 _SFR_MEM8(0XC6) |
---|
| 694 | |
---|
| 695 | /* Reserved [0xC7..0xD7] */ |
---|
| 696 | |
---|
| 697 | #define PINH _SFR_MEM8(0xD8) |
---|
| 698 | #define PINH7 7 |
---|
| 699 | #define PINH6 6 |
---|
| 700 | #define PINH5 5 |
---|
| 701 | #define PINH4 4 |
---|
| 702 | #define PINH3 3 |
---|
| 703 | #define PINH2 2 |
---|
| 704 | #define PINH1 1 |
---|
| 705 | #define PINH0 0 |
---|
| 706 | |
---|
| 707 | #define DDRH _SFR_MEM8(0xD9) |
---|
| 708 | #define DDH7 7 |
---|
| 709 | #define DDH6 6 |
---|
| 710 | #define DDH5 5 |
---|
| 711 | #define DDH4 4 |
---|
| 712 | #define DDH3 3 |
---|
| 713 | #define DDH2 2 |
---|
| 714 | #define DDH1 1 |
---|
| 715 | #define DDH0 0 |
---|
| 716 | |
---|
| 717 | #define PORTH _SFR_MEM8(0xDA) |
---|
| 718 | #define PH7 7 |
---|
| 719 | #define PH6 6 |
---|
| 720 | #define PH5 5 |
---|
| 721 | #define PH4 4 |
---|
| 722 | #define PH3 3 |
---|
| 723 | #define PH2 2 |
---|
| 724 | #define PH1 1 |
---|
| 725 | #define PH0 0 |
---|
| 726 | |
---|
| 727 | #define PINJ _SFR_MEM8(0xDB) |
---|
| 728 | #define PINJ6 6 |
---|
| 729 | #define PINJ5 5 |
---|
| 730 | #define PINJ4 4 |
---|
| 731 | #define PINJ3 3 |
---|
| 732 | #define PINJ2 2 |
---|
| 733 | #define PINJ1 1 |
---|
| 734 | #define PINJ0 0 |
---|
| 735 | |
---|
| 736 | #define DDRJ _SFR_MEM8(0xDC) |
---|
| 737 | #define DDJ6 6 |
---|
| 738 | #define DDJ5 5 |
---|
| 739 | #define DDJ4 4 |
---|
| 740 | #define DDJ3 3 |
---|
| 741 | #define DDJ2 2 |
---|
| 742 | #define DDJ1 1 |
---|
| 743 | #define DDJ0 0 |
---|
| 744 | |
---|
| 745 | #define PORTJ _SFR_MEM8(0xDD) |
---|
| 746 | #define PJ6 6 |
---|
| 747 | #define PJ5 5 |
---|
| 748 | #define PJ4 4 |
---|
| 749 | #define PJ3 3 |
---|
| 750 | #define PJ2 2 |
---|
| 751 | #define PJ1 1 |
---|
| 752 | #define PJ0 0 |
---|
| 753 | |
---|
| 754 | /* Reserved [0xDE..0xFF] */ |
---|
| 755 | |
---|
| 756 | |
---|
| 757 | /* Interrupt vectors */ |
---|
| 758 | /* Vector 0 is the reset vector */ |
---|
| 759 | /* External Interrupt Request 0 */ |
---|
| 760 | #define INT0_vect _VECTOR(1) |
---|
| 761 | #define SIG_INTERRUPT0 _VECTOR(1) |
---|
| 762 | |
---|
| 763 | /* Pin Change Interrupt Request 0 */ |
---|
| 764 | #define PCINT0_vect _VECTOR(2) |
---|
| 765 | #define SIG_PIN_CHANGE0 _VECTOR(2) |
---|
| 766 | |
---|
| 767 | /* Pin Change Interrupt Request 1 */ |
---|
| 768 | #define PCINT1_vect _VECTOR(3) |
---|
| 769 | #define SIG_PIN_CHANGE1 _VECTOR(3) |
---|
| 770 | |
---|
| 771 | /* Timer/Counter2 Compare Match */ |
---|
| 772 | #define TIMER2_COMP_vect _VECTOR(4) |
---|
| 773 | #define SIG_OUTPUT_COMPARE2 _VECTOR(4) |
---|
| 774 | |
---|
| 775 | /* Timer/Counter2 Overflow */ |
---|
| 776 | #define TIMER2_OVF_vect _VECTOR(5) |
---|
| 777 | #define SIG_OVERFLOW2 _VECTOR(5) |
---|
| 778 | |
---|
| 779 | /* Timer/Counter1 Capture Event */ |
---|
| 780 | #define TIMER1_CAPT_vect _VECTOR(6) |
---|
| 781 | #define SIG_INPUT_CAPTURE1 _VECTOR(6) |
---|
| 782 | |
---|
| 783 | /* Timer/Counter1 Compare Match A */ |
---|
| 784 | #define TIMER1_COMPA_vect _VECTOR(7) |
---|
| 785 | #define SIG_OUTPUT_COMPARE1A _VECTOR(7) |
---|
| 786 | |
---|
| 787 | /* Timer/Counter Compare Match B */ |
---|
| 788 | #define TIMER1_COMPB_vect _VECTOR(8) |
---|
| 789 | #define SIG_OUTPUT_COMPARE1B _VECTOR(8) |
---|
| 790 | |
---|
| 791 | /* Timer/Counter1 Overflow */ |
---|
| 792 | #define TIMER1_OVF_vect _VECTOR(9) |
---|
| 793 | #define SIG_OVERFLOW1 _VECTOR(9) |
---|
| 794 | |
---|
| 795 | /* Timer/Counter0 Compare Match */ |
---|
| 796 | #define TIMER0_COMP_vect _VECTOR(10) |
---|
| 797 | #define SIG_OUTPUT_COMPARE0 _VECTOR(10) |
---|
| 798 | |
---|
| 799 | /* Timer/Counter0 Overflow */ |
---|
| 800 | #define TIMER0_OVF_vect _VECTOR(11) |
---|
| 801 | #define SIG_OVERFLOW0 _VECTOR(11) |
---|
| 802 | |
---|
| 803 | /* SPI Serial Transfer Complete */ |
---|
| 804 | #define SPI_STC_vect _VECTOR(12) |
---|
| 805 | #define SIG_SPI _VECTOR(12) |
---|
| 806 | |
---|
| 807 | /* USART, Rx Complete */ |
---|
| 808 | #define USART_RX_vect _VECTOR(13) |
---|
| 809 | #define USART0_RX_vect _VECTOR(13) /* Alias */ |
---|
| 810 | #define SIG_UART_RECV _VECTOR(13) |
---|
| 811 | |
---|
| 812 | /* USART Data register Empty */ |
---|
| 813 | #define USART_UDRE_vect _VECTOR(14) |
---|
| 814 | #define USART0_UDRE_vect _VECTOR(14) /* Alias */ |
---|
| 815 | #define SIG_UART_DATA _VECTOR(14) |
---|
| 816 | |
---|
| 817 | /* USART0, Tx Complete */ |
---|
| 818 | #define USART0_TX_vect _VECTOR(15) |
---|
| 819 | #define USART_TX_vect _VECTOR(15) /* Alias */ |
---|
| 820 | #define SIG_UART_TRANS _VECTOR(15) |
---|
| 821 | |
---|
| 822 | /* USI Start Condition */ |
---|
| 823 | #define USI_START_vect _VECTOR(16) |
---|
| 824 | #define SIG_USI_START _VECTOR(16) |
---|
| 825 | |
---|
| 826 | /* USI Overflow */ |
---|
| 827 | #define USI_OVERFLOW_vect _VECTOR(17) |
---|
| 828 | #define SIG_USI_OVERFLOW _VECTOR(17) |
---|
| 829 | |
---|
| 830 | /* Analog Comparator */ |
---|
| 831 | #define ANALOG_COMP_vect _VECTOR(18) |
---|
| 832 | #define SIG_COMPARATOR _VECTOR(18) |
---|
| 833 | |
---|
| 834 | /* ADC Conversion Complete */ |
---|
| 835 | #define ADC_vect _VECTOR(19) |
---|
| 836 | #define SIG_ADC _VECTOR(19) |
---|
| 837 | |
---|
| 838 | /* EEPROM Ready */ |
---|
| 839 | #define EE_READY_vect _VECTOR(20) |
---|
| 840 | #define SIG_EEPROM_READY _VECTOR(20) |
---|
| 841 | |
---|
| 842 | /* Store Program Memory Read */ |
---|
| 843 | #define SPM_READY_vect _VECTOR(21) |
---|
| 844 | #define SIG_SPM_READY _VECTOR(21) |
---|
| 845 | |
---|
| 846 | /* Pin Change Interrupt Request 2 */ |
---|
| 847 | #define PCINT2_vect _VECTOR(23) |
---|
| 848 | #define SIG_PIN_CHANGE2 _VECTOR(23) |
---|
| 849 | |
---|
| 850 | /* Pin Change Interrupt Request 3 */ |
---|
| 851 | #define PCINT3_vect _VECTOR(24) |
---|
| 852 | #define SIG_PIN_CHANGE3 _VECTOR(24) |
---|
| 853 | |
---|
| 854 | #define _VECTORS_SIZE 100 |
---|
| 855 | |
---|
| 856 | |
---|
| 857 | /* Constants */ |
---|
| 858 | #define SPM_PAGESIZE 128 |
---|
| 859 | #define RAMEND 0x8FF |
---|
| 860 | #define XRAMEND RAMEND |
---|
| 861 | #define E2END 0x3FF |
---|
| 862 | #define E2PAGESIZE 4 |
---|
| 863 | #define FLASHEND 0x7FFF |
---|
| 864 | |
---|
| 865 | |
---|
| 866 | /* Fuses */ |
---|
| 867 | |
---|
| 868 | #define FUSE_MEMORY_SIZE 3 |
---|
| 869 | |
---|
| 870 | /* Low Fuse Byte */ |
---|
| 871 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
---|
| 872 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
---|
| 873 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
---|
| 874 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
---|
| 875 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
---|
| 876 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
---|
| 877 | #define FUSE_CKOUT (unsigned char)~_BV(6) |
---|
| 878 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) |
---|
| 879 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
---|
| 880 | |
---|
| 881 | /* High Fuse Byte */ |
---|
| 882 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
---|
| 883 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
---|
| 884 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
---|
| 885 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
---|
| 886 | #define FUSE_WDTON (unsigned char)~_BV(4) |
---|
| 887 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
---|
| 888 | #define FUSE_JTAGEN (unsigned char)~_BV(6) |
---|
| 889 | #define FUSE_OCDEN (unsigned char)~_BV(7) |
---|
| 890 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
---|
| 891 | |
---|
| 892 | /* Extended Fuse Byte */ |
---|
| 893 | #define FUSE_RSTDISBL (unsigned char)~_BV(0) |
---|
| 894 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) |
---|
| 895 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) |
---|
| 896 | #define EFUSE_DEFAULT (0xFF) |
---|
| 897 | |
---|
| 898 | |
---|
| 899 | /* Lock Bits */ |
---|
| 900 | #define __LOCK_BITS_EXIST |
---|
| 901 | #define __BOOT_LOCK_BITS_0_EXIST |
---|
| 902 | #define __BOOT_LOCK_BITS_1_EXIST |
---|
| 903 | |
---|
| 904 | |
---|
| 905 | /* Signature */ |
---|
| 906 | #define SIGNATURE_0 0x1E |
---|
| 907 | #define SIGNATURE_1 0x95 |
---|
| 908 | #define SIGNATURE_2 0x06 |
---|
| 909 | |
---|
| 910 | |
---|
| 911 | #endif /* _AVR_IOM3250_H_ */ |
---|