source: rtems/cpukit/score/cpu/avr/avr/iom323.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 12.7 KB
Line 
1/* Copyright (c) 2002, Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom323.h - definitions for ATmega323 */
34
35#ifndef _AVR_IOM323_H_
36#define _AVR_IOM323_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom323.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
53#define TWBR    _SFR_IO8(0x00)
54#define TWSR    _SFR_IO8(0x01)
55#define TWAR    _SFR_IO8(0x02)
56#define TWDR    _SFR_IO8(0x03)
57
58/* ADC */
59#ifndef __ASSEMBLER__
60#define ADC     _SFR_IO16(0x04)
61#endif
62#define ADCW    _SFR_IO16(0x04)
63#define ADCL    _SFR_IO8(0x04)
64#define ADCH    _SFR_IO8(0x05)
65#define ADCSR   _SFR_IO8(0x06)
66#define ADMUX   _SFR_IO8(0x07)
67
68/* analog comparator */
69#define ACSR    _SFR_IO8(0x08)
70
71/* UART */
72#define UBRR    _SFR_IO8(0x09)
73#define UBRRL   UBRR
74#define UCSRB   _SFR_IO8(0x0A)
75#define UCSRA   _SFR_IO8(0x0B)
76#define UDR     _SFR_IO8(0x0C)
77
78/* SPI */
79#define SPCR    _SFR_IO8(0x0D)
80#define SPSR    _SFR_IO8(0x0E)
81#define SPDR    _SFR_IO8(0x0F)
82
83/* Port D */
84#define PIND    _SFR_IO8(0x10)
85#define DDRD    _SFR_IO8(0x11)
86#define PORTD   _SFR_IO8(0x12)
87
88/* Port C */
89#define PINC    _SFR_IO8(0x13)
90#define DDRC    _SFR_IO8(0x14)
91#define PORTC   _SFR_IO8(0x15)
92
93/* Port B */
94#define PINB    _SFR_IO8(0x16)
95#define DDRB    _SFR_IO8(0x17)
96#define PORTB   _SFR_IO8(0x18)
97
98/* Port A */
99#define PINA    _SFR_IO8(0x19)
100#define DDRA    _SFR_IO8(0x1A)
101#define PORTA   _SFR_IO8(0x1B)
102
103/* EEPROM Control Register */
104#define EECR    _SFR_IO8(0x1C)
105
106/* EEPROM Data Register */
107#define EEDR    _SFR_IO8(0x1D)
108
109/* EEPROM Address Register */
110#define EEAR    _SFR_IO16(0x1E)
111#define EEARL   _SFR_IO8(0x1E)
112#define EEARH   _SFR_IO8(0x1F)
113
114#define UBRRH   _SFR_IO8(0x20)
115#define UCSRC   UBRRH
116
117#define WDTCR   _SFR_IO8(0x21)
118
119#define ASSR    _SFR_IO8(0x22)
120
121/* Timer 2 */
122#define OCR2    _SFR_IO8(0x23)
123#define TCNT2   _SFR_IO8(0x24)
124#define TCCR2   _SFR_IO8(0x25)
125
126/* Timer 1 */
127#define ICR1    _SFR_IO16(0x26)
128#define ICR1L   _SFR_IO8(0x26)
129#define ICR1H   _SFR_IO8(0x27)
130#define OCR1B   _SFR_IO16(0x28)
131#define OCR1BL  _SFR_IO8(0x28)
132#define OCR1BH  _SFR_IO8(0x29)
133#define OCR1A   _SFR_IO16(0x2A)
134#define OCR1AL  _SFR_IO8(0x2A)
135#define OCR1AH  _SFR_IO8(0x2B)
136#define TCNT1   _SFR_IO16(0x2C)
137#define TCNT1L  _SFR_IO8(0x2C)
138#define TCNT1H  _SFR_IO8(0x2D)
139#define TCCR1B  _SFR_IO8(0x2E)
140#define TCCR1A  _SFR_IO8(0x2F)
141
142#define SFIOR   _SFR_IO8(0x30)
143
144#define OSCCAL  _SFR_IO8(0x31)
145
146/* Timer 0 */
147#define TCNT0   _SFR_IO8(0x32)
148#define TCCR0   _SFR_IO8(0x33)
149
150#define MCUSR   _SFR_IO8(0x34)
151#define MCUCSR  MCUSR
152#define MCUCR   _SFR_IO8(0x35)
153
154#define TWCR    _SFR_IO8(0x36)
155
156#define SPMCR   _SFR_IO8(0x37)
157
158#define TIFR    _SFR_IO8(0x38)
159#define TIMSK   _SFR_IO8(0x39)
160
161#define GIFR    _SFR_IO8(0x3A)
162#define GIMSK   _SFR_IO8(0x3B)
163#define GICR    GIMSK
164
165#define OCR0    _SFR_IO8(0x3C)
166
167/* 0x3D..0x3E SP */
168
169/* 0x3F SREG */
170
171/* Interrupt vectors */
172
173/* External Interrupt Request 0 */
174#define INT0_vect                       _VECTOR(1)
175#define SIG_INTERRUPT0                  _VECTOR(1)
176
177/* External Interrupt Request 1 */
178#define INT1_vect                       _VECTOR(2)
179#define SIG_INTERRUPT1                  _VECTOR(2)
180
181/* External Interrupt Request 2 */
182#define INT2_vect                       _VECTOR(3)
183#define SIG_INTERRUPT2                  _VECTOR(3)
184
185/* Timer/Counter2 Compare Match */
186#define TIMER2_COMP_vect                _VECTOR(4)
187#define SIG_OUTPUT_COMPARE2             _VECTOR(4)
188
189/* Timer/Counter2 Overflow */
190#define TIMER2_OVF_vect                 _VECTOR(5)
191#define SIG_OVERFLOW2                   _VECTOR(5)
192
193/* Timer/Counter1 Capture Event */
194#define TIMER1_CAPT_vect                _VECTOR(6)
195#define SIG_INPUT_CAPTURE1              _VECTOR(6)
196
197/* Timer/Counter1 Compare Match A */
198#define TIMER1_COMPA_vect               _VECTOR(7)
199#define SIG_OUTPUT_COMPARE1A            _VECTOR(7)
200
201/* Timer/Counter1 Compare Match B */
202#define TIMER1_COMPB_vect               _VECTOR(8)
203#define SIG_OUTPUT_COMPARE1B            _VECTOR(8)
204
205/* Timer/Counter1 Overflow */
206#define TIMER1_OVF_vect                 _VECTOR(9)
207#define SIG_OVERFLOW1                   _VECTOR(9)
208
209/* Timer/Counter0 Compare Match */
210#define TIMER0_COMP_vect                _VECTOR(10)
211#define SIG_OUTPUT_COMPARE0             _VECTOR(10)
212
213/* Timer/Counter0 Overflow */
214#define TIMER0_OVF_vect                 _VECTOR(11)
215#define SIG_OVERFLOW0                   _VECTOR(11)
216
217/* Serial Transfer Complete */
218#define SPI_STC_vect                    _VECTOR(12)
219#define SIG_SPI                         _VECTOR(12)
220
221/* USART, Rx Complete */
222#define USART_RXC_vect                  _VECTOR(13)
223#define SIG_UART_RECV                   _VECTOR(13)
224
225/* USART Data Register Empty */
226#define USART_UDRE_vect                 _VECTOR(14)
227#define SIG_UART_DATA                   _VECTOR(14)
228
229/* USART, Tx Complete */
230#define USART_TXC_vect                  _VECTOR(15)
231#define SIG_UART_TRANS                  _VECTOR(15)
232
233/* ADC Conversion Complete */
234#define ADC_vect                        _VECTOR(16)
235#define SIG_ADC                         _VECTOR(16)
236
237/* EEPROM Ready */
238#define EE_RDY_vect                     _VECTOR(17)
239#define SIG_EEPROM_READY                _VECTOR(17)
240
241/* Analog Comparator */
242#define ANA_COMP_vect                   _VECTOR(18)
243#define SIG_COMPARATOR                  _VECTOR(18)
244
245/* 2-wire Serial Interface */
246#define TWI_vect                        _VECTOR(19)
247#define SIG_2WIRE_SERIAL                _VECTOR(19)
248
249/* Store Program Memory Ready */
250#define SPM_RDY_vect                    _VECTOR(20)
251
252#define _VECTORS_SIZE 80
253
254
255/* Bit numbers */
256
257/* GIMSK */
258#define INT1    7
259#define INT0    6
260#define INT2    5
261#define IVSEL   1
262#define IVCE    0
263
264/* GIFR */
265#define INTF1   7
266#define INTF0   6
267#define INTF2   5
268
269/* TIMSK */
270#define OCIE2   7
271#define TOIE2   6
272#define TICIE1  5
273#define OCIE1A  4
274#define OCIE1B  3
275#define TOIE1   2
276#define OCIE0   1
277#define TOIE0   0
278
279/* TIFR */
280#define OCF2    7
281#define TOV2    6
282#define ICF1    5
283#define OCF1A   4
284#define OCF1B   3
285#define TOV1    2
286#define OCF0    1
287#define TOV0    0
288
289/* SPMCR */
290#define SPMIE   7
291#define ASB     6
292/* bit 5 reserved */
293#define ASRE    4
294#define BLBSET  3
295#define PGWRT   2
296#define PGERS   1
297#define SPMEN   0
298
299/* TWCR */
300#define TWINT   7
301#define TWEA    6
302#define TWSTA   5
303#define TWSTO   4
304#define TWWC    3
305#define TWEN    2
306#define TWI_TST 1
307#define TWIE    0
308
309/* TWAR */
310#define TWGCE   0
311
312/* TWSR */
313#define    TWS7         7
314#define    TWS6         6
315#define    TWS5         5
316#define    TWS4         4
317#define    TWS3         3
318/* bits 2-0 reserved */
319
320/* MCUCR */
321/* bit 7 reserved (SM2?) */
322#define SE      7
323#define SM2     6
324#define SM1     5
325#define SM0     4
326#define ISC11   3
327#define ISC10   2
328#define ISC01   1
329#define ISC00   0
330
331/* MCUCSR */
332#define JTD     7
333#define ISC2    6
334#define EIH     5
335#define JTRF    4
336#define WDRF    3
337#define BORF    2
338#define EXTRF   1
339#define PORF    0
340
341/* SFIOR */
342#define RPDD    7
343#define RPDC    6
344#define RPDB    5
345#define RPDA    4
346#define ACME    3
347#define PUD     2
348#define PSR2    1
349#define PSR10   0
350
351/* TCCR0 */
352#define FOC0    7
353#define PWM0    6
354#define COM01   5
355#define COM00   4
356#define CTC0    3
357#define CS02    2
358#define CS01    1
359#define CS00    0
360
361/* TCCR2 */
362#define FOC2    7
363#define PWM2    6
364#define COM21   5
365#define COM20   4
366#define CTC2    3
367#define CS22    2
368#define CS21    1
369#define CS20    0
370
371/* ASSR */
372/* bits 7-4 reserved */
373#define AS2     3
374#define TCN2UB  2
375#define OCR2UB  1
376#define TCR2UB  0
377
378/* TCCR1A */
379#define COM1A1  7
380#define COM1A0  6
381#define COM1B1  5
382#define COM1B0  4
383#define FOC1A   3
384#define FOC1B   2
385#define PWM11   1
386#define PWM10   0
387
388/* TCCR1B */
389#define ICNC1   7
390#define ICES1   6
391/* bit 5 reserved */
392#define CTC11   4
393#define CTC10   3
394#define CS12    2
395#define CS11    1
396#define CS10    0
397
398/* WDTCR */
399/* bits 7-5 reserved */
400#define WDTOE   4
401#define WDE     3
402#define WDP2    2
403#define WDP1    1
404#define WDP0    0
405
406/* PA7-PA0 = ADC7-ADC0 */
407/* PORTA */
408#define PA7     7
409#define PA6     6
410#define PA5     5
411#define PA4     4
412#define PA3     3
413#define PA2     2
414#define PA1     1
415#define PA0     0
416
417/* DDRA */
418#define DDA7    7
419#define DDA6    6
420#define DDA5    5
421#define DDA4    4
422#define DDA3    3
423#define DDA2    2
424#define DDA1    1
425#define DDA0    0
426
427/* PINA */
428#define PINA7   7
429#define PINA6   6
430#define PINA5   5
431#define PINA4   4
432#define PINA3   3
433#define PINA2   2
434#define PINA1   1
435#define PINA0   0
436
437/*
438   PB7 = SCK
439   PB6 = MISO
440   PB5 = MOSI
441   PB4 = SS#
442   PB3 = AIN1
443   PB2 = AIN0
444   PB1 = T1
445   PB0 = T0
446 */
447
448/* PORTB */
449#define PB7     7
450#define PB6     6
451#define PB5     5
452#define PB4     4
453#define PB3     3
454#define PB2     2
455#define PB1     1
456#define PB0     0
457
458/* DDRB */
459#define DDB7    7
460#define DDB6    6
461#define DDB5    5
462#define DDB4    4
463#define DDB3    3
464#define DDB2    2
465#define DDB1    1
466#define DDB0    0
467
468/* PINB */
469#define PINB7   7
470#define PINB6   6
471#define PINB5   5
472#define PINB4   4
473#define PINB3   3
474#define PINB2   2
475#define PINB1   1
476#define PINB0   0
477
478/*
479   PC7 = TOSC2
480   PC6 = TOSC1
481   PC1 = SDA
482   PC0 = SCL
483 */
484/* PORTC */
485#define PC7      7
486#define PC6      6
487#define PC5      5
488#define PC4      4
489#define PC3      3
490#define PC2      2
491#define PC1      1
492#define PC0      0
493
494/* DDRC */
495#define DDC7    7
496#define DDC6    6
497#define DDC5    5
498#define DDC4    4
499#define DDC3    3
500#define DDC2    2
501#define DDC1    1
502#define DDC0    0
503
504/* PINC */
505#define PINC7   7
506#define PINC6   6
507#define PINC5   5
508#define PINC4   4
509#define PINC3   3
510#define PINC2   2
511#define PINC1   1
512#define PINC0   0
513
514/*
515   PD7 = OC2
516   PD6 = ICP
517   PD5 = OC1A
518   PD4 = OC1B
519   PD3 = INT1
520   PD2 = INT0
521   PD1 = TXD
522   PD0 = RXD
523 */
524
525/* PORTD */
526#define PD7      7
527#define PD6      6
528#define PD5      5
529#define PD4      4
530#define PD3      3
531#define PD2      2
532#define PD1      1
533#define PD0      0
534
535/* DDRD */
536#define DDD7    7
537#define DDD6    6
538#define DDD5    5
539#define DDD4    4
540#define DDD3    3
541#define DDD2    2
542#define DDD1    1
543#define DDD0    0
544
545/* PIND */
546#define PIND7   7
547#define PIND6   6
548#define PIND5   5
549#define PIND4   4
550#define PIND3   3
551#define PIND2   2
552#define PIND1   1
553#define PIND0   0
554
555/*
556   PE2 = ALE
557   PE1 = OC1B
558   PE0 = ICP / INT2
559 */
560
561/* SPSR */
562#define SPIF    7
563#define WCOL    6
564#define SPI2X   0
565
566/* SPCR */
567#define SPIE    7
568#define SPE     6
569#define DORD    5
570#define MSTR    4
571#define CPOL    3
572#define CPHA    2
573#define SPR1    1
574#define SPR0    0
575
576/* UCSRA */
577#define RXC     7
578#define TXC     6
579#define UDRE    5
580#define FE      4
581#define DOR     3
582#define PE      2
583#define U2X     1
584#define MPCM    0
585
586/* UCSRB */
587#define RXCIE   7
588#define TXCIE   6
589#define UDRIE   5
590#define RXEN    4
591#define TXEN    3
592#define UCSZ2   2
593#define CHR9    2
594#define RXB8    1
595#define TXB8    0
596
597/* UCSRC */
598#define URSEL   7
599#define UMSEL   6
600#define UPM1    5
601#define UPM0    4
602#define USBS    3
603#define UCSZ1   2
604#define UCSZ0   1
605#define UCPOL   0
606
607/* ACSR */
608#define ACD     7
609#define AINBG   6
610#define ACO     5
611#define ACI     4
612#define ACIE    3
613#define ACIC    2
614#define ACIS1   1
615#define ACIS0   0
616
617/* ADCSR */
618#define ADEN    7
619#define ADSC    6
620#define ADFR    5
621#define ADIF    4
622#define ADIE    3
623#define ADPS2   2
624#define ADPS1   1
625#define ADPS0   0
626
627/* ADMUX */
628#define REFS1   7
629#define REFS0   6
630#define ADLAR   5
631#define MUX4    4
632#define MUX3    3
633#define MUX2    2
634#define MUX1    1
635#define MUX0    0
636
637/* EEPROM Control Register */
638#define    EERIE        3
639#define    EEMWE        2
640#define    EEWE         1
641#define    EERE         0
642
643/* Constants */
644#define SPM_PAGESIZE 128
645#define RAMEND          0x85F
646#define XRAMEND         RAMEND
647#define E2END           0x3FF
648#define E2PAGESIZE  0
649#define FLASHEND        0x7FFF
650
651
652/* Fuses */
653
654#define FUSE_MEMORY_SIZE 2
655
656/* Low Fuse Byte */
657#define FUSE_CKSEL0      (unsigned char)~_BV(0)
658#define FUSE_CKSEL1      (unsigned char)~_BV(1)
659#define FUSE_CKSEL2      (unsigned char)~_BV(2)
660#define FUSE_CKSEL3      (unsigned char)~_BV(3)
661#define FUSE_BODEN       (unsigned char)~_BV(6)
662#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
663#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3)
664
665/* High Fuse Byte */
666#define FUSE_BOOTRST     (unsigned char)~_BV(0)
667#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
668#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
669#define FUSE_EESAVE      (unsigned char)~_BV(3)
670#define FUSE_SPIEN       (unsigned char)~_BV(5)
671#define FUSE_JTAGEN      (unsigned char)~_BV(6)
672#define FUSE_OCDEN       (unsigned char)~_BV(7)
673#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_JTAGEN)
674
675
676/* Lock Bits */
677#define __LOCK_BITS_EXIST
678#define __BOOT_LOCK_BITS_0_EXIST
679#define __BOOT_LOCK_BITS_1_EXIST
680
681
682/* Signature */
683#define SIGNATURE_0 0x1E
684#define SIGNATURE_1 0x95
685#define SIGNATURE_2 0x01
686
687
688#endif /* _AVR_IOM323_H_ */
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