[04a62dce] | 1 | /* Copyright (c) 2009 Atmel Corporation |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/iom16u4.h - definitions for ATmega16U4 */ |
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| 34 | |
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| 35 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 36 | |
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| 37 | #ifndef _AVR_IO_H_ |
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| 38 | # error "Include <avr/io.h> instead of this file." |
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| 39 | #endif |
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| 40 | |
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| 41 | #ifndef _AVR_IOXXX_H_ |
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| 42 | # define _AVR_IOXXX_H_ "iom16u4.h" |
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| 43 | #else |
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| 44 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 45 | #endif |
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| 46 | |
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| 47 | |
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| 48 | #ifndef _AVR_ATmega16U4_H_ |
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| 49 | #define _AVR_ATmega16U4_H_ 1 |
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| 50 | |
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| 51 | |
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| 52 | /* Registers and associated bit numbers. */ |
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| 53 | |
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| 54 | #define PINB _SFR_IO8(0x03) |
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| 55 | #define PINB0 0 |
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| 56 | #define PINB1 1 |
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| 57 | #define PINB2 2 |
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| 58 | #define PINB3 3 |
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| 59 | #define PINB4 4 |
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| 60 | #define PINB5 5 |
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| 61 | #define PINB6 6 |
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| 62 | #define PINB7 7 |
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| 63 | |
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| 64 | #define DDRB _SFR_IO8(0x04) |
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| 65 | #define DDB0 0 |
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| 66 | #define DDB1 1 |
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| 67 | #define DDB2 2 |
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| 68 | #define DDB3 3 |
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| 69 | #define DDB4 4 |
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| 70 | #define DDB5 5 |
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| 71 | #define DDB6 6 |
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| 72 | #define DDB7 7 |
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| 73 | |
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| 74 | #define PORTB _SFR_IO8(0x05) |
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| 75 | #define PORTB0 0 |
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| 76 | #define PORTB1 1 |
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| 77 | #define PORTB2 2 |
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| 78 | #define PORTB3 3 |
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| 79 | #define PORTB4 4 |
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| 80 | #define PORTB5 5 |
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| 81 | #define PORTB6 6 |
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| 82 | #define PORTB7 7 |
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| 83 | |
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| 84 | #define PINC _SFR_IO8(0x06) |
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| 85 | #define PINC6 6 |
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| 86 | #define PINC7 7 |
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| 87 | |
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| 88 | #define DDRC _SFR_IO8(0x07) |
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| 89 | #define DDC6 6 |
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| 90 | #define DDC7 7 |
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| 91 | |
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| 92 | #define PORTC _SFR_IO8(0x08) |
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| 93 | #define PORTC6 6 |
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| 94 | #define PORTC7 7 |
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| 95 | |
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| 96 | #define PIND _SFR_IO8(0x09) |
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| 97 | #define PIND0 0 |
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| 98 | #define PIND1 1 |
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| 99 | #define PIND2 2 |
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| 100 | #define PIND3 3 |
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| 101 | #define PIND4 4 |
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| 102 | #define PIND5 5 |
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| 103 | #define PIND6 6 |
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| 104 | #define PIND7 7 |
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| 105 | |
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| 106 | #define DDRD _SFR_IO8(0x0A) |
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| 107 | #define DDD0 0 |
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| 108 | #define DDD1 1 |
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| 109 | #define DDD2 2 |
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| 110 | #define DDD3 3 |
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| 111 | #define DDD4 4 |
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| 112 | #define DDD5 5 |
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| 113 | #define DDD6 6 |
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| 114 | #define DDD7 7 |
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| 115 | |
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| 116 | #define PORTD _SFR_IO8(0x0B) |
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| 117 | #define PORTD0 0 |
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| 118 | #define PORTD1 1 |
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| 119 | #define PORTD2 2 |
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| 120 | #define PORTD3 3 |
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| 121 | #define PORTD4 4 |
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| 122 | #define PORTD5 5 |
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| 123 | #define PORTD6 6 |
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| 124 | #define PORTD7 7 |
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| 125 | |
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| 126 | #define PINE _SFR_IO8(0x0C) |
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| 127 | #define PINE2 2 |
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| 128 | #define PINE6 6 |
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| 129 | |
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| 130 | #define DDRE _SFR_IO8(0x0D) |
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| 131 | #define DDE2 2 |
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| 132 | #define DDE6 6 |
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| 133 | |
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| 134 | #define PORTE _SFR_IO8(0x0E) |
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| 135 | #define PORTE2 2 |
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| 136 | #define PORTE6 6 |
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| 137 | |
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| 138 | #define PINF _SFR_IO8(0x0F) |
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| 139 | #define PINF0 0 |
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| 140 | #define PINF1 1 |
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| 141 | #define PINF4 4 |
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| 142 | #define PINF5 5 |
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| 143 | #define PINF6 6 |
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| 144 | #define PINF7 7 |
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| 145 | |
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| 146 | #define DDRF _SFR_IO8(0x10) |
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| 147 | #define DDF0 0 |
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| 148 | #define DDF1 1 |
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| 149 | #define DDF4 4 |
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| 150 | #define DDF5 5 |
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| 151 | #define DDF6 6 |
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| 152 | #define DDF7 7 |
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| 153 | |
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| 154 | #define PORTF _SFR_IO8(0x11) |
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| 155 | #define PORTF0 0 |
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| 156 | #define PORTF1 1 |
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| 157 | #define PORTF4 4 |
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| 158 | #define PORTF5 5 |
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| 159 | #define PORTF6 6 |
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| 160 | #define PORTF7 7 |
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| 161 | |
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| 162 | #define TIFR0 _SFR_IO8(0x15) |
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| 163 | #define TOV0 0 |
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| 164 | #define OCF0A 1 |
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| 165 | #define OCF0B 2 |
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| 166 | |
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| 167 | #define TIFR1 _SFR_IO8(0x16) |
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| 168 | #define TOV1 0 |
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| 169 | #define OCF1A 1 |
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| 170 | #define OCF1B 2 |
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| 171 | #define OCF1C 3 |
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| 172 | #define ICF1 5 |
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| 173 | |
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| 174 | #define TIFR2 _SFR_IO8(0x17) |
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| 175 | |
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| 176 | #define TIFR3 _SFR_IO8(0x18) |
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| 177 | #define TOV3 0 |
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| 178 | #define OCF3A 1 |
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| 179 | #define OCF3B 2 |
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| 180 | #define OCF3C 3 |
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| 181 | #define ICF3 5 |
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| 182 | |
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| 183 | #define TIFR4 _SFR_IO8(0x19) |
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| 184 | #define TOV4 2 |
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| 185 | #define OCF4B 5 |
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| 186 | #define OCF4A 6 |
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| 187 | #define OCF4D 7 |
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| 188 | |
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| 189 | #define PCIFR _SFR_IO8(0x1B) |
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| 190 | #define PCIF0 0 |
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| 191 | |
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| 192 | #define EIFR _SFR_IO8(0x1C) |
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| 193 | #define INTF0 0 |
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| 194 | #define INTF1 1 |
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| 195 | #define INTF2 2 |
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| 196 | #define INTF3 3 |
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| 197 | #define INTF4 4 |
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| 198 | #define INTF5 5 |
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| 199 | #define INTF6 6 |
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| 200 | #define INTF7 7 |
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| 201 | |
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| 202 | #define EIMSK _SFR_IO8(0x1D) |
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| 203 | #define INT0 0 |
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| 204 | #define INT1 1 |
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| 205 | #define INT2 2 |
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| 206 | #define INT3 3 |
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| 207 | #define INT4 4 |
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| 208 | #define INT5 5 |
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| 209 | #define INT6 6 |
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| 210 | #define INT7 7 |
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| 211 | |
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| 212 | #define GPIOR0 _SFR_IO8(0x1E) |
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| 213 | #define GPIOR00 0 |
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| 214 | #define GPIOR01 1 |
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| 215 | #define GPIOR02 2 |
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| 216 | #define GPIOR03 3 |
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| 217 | #define GPIOR04 4 |
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| 218 | #define GPIOR05 5 |
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| 219 | #define GPIOR06 6 |
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| 220 | #define GPIOR07 7 |
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| 221 | |
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| 222 | #define EECR _SFR_IO8(0x1F) |
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| 223 | #define EERE 0 |
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| 224 | #define EEPE 1 |
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| 225 | #define EEMPE 2 |
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| 226 | #define EERIE 3 |
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| 227 | #define EEPM0 4 |
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| 228 | #define EEPM1 5 |
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| 229 | |
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| 230 | #define EEDR _SFR_IO8(0x20) |
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| 231 | #define EEDR0 0 |
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| 232 | #define EEDR1 1 |
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| 233 | #define EEDR2 2 |
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| 234 | #define EEDR3 3 |
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| 235 | #define EEDR4 4 |
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| 236 | #define EEDR5 5 |
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| 237 | #define EEDR6 6 |
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| 238 | #define EEDR7 7 |
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| 239 | |
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| 240 | #define EEAR _SFR_IO16(0x21) |
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| 241 | |
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| 242 | #define EEARL _SFR_IO8(0x21) |
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| 243 | #define EEAR0 0 |
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| 244 | #define EEAR1 1 |
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| 245 | #define EEAR2 2 |
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| 246 | #define EEAR3 3 |
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| 247 | #define EEAR4 4 |
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| 248 | #define EEAR5 5 |
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| 249 | #define EEAR6 6 |
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| 250 | #define EEAR7 7 |
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| 251 | |
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| 252 | #define EEARH _SFR_IO8(0x22) |
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| 253 | #define EEAR8 0 |
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| 254 | #define EEAR9 1 |
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| 255 | #define EEAR10 2 |
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| 256 | #define EEAR11 3 |
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| 257 | |
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| 258 | #define GTCCR _SFR_IO8(0x23) |
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| 259 | #define PSRSYNC 0 |
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| 260 | #define TSM 7 |
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| 261 | |
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| 262 | #define TCCR0A _SFR_IO8(0x24) |
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| 263 | #define WGM00 0 |
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| 264 | #define WGM01 1 |
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| 265 | #define COM0B0 4 |
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| 266 | #define COM0B1 5 |
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| 267 | #define COM0A0 6 |
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| 268 | #define COM0A1 7 |
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| 269 | |
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| 270 | #define TCCR0B _SFR_IO8(0x25) |
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| 271 | #define CS00 0 |
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| 272 | #define CS01 1 |
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| 273 | #define CS02 2 |
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| 274 | #define WGM02 3 |
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| 275 | #define FOC0B 6 |
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| 276 | #define FOC0A 7 |
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| 277 | |
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| 278 | #define TCNT0 _SFR_IO8(0x26) |
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| 279 | #define TCNT0_0 0 |
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| 280 | #define TCNT0_1 1 |
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| 281 | #define TCNT0_2 2 |
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| 282 | #define TCNT0_3 3 |
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| 283 | #define TCNT0_4 4 |
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| 284 | #define TCNT0_5 5 |
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| 285 | #define TCNT0_6 6 |
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| 286 | #define TCNT0_7 7 |
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| 287 | |
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| 288 | #define OCR0A _SFR_IO8(0x27) |
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| 289 | #define OCROA_0 0 |
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| 290 | #define OCROA_1 1 |
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| 291 | #define OCROA_2 2 |
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| 292 | #define OCROA_3 3 |
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| 293 | #define OCROA_4 4 |
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| 294 | #define OCROA_5 5 |
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| 295 | #define OCROA_6 6 |
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| 296 | #define OCROA_7 7 |
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| 297 | |
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| 298 | #define OCR0B _SFR_IO8(0x28) |
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| 299 | #define OCR0B_0 0 |
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| 300 | #define OCR0B_1 1 |
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| 301 | #define OCR0B_2 2 |
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| 302 | #define OCR0B_3 3 |
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| 303 | #define OCR0B_4 4 |
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| 304 | #define OCR0B_5 5 |
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| 305 | #define OCR0B_6 6 |
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| 306 | #define OCR0B_7 7 |
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| 307 | |
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| 308 | #define PLLCSR _SFR_IO8(0x29) |
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| 309 | #define PLOCK 0 |
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| 310 | #define PLLE 1 |
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| 311 | #define PINDIV 4 |
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| 312 | |
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| 313 | #define GPIOR1 _SFR_IO8(0x2A) |
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| 314 | #define GPIOR10 0 |
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| 315 | #define GPIOR11 1 |
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| 316 | #define GPIOR12 2 |
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| 317 | #define GPIOR13 3 |
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| 318 | #define GPIOR14 4 |
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| 319 | #define GPIOR15 5 |
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| 320 | #define GPIOR16 6 |
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| 321 | #define GPIOR17 7 |
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| 322 | |
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| 323 | #define GPIOR2 _SFR_IO8(0x2B) |
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| 324 | #define GPIOR20 0 |
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| 325 | #define GPIOR21 1 |
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| 326 | #define GPIOR22 2 |
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| 327 | #define GPIOR23 3 |
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| 328 | #define GPIOR24 4 |
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| 329 | #define GPIOR25 5 |
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| 330 | #define GPIOR26 6 |
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| 331 | #define GPIOR27 7 |
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| 332 | |
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| 333 | #define SPCR _SFR_IO8(0x2C) |
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| 334 | #define SPR0 0 |
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| 335 | #define SPR1 1 |
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| 336 | #define CPHA 2 |
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| 337 | #define CPOL 3 |
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| 338 | #define MSTR 4 |
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| 339 | #define DORD 5 |
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| 340 | #define SPE 6 |
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| 341 | #define SPIE 7 |
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| 342 | |
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| 343 | #define SPSR _SFR_IO8(0x2D) |
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| 344 | #define SPI2X 0 |
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| 345 | #define WCOL 6 |
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| 346 | #define SPIF 7 |
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| 347 | |
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| 348 | #define SPDR _SFR_IO8(0x2E) |
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| 349 | #define SPDR0 0 |
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| 350 | #define SPDR1 1 |
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| 351 | #define SPDR2 2 |
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| 352 | #define SPDR3 3 |
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| 353 | #define SPDR4 4 |
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| 354 | #define SPDR5 5 |
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| 355 | #define SPDR6 6 |
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| 356 | #define SPDR7 7 |
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| 357 | |
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| 358 | #define ACSR _SFR_IO8(0x30) |
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| 359 | #define ACIS0 0 |
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| 360 | #define ACIS1 1 |
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| 361 | #define ACIC 2 |
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| 362 | #define ACIE 3 |
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| 363 | #define ACI 4 |
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| 364 | #define ACO 5 |
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| 365 | #define ACBG 6 |
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| 366 | #define ACD 7 |
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| 367 | |
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| 368 | #define OCDR _SFR_IO8(0x31) |
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| 369 | #define OCDR0 0 |
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| 370 | #define OCDR1 1 |
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| 371 | #define OCDR2 2 |
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| 372 | #define OCDR3 3 |
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| 373 | #define OCDR4 4 |
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| 374 | #define OCDR5 5 |
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| 375 | #define OCDR6 6 |
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| 376 | #define OCDR7 7 |
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| 377 | |
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| 378 | #define PLLFRQ _SFR_IO8(0x32) |
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| 379 | #define PDIV0 0 |
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| 380 | #define PDIV1 1 |
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| 381 | #define PDIV2 2 |
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| 382 | #define PDIV3 3 |
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| 383 | #define PLLTM0 4 |
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| 384 | #define PLLTM1 5 |
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| 385 | #define PLLUSB 6 |
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| 386 | #define PINMUX 7 |
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| 387 | |
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| 388 | #define SMCR _SFR_IO8(0x33) |
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| 389 | #define SE 0 |
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| 390 | #define SM0 1 |
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| 391 | #define SM1 2 |
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| 392 | #define SM2 3 |
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| 393 | |
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| 394 | #define MCUSR _SFR_IO8(0x34) |
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| 395 | #define PORF 0 |
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| 396 | #define EXTRF 1 |
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| 397 | #define BORF 2 |
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| 398 | #define WDRF 3 |
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| 399 | #define JTRF 4 |
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| 400 | |
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| 401 | #define MCUCR _SFR_IO8(0x35) |
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| 402 | #define IVCE 0 |
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| 403 | #define IVSEL 1 |
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| 404 | #define PUD 4 |
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| 405 | #define JTD 7 |
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| 406 | |
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| 407 | #define SPMCSR _SFR_IO8(0x37) |
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| 408 | #define SPMEN 0 |
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| 409 | #define PGERS 1 |
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| 410 | #define PGWRT 2 |
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| 411 | #define BLBSET 3 |
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| 412 | #define RWWSRE 4 |
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| 413 | #define SIGRD 5 |
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| 414 | #define RWWSB 6 |
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| 415 | #define SPMIE 7 |
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| 416 | |
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| 417 | #define RAMPZ _SFR_IO8(0x3B) |
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| 418 | #define RAMPZ0 0 |
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| 419 | |
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| 420 | #define EIND _SFR_IO8(0x3C) |
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| 421 | #define EIND0 0 |
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| 422 | |
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| 423 | #define WDTCSR _SFR_MEM8(0x60) |
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| 424 | #define WDP0 0 |
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| 425 | #define WDP1 1 |
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| 426 | #define WDP2 2 |
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| 427 | #define WDE 3 |
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| 428 | #define WDCE 4 |
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| 429 | #define WDP3 5 |
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| 430 | #define WDIE 6 |
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| 431 | #define WDIF 7 |
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| 432 | |
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| 433 | #define CLKPR _SFR_MEM8(0x61) |
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| 434 | #define CLKPS0 0 |
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| 435 | #define CLKPS1 1 |
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| 436 | #define CLKPS2 2 |
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| 437 | #define CLKPS3 3 |
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| 438 | #define CLKPCE 7 |
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| 439 | |
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| 440 | #define PRR0 _SFR_MEM8(0x64) |
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| 441 | #define PRADC 0 |
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| 442 | #define PRUSART0 1 |
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| 443 | #define PRSPI 2 |
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| 444 | #define PRTIM1 3 |
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| 445 | #define PRTIM0 5 |
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| 446 | #define PRTIM2 6 |
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| 447 | #define PRTWI 7 |
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| 448 | |
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| 449 | #define PRR1 _SFR_MEM8(0x65) |
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| 450 | #define PRUSART1 0 |
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| 451 | #define PRTIM3 3 |
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| 452 | #define PRUSB 7 |
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| 453 | |
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| 454 | #define OSCCAL _SFR_MEM8(0x66) |
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| 455 | #define CAL0 0 |
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| 456 | #define CAL1 1 |
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| 457 | #define CAL2 2 |
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| 458 | #define CAL3 3 |
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| 459 | #define CAL4 4 |
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| 460 | #define CAL5 5 |
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| 461 | #define CAL6 6 |
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| 462 | #define CAL7 7 |
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| 463 | |
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| 464 | #define RCCTRL _SFR_MEM8(0x67) |
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| 465 | #define RCFREQ 0 |
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| 466 | |
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| 467 | #define PCICR _SFR_MEM8(0x68) |
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| 468 | #define PCIE0 0 |
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| 469 | |
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| 470 | #define EICRA _SFR_MEM8(0x69) |
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| 471 | #define ISC00 0 |
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| 472 | #define ISC01 1 |
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| 473 | #define ISC10 2 |
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| 474 | #define ISC11 3 |
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| 475 | #define ISC20 4 |
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| 476 | #define ISC21 5 |
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| 477 | #define ISC30 6 |
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| 478 | #define ISC31 7 |
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| 479 | |
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| 480 | #define EICRB _SFR_MEM8(0x6A) |
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| 481 | #define ISC40 0 |
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| 482 | #define ISC41 1 |
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| 483 | #define ISC50 2 |
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| 484 | #define ISC51 3 |
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| 485 | #define ISC60 4 |
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| 486 | #define ISC61 5 |
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| 487 | #define ISC70 6 |
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| 488 | #define ISC71 7 |
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| 489 | |
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| 490 | #define PCMSK0 _SFR_MEM8(0x6B) |
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| 491 | #define PCINT0 0 |
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| 492 | #define PCINT1 1 |
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| 493 | #define PCINT2 2 |
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| 494 | #define PCINT3 3 |
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| 495 | #define PCINT4 4 |
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| 496 | #define PCINT5 5 |
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| 497 | #define PCINT6 6 |
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| 498 | #define PCINT7 7 |
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| 499 | |
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| 500 | #define TIMSK0 _SFR_MEM8(0x6E) |
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| 501 | #define TOIE0 0 |
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| 502 | #define OCIE0A 1 |
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| 503 | #define OCIE0B 2 |
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| 504 | |
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| 505 | #define TIMSK1 _SFR_MEM8(0x6F) |
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| 506 | #define TOIE1 0 |
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| 507 | #define OCIE1A 1 |
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| 508 | #define OCIE1B 2 |
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| 509 | #define OCIE1C 3 |
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| 510 | #define ICIE1 5 |
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| 511 | |
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| 512 | #define TIMSK3 _SFR_MEM8(0x71) |
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| 513 | #define TOIE3 0 |
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| 514 | #define OCIE3A 1 |
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| 515 | #define OCIE3B 2 |
---|
| 516 | #define OCIE3C 3 |
---|
| 517 | #define ICIE3 5 |
---|
| 518 | |
---|
| 519 | #define TIMSK4 _SFR_MEM8(0x72) |
---|
| 520 | #define TOIE4 2 |
---|
| 521 | #define OCIE4B 5 |
---|
| 522 | #define OCIE4A 6 |
---|
| 523 | #define OCIE4D 7 |
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| 524 | |
---|
| 525 | #ifndef __ASSEMBLER__ |
---|
| 526 | #define ADC _SFR_MEM16(0x78) |
---|
| 527 | #endif |
---|
| 528 | #define ADCW _SFR_MEM16(0x78) |
---|
| 529 | |
---|
| 530 | #define ADCL _SFR_MEM8(0x78) |
---|
| 531 | #define ADCL0 0 |
---|
| 532 | #define ADCL1 1 |
---|
| 533 | #define ADCL2 2 |
---|
| 534 | #define ADCL3 3 |
---|
| 535 | #define ADCL4 4 |
---|
| 536 | #define ADCL5 5 |
---|
| 537 | #define ADCL6 6 |
---|
| 538 | #define ADCL7 7 |
---|
| 539 | |
---|
| 540 | #define ADCH _SFR_MEM8(0x79) |
---|
| 541 | #define ADCH0 0 |
---|
| 542 | #define ADCH1 1 |
---|
| 543 | #define ADCH2 2 |
---|
| 544 | #define ADCH3 3 |
---|
| 545 | #define ADCH4 4 |
---|
| 546 | #define ADCH5 5 |
---|
| 547 | #define ADCH6 6 |
---|
| 548 | #define ADCH7 7 |
---|
| 549 | |
---|
| 550 | #define ADCSRA _SFR_MEM8(0x7A) |
---|
| 551 | #define ADPS0 0 |
---|
| 552 | #define ADPS1 1 |
---|
| 553 | #define ADPS2 2 |
---|
| 554 | #define ADIE 3 |
---|
| 555 | #define ADIF 4 |
---|
| 556 | #define ADATE 5 |
---|
| 557 | #define ADSC 6 |
---|
| 558 | #define ADEN 7 |
---|
| 559 | |
---|
| 560 | #define ADCSRB _SFR_MEM8(0x7B) |
---|
| 561 | #define ADTS0 0 |
---|
| 562 | #define ADTS1 1 |
---|
| 563 | #define ADTS2 2 |
---|
| 564 | #define ADTS3 4 |
---|
| 565 | #define MUX5 5 |
---|
| 566 | #define ACME 6 |
---|
| 567 | #define ADHSM 7 |
---|
| 568 | |
---|
| 569 | #define ADMUX _SFR_MEM8(0x7C) |
---|
| 570 | #define MUX0 0 |
---|
| 571 | #define MUX1 1 |
---|
| 572 | #define MUX2 2 |
---|
| 573 | #define MUX3 3 |
---|
| 574 | #define MUX4 4 |
---|
| 575 | #define ADLAR 5 |
---|
| 576 | #define REFS0 6 |
---|
| 577 | #define REFS1 7 |
---|
| 578 | |
---|
| 579 | #define DIDR2 _SFR_MEM8(0x7D) |
---|
| 580 | #define ADC8D 0 |
---|
| 581 | #define ADC9D 1 |
---|
| 582 | #define ADC10D 2 |
---|
| 583 | #define ADC11D 3 |
---|
| 584 | #define ADC12D 4 |
---|
| 585 | #define ADC13D 5 |
---|
| 586 | |
---|
| 587 | #define DIDR0 _SFR_MEM8(0x7E) |
---|
| 588 | #define ADC0D 0 |
---|
| 589 | #define ADC1D 1 |
---|
| 590 | #define ADC2D 2 |
---|
| 591 | #define ADC3D 3 |
---|
| 592 | #define ADC4D 4 |
---|
| 593 | #define ADC5D 5 |
---|
| 594 | #define ADC6D 6 |
---|
| 595 | #define ADC7D 7 |
---|
| 596 | |
---|
| 597 | #define DIDR1 _SFR_MEM8(0x7F) |
---|
| 598 | #define AIN0D 0 |
---|
| 599 | #define AIN1D 1 |
---|
| 600 | |
---|
| 601 | #define TCCR1A _SFR_MEM8(0x80) |
---|
| 602 | #define WGM10 0 |
---|
| 603 | #define WGM11 1 |
---|
| 604 | #define COM1C0 2 |
---|
| 605 | #define COM1C1 3 |
---|
| 606 | #define COM1B0 4 |
---|
| 607 | #define COM1B1 5 |
---|
| 608 | #define COM1A0 6 |
---|
| 609 | #define COM1A1 7 |
---|
| 610 | |
---|
| 611 | #define TCCR1B _SFR_MEM8(0x81) |
---|
| 612 | #define CS10 0 |
---|
| 613 | #define CS11 1 |
---|
| 614 | #define CS12 2 |
---|
| 615 | #define WGM12 3 |
---|
| 616 | #define WGM13 4 |
---|
| 617 | #define ICES1 6 |
---|
| 618 | #define ICNC1 7 |
---|
| 619 | |
---|
| 620 | #define TCCR1C _SFR_MEM8(0x82) |
---|
| 621 | #define FOC1C 5 |
---|
| 622 | #define FOC1B 6 |
---|
| 623 | #define FOC1A 7 |
---|
| 624 | |
---|
| 625 | #define TCNT1 _SFR_MEM16(0x84) |
---|
| 626 | |
---|
| 627 | #define TCNT1L _SFR_MEM8(0x84) |
---|
| 628 | #define TCNT1L0 0 |
---|
| 629 | #define TCNT1L1 1 |
---|
| 630 | #define TCNT1L2 2 |
---|
| 631 | #define TCNT1L3 3 |
---|
| 632 | #define TCNT1L4 4 |
---|
| 633 | #define TCNT1L5 5 |
---|
| 634 | #define TCNT1L6 6 |
---|
| 635 | #define TCNT1L7 7 |
---|
| 636 | |
---|
| 637 | #define TCNT1H _SFR_MEM8(0x85) |
---|
| 638 | #define TCNT1H0 0 |
---|
| 639 | #define TCNT1H1 1 |
---|
| 640 | #define TCNT1H2 2 |
---|
| 641 | #define TCNT1H3 3 |
---|
| 642 | #define TCNT1H4 4 |
---|
| 643 | #define TCNT1H5 5 |
---|
| 644 | #define TCNT1H6 6 |
---|
| 645 | #define TCNT1H7 7 |
---|
| 646 | |
---|
| 647 | #define ICR1 _SFR_MEM16(0x86) |
---|
| 648 | |
---|
| 649 | #define ICR1L _SFR_MEM8(0x86) |
---|
| 650 | #define ICR1L0 0 |
---|
| 651 | #define ICR1L1 1 |
---|
| 652 | #define ICR1L2 2 |
---|
| 653 | #define ICR1L3 3 |
---|
| 654 | #define ICR1L4 4 |
---|
| 655 | #define ICR1L5 5 |
---|
| 656 | #define ICR1L6 6 |
---|
| 657 | #define ICR1L7 7 |
---|
| 658 | |
---|
| 659 | #define ICR1H _SFR_MEM8(0x87) |
---|
| 660 | #define ICR1H0 0 |
---|
| 661 | #define ICR1H1 1 |
---|
| 662 | #define ICR1H2 2 |
---|
| 663 | #define ICR1H3 3 |
---|
| 664 | #define ICR1H4 4 |
---|
| 665 | #define ICR1H5 5 |
---|
| 666 | #define ICR1H6 6 |
---|
| 667 | #define ICR1H7 7 |
---|
| 668 | |
---|
| 669 | #define OCR1A _SFR_MEM16(0x88) |
---|
| 670 | |
---|
| 671 | #define OCR1AL _SFR_MEM8(0x88) |
---|
| 672 | #define OCR1AL0 0 |
---|
| 673 | #define OCR1AL1 1 |
---|
| 674 | #define OCR1AL2 2 |
---|
| 675 | #define OCR1AL3 3 |
---|
| 676 | #define OCR1AL4 4 |
---|
| 677 | #define OCR1AL5 5 |
---|
| 678 | #define OCR1AL6 6 |
---|
| 679 | #define OCR1AL7 7 |
---|
| 680 | |
---|
| 681 | #define OCR1AH _SFR_MEM8(0x89) |
---|
| 682 | #define OCR1AH0 0 |
---|
| 683 | #define OCR1AH1 1 |
---|
| 684 | #define OCR1AH2 2 |
---|
| 685 | #define OCR1AH3 3 |
---|
| 686 | #define OCR1AH4 4 |
---|
| 687 | #define OCR1AH5 5 |
---|
| 688 | #define OCR1AH6 6 |
---|
| 689 | #define OCR1AH7 7 |
---|
| 690 | |
---|
| 691 | #define OCR1B _SFR_MEM16(0x8A) |
---|
| 692 | |
---|
| 693 | #define OCR1BL _SFR_MEM8(0x8A) |
---|
| 694 | #define OCR1BL0 0 |
---|
| 695 | #define OCR1BL1 1 |
---|
| 696 | #define OCR1BL2 2 |
---|
| 697 | #define OCR1BL3 3 |
---|
| 698 | #define OCR1BL4 4 |
---|
| 699 | #define OCR1BL5 5 |
---|
| 700 | #define OCR1BL6 6 |
---|
| 701 | #define OCR1BL7 7 |
---|
| 702 | |
---|
| 703 | #define OCR1BH _SFR_MEM8(0x8B) |
---|
| 704 | #define OCR1BH0 0 |
---|
| 705 | #define OCR1BH1 1 |
---|
| 706 | #define OCR1BH2 2 |
---|
| 707 | #define OCR1BH3 3 |
---|
| 708 | #define OCR1BH4 4 |
---|
| 709 | #define OCR1BH5 5 |
---|
| 710 | #define OCR1BH6 6 |
---|
| 711 | #define OCR1BH7 7 |
---|
| 712 | |
---|
| 713 | #define OCR1C _SFR_MEM16(0x8C) |
---|
| 714 | |
---|
| 715 | #define OCR1CL _SFR_MEM8(0x8C) |
---|
| 716 | #define OCR1CL0 0 |
---|
| 717 | #define OCR1CL1 1 |
---|
| 718 | #define OCR1CL2 2 |
---|
| 719 | #define OCR1CL3 3 |
---|
| 720 | #define OCR1CL4 4 |
---|
| 721 | #define OCR1CL5 5 |
---|
| 722 | #define OCR1CL6 6 |
---|
| 723 | #define OCR1CL7 7 |
---|
| 724 | |
---|
| 725 | #define OCR1CH _SFR_MEM8(0x8D) |
---|
| 726 | #define OCR1CH0 0 |
---|
| 727 | #define OCR1CH1 1 |
---|
| 728 | #define OCR1CH2 2 |
---|
| 729 | #define OCR1CH3 3 |
---|
| 730 | #define OCR1CH4 4 |
---|
| 731 | #define OCR1CH5 5 |
---|
| 732 | #define OCR1CH6 6 |
---|
| 733 | #define OCR1CH7 7 |
---|
| 734 | |
---|
| 735 | #define TCCR3A _SFR_MEM8(0x90) |
---|
| 736 | #define WGM30 0 |
---|
| 737 | #define WGM31 1 |
---|
| 738 | #define COM3C0 2 |
---|
| 739 | #define COM3C1 3 |
---|
| 740 | #define COM3B0 4 |
---|
| 741 | #define COM3B1 5 |
---|
| 742 | #define COM3A0 6 |
---|
| 743 | #define COM3A1 7 |
---|
| 744 | |
---|
| 745 | #define TCCR3B _SFR_MEM8(0x91) |
---|
| 746 | #define CS30 0 |
---|
| 747 | #define CS31 1 |
---|
| 748 | #define CS32 2 |
---|
| 749 | #define WGM32 3 |
---|
| 750 | #define WGM33 4 |
---|
| 751 | #define ICES3 6 |
---|
| 752 | #define ICNC3 7 |
---|
| 753 | |
---|
| 754 | #define TCCR3C _SFR_MEM8(0x92) |
---|
| 755 | #define FOC3C 5 |
---|
| 756 | #define FOC3B 6 |
---|
| 757 | #define FOC3A 7 |
---|
| 758 | |
---|
| 759 | #define TCNT3 _SFR_MEM16(0x94) |
---|
| 760 | |
---|
| 761 | #define TCNT3L _SFR_MEM8(0x94) |
---|
| 762 | #define TCNT3L0 0 |
---|
| 763 | #define TCNT3L1 1 |
---|
| 764 | #define TCNT3L2 2 |
---|
| 765 | #define TCNT3L3 3 |
---|
| 766 | #define TCNT3L4 4 |
---|
| 767 | #define TCNT3L5 5 |
---|
| 768 | #define TCNT3L6 6 |
---|
| 769 | #define TCNT3L7 7 |
---|
| 770 | |
---|
| 771 | #define TCNT3H _SFR_MEM8(0x95) |
---|
| 772 | #define TCNT3H0 0 |
---|
| 773 | #define TCNT3H1 1 |
---|
| 774 | #define TCNT3H2 2 |
---|
| 775 | #define TCNT3H3 3 |
---|
| 776 | #define TCNT3H4 4 |
---|
| 777 | #define TCNT3H5 5 |
---|
| 778 | #define TCNT3H6 6 |
---|
| 779 | #define TCNT3H7 7 |
---|
| 780 | |
---|
| 781 | #define ICR3 _SFR_MEM16(0x96) |
---|
| 782 | |
---|
| 783 | #define ICR3L _SFR_MEM8(0x96) |
---|
| 784 | #define ICR3L0 0 |
---|
| 785 | #define ICR3L1 1 |
---|
| 786 | #define ICR3L2 2 |
---|
| 787 | #define ICR3L3 3 |
---|
| 788 | #define ICR3L4 4 |
---|
| 789 | #define ICR3L5 5 |
---|
| 790 | #define ICR3L6 6 |
---|
| 791 | #define ICR3L7 7 |
---|
| 792 | |
---|
| 793 | #define ICR3H _SFR_MEM8(0x97) |
---|
| 794 | #define ICR3H0 0 |
---|
| 795 | #define ICR3H1 1 |
---|
| 796 | #define ICR3H2 2 |
---|
| 797 | #define ICR3H3 3 |
---|
| 798 | #define ICR3H4 4 |
---|
| 799 | #define ICR3H5 5 |
---|
| 800 | #define ICR3H6 6 |
---|
| 801 | #define ICR3H7 7 |
---|
| 802 | |
---|
| 803 | #define OCR3A _SFR_MEM16(0x98) |
---|
| 804 | |
---|
| 805 | #define OCR3AL _SFR_MEM8(0x98) |
---|
| 806 | #define OCR3AL0 0 |
---|
| 807 | #define OCR3AL1 1 |
---|
| 808 | #define OCR3AL2 2 |
---|
| 809 | #define OCR3AL3 3 |
---|
| 810 | #define OCR3AL4 4 |
---|
| 811 | #define OCR3AL5 5 |
---|
| 812 | #define OCR3AL6 6 |
---|
| 813 | #define OCR3AL7 7 |
---|
| 814 | |
---|
| 815 | #define OCR3AH _SFR_MEM8(0x99) |
---|
| 816 | #define OCR3AH0 0 |
---|
| 817 | #define OCR3AH1 1 |
---|
| 818 | #define OCR3AH2 2 |
---|
| 819 | #define OCR3AH3 3 |
---|
| 820 | #define OCR3AH4 4 |
---|
| 821 | #define OCR3AH5 5 |
---|
| 822 | #define OCR3AH6 6 |
---|
| 823 | #define OCR3AH7 7 |
---|
| 824 | |
---|
| 825 | #define OCR3B _SFR_MEM16(0x9A) |
---|
| 826 | |
---|
| 827 | #define OCR3BL _SFR_MEM8(0x9A) |
---|
| 828 | #define OCR3BL0 0 |
---|
| 829 | #define OCR3BL1 1 |
---|
| 830 | #define OCR3BL2 2 |
---|
| 831 | #define OCR3BL3 3 |
---|
| 832 | #define OCR3BL4 4 |
---|
| 833 | #define OCR3BL5 5 |
---|
| 834 | #define OCR3BL6 6 |
---|
| 835 | #define OCR3BL7 7 |
---|
| 836 | |
---|
| 837 | #define OCR3BH _SFR_MEM8(0x9B) |
---|
| 838 | #define OCR3BH0 0 |
---|
| 839 | #define OCR3BH1 1 |
---|
| 840 | #define OCR3BH2 2 |
---|
| 841 | #define OCR3BH3 3 |
---|
| 842 | #define OCR3BH4 4 |
---|
| 843 | #define OCR3BH5 5 |
---|
| 844 | #define OCR3BH6 6 |
---|
| 845 | #define OCR3BH7 7 |
---|
| 846 | |
---|
| 847 | #define OCR3C _SFR_MEM16(0x9C) |
---|
| 848 | |
---|
| 849 | #define OCR3CL _SFR_MEM8(0x9C) |
---|
| 850 | #define OCR3CL0 0 |
---|
| 851 | #define OCR3CL1 1 |
---|
| 852 | #define OCR3CL2 2 |
---|
| 853 | #define OCR3CL3 3 |
---|
| 854 | #define OCR3CL4 4 |
---|
| 855 | #define OCR3CL5 5 |
---|
| 856 | #define OCR3CL6 6 |
---|
| 857 | #define OCR3CL7 7 |
---|
| 858 | |
---|
| 859 | #define OCR3CH _SFR_MEM8(0x9D) |
---|
| 860 | #define OCR3CH0 0 |
---|
| 861 | #define OCR3CH1 1 |
---|
| 862 | #define OCR3CH2 2 |
---|
| 863 | #define OCR3CH3 3 |
---|
| 864 | #define OCR3CH4 4 |
---|
| 865 | #define OCR3CH5 5 |
---|
| 866 | #define OCR3CH6 6 |
---|
| 867 | #define OCR3CH7 7 |
---|
| 868 | |
---|
| 869 | #define TCNT4 _SFR_MEM8(0xBE) |
---|
| 870 | #define TC40 0 |
---|
| 871 | #define TC41 1 |
---|
| 872 | #define TC42 2 |
---|
| 873 | #define TC43 3 |
---|
| 874 | #define TC44 4 |
---|
| 875 | #define TC45 5 |
---|
| 876 | #define TC46 6 |
---|
| 877 | #define TC47 7 |
---|
| 878 | |
---|
| 879 | #define TC4H _SFR_MEM8(0xBF) |
---|
| 880 | #define TC48 0 |
---|
| 881 | #define TC49 1 |
---|
| 882 | #define TC410 2 |
---|
| 883 | |
---|
| 884 | #define TCCR4A _SFR_MEM8(0xC0) |
---|
| 885 | #define PWM4B 0 |
---|
| 886 | #define PWM4A 1 |
---|
| 887 | #define FOC4B 2 |
---|
| 888 | #define FOC4A 3 |
---|
| 889 | #define COM4B0 4 |
---|
| 890 | #define COM4B1 5 |
---|
| 891 | #define COM4A0 6 |
---|
| 892 | #define COM4A1 7 |
---|
| 893 | |
---|
| 894 | #define TCCR4B _SFR_MEM8(0xC1) |
---|
| 895 | #define CS40 0 |
---|
| 896 | #define CS41 1 |
---|
| 897 | #define CS42 2 |
---|
| 898 | #define CS43 3 |
---|
| 899 | #define DTPS40 4 |
---|
| 900 | #define DTPS41 5 |
---|
| 901 | #define PSR4 6 |
---|
| 902 | #define PWM4X 7 |
---|
| 903 | |
---|
| 904 | #define TCCR4C _SFR_MEM8(0xC2) |
---|
| 905 | #define PWM4D 0 |
---|
| 906 | #define FOC4D 1 |
---|
| 907 | #define COM4D0 2 |
---|
| 908 | #define COM4D1 3 |
---|
| 909 | #define COM4B0S 4 |
---|
| 910 | #define COM4B1S 5 |
---|
| 911 | #define COM4A0S 6 |
---|
| 912 | #define COM4A1S 7 |
---|
| 913 | |
---|
| 914 | #define TCCR4D _SFR_MEM8(0xC3) |
---|
| 915 | #define WGM40 0 |
---|
| 916 | #define WGM41 1 |
---|
| 917 | #define FPF4 2 |
---|
| 918 | #define FPAC4 3 |
---|
| 919 | #define FPES4 4 |
---|
| 920 | #define FPNC4 5 |
---|
| 921 | #define FPEN4 6 |
---|
| 922 | #define FPIE4 7 |
---|
| 923 | |
---|
| 924 | #define TCCR4E _SFR_MEM8(0xC4) |
---|
| 925 | #define OC4OE0 0 |
---|
| 926 | #define OC4OE1 1 |
---|
| 927 | #define OC4OE2 2 |
---|
| 928 | #define OC4OE3 3 |
---|
| 929 | #define OC4OE4 4 |
---|
| 930 | #define OC4OE5 5 |
---|
| 931 | #define ENHC4 6 |
---|
| 932 | #define TLOCK4 7 |
---|
| 933 | |
---|
| 934 | #define CLKSEL0 _SFR_MEM8(0xC5) |
---|
| 935 | #define CLKS 0 |
---|
| 936 | #define EXTE 2 |
---|
| 937 | #define RCE 3 |
---|
| 938 | #define EXSUT0 4 |
---|
| 939 | #define EXSUT1 5 |
---|
| 940 | #define RCSUT0 6 |
---|
| 941 | #define RCSUT1 7 |
---|
| 942 | |
---|
| 943 | #define CLKSEL1 _SFR_MEM8(0xC6) |
---|
| 944 | #define EXCKSEL0 0 |
---|
| 945 | #define EXCKSEL1 1 |
---|
| 946 | #define EXCKSEL2 2 |
---|
| 947 | #define EXCKSEL3 3 |
---|
| 948 | #define RCCKSEL0 4 |
---|
| 949 | #define RCCKSEL1 5 |
---|
| 950 | #define RCCKSEL2 6 |
---|
| 951 | #define RCCKSEL3 7 |
---|
| 952 | |
---|
| 953 | #define CLKSTA _SFR_MEM8(0xC7) |
---|
| 954 | #define EXTON 0 |
---|
| 955 | #define RCON 1 |
---|
| 956 | |
---|
| 957 | #define UCSR1A _SFR_MEM8(0xC8) |
---|
| 958 | #define MPCM1 0 |
---|
| 959 | #define U2X1 1 |
---|
| 960 | #define UPE1 2 |
---|
| 961 | #define DOR1 3 |
---|
| 962 | #define FE1 4 |
---|
| 963 | #define UDRE1 5 |
---|
| 964 | #define TXC1 6 |
---|
| 965 | #define RXC1 7 |
---|
| 966 | |
---|
| 967 | #define UCSR1B _SFR_MEM8(0xC9) |
---|
| 968 | #define TXB81 0 |
---|
| 969 | #define RXB81 1 |
---|
| 970 | #define UCSZ12 2 |
---|
| 971 | #define TXEN1 3 |
---|
| 972 | #define RXEN1 4 |
---|
| 973 | #define UDRIE1 5 |
---|
| 974 | #define TXCIE1 6 |
---|
| 975 | #define RXCIE1 7 |
---|
| 976 | |
---|
| 977 | #define UCSR1C _SFR_MEM8(0xCA) |
---|
| 978 | #define UCPOL1 0 |
---|
| 979 | #define UCSZ10 1 |
---|
| 980 | #define UCSZ11 2 |
---|
| 981 | #define USBS1 3 |
---|
| 982 | #define UPM10 4 |
---|
| 983 | #define UPM11 5 |
---|
| 984 | #define UMSEL10 6 |
---|
| 985 | #define UMSEL11 7 |
---|
| 986 | |
---|
| 987 | #define UBRR1 _SFR_MEM16(0xCC) |
---|
| 988 | |
---|
| 989 | #define UBRR1L _SFR_MEM8(0xCC) |
---|
| 990 | |
---|
| 991 | #define UBRR1H _SFR_MEM8(0xCD) |
---|
| 992 | |
---|
| 993 | #define UDR1 _SFR_MEM8(0xCE) |
---|
| 994 | #define UDR1_0 0 |
---|
| 995 | #define UDR1_1 1 |
---|
| 996 | #define UDR1_2 2 |
---|
| 997 | #define UDR1_3 3 |
---|
| 998 | #define UDR1_4 4 |
---|
| 999 | #define UDR1_5 5 |
---|
| 1000 | #define UDR1_6 6 |
---|
| 1001 | #define UDR1_7 7 |
---|
| 1002 | |
---|
| 1003 | #define OCR4A _SFR_MEM8(0xCF) |
---|
| 1004 | #define OCR4A0 0 |
---|
| 1005 | #define OCR4A1 1 |
---|
| 1006 | #define OCR4A2 2 |
---|
| 1007 | #define OCR4A3 3 |
---|
| 1008 | #define OCR4A4 4 |
---|
| 1009 | #define OCR4A5 5 |
---|
| 1010 | #define OCR4A6 6 |
---|
| 1011 | #define OCR4A7 7 |
---|
| 1012 | |
---|
| 1013 | #define OCR4B _SFR_MEM8(0xD0) |
---|
| 1014 | #define OCR4B0 0 |
---|
| 1015 | #define OCR4B1 1 |
---|
| 1016 | #define OCR4B2 2 |
---|
| 1017 | #define OCR4B3 3 |
---|
| 1018 | #define OCR4B4 4 |
---|
| 1019 | #define OCR4B5 5 |
---|
| 1020 | #define OCR4B6 6 |
---|
| 1021 | #define OCR4B7 7 |
---|
| 1022 | |
---|
| 1023 | #define OCR4C _SFR_MEM8(0xD1) |
---|
| 1024 | #define OCR4C0 0 |
---|
| 1025 | #define OCR4C1 1 |
---|
| 1026 | #define OCR4C2 2 |
---|
| 1027 | #define OCR4C3 3 |
---|
| 1028 | #define OCR4C4 4 |
---|
| 1029 | #define OCR4C5 5 |
---|
| 1030 | #define OCR4C6 6 |
---|
| 1031 | #define OCR4C7 7 |
---|
| 1032 | |
---|
| 1033 | #define OCR4D _SFR_MEM8(0xD2) |
---|
| 1034 | #define OCR4D0 0 |
---|
| 1035 | #define OCR4D1 1 |
---|
| 1036 | #define OCR4D2 2 |
---|
| 1037 | #define OCR4D3 3 |
---|
| 1038 | #define OCR4D4 4 |
---|
| 1039 | #define OCR4D5 5 |
---|
| 1040 | #define OCR4D6 6 |
---|
| 1041 | #define OCR4D7 7 |
---|
| 1042 | |
---|
| 1043 | #define DT4 _SFR_MEM8(0xD4) |
---|
| 1044 | #define DT4L0 0 |
---|
| 1045 | #define DT4L1 1 |
---|
| 1046 | #define DT4L2 2 |
---|
| 1047 | #define DT4L3 3 |
---|
| 1048 | #define DT4L4 4 |
---|
| 1049 | #define DT4L5 5 |
---|
| 1050 | #define DT4L6 6 |
---|
| 1051 | #define DT4L7 7 |
---|
| 1052 | |
---|
| 1053 | #define UHWCON _SFR_MEM8(0xD7) |
---|
| 1054 | #define UVREGE 0 |
---|
| 1055 | |
---|
| 1056 | #define USBCON _SFR_MEM8(0xD8) |
---|
| 1057 | #define VBUSTE 0 |
---|
| 1058 | #define OTGPADE 4 |
---|
| 1059 | #define FRZCLK 5 |
---|
| 1060 | #define USBE 7 |
---|
| 1061 | |
---|
| 1062 | #define USBSTA _SFR_MEM8(0xD9) |
---|
| 1063 | #define VBUS 0 |
---|
| 1064 | #define SPEED 3 |
---|
| 1065 | |
---|
| 1066 | #define USBINT _SFR_MEM8(0xDA) |
---|
| 1067 | #define VBUSTI 0 |
---|
| 1068 | |
---|
| 1069 | #define UDCON _SFR_MEM8(0xE0) |
---|
| 1070 | #define DETACH 0 |
---|
| 1071 | #define RMWKUP 1 |
---|
| 1072 | #define LSM 2 |
---|
| 1073 | #define RSTCPU 3 |
---|
| 1074 | |
---|
| 1075 | #define UDINT _SFR_MEM8(0xE1) |
---|
| 1076 | #define SUSPI 0 |
---|
| 1077 | #define SOFI 2 |
---|
| 1078 | #define EORSTI 3 |
---|
| 1079 | #define WAKEUPI 4 |
---|
| 1080 | #define EORSMI 5 |
---|
| 1081 | #define UPRSMI 6 |
---|
| 1082 | |
---|
| 1083 | #define UDIEN _SFR_MEM8(0xE2) |
---|
| 1084 | #define SUSPE 0 |
---|
| 1085 | #define SOFE 2 |
---|
| 1086 | #define EORSTE 3 |
---|
| 1087 | #define WAKEUPE 4 |
---|
| 1088 | #define EORSME 5 |
---|
| 1089 | #define UPRSME 6 |
---|
| 1090 | |
---|
| 1091 | #define UDADDR _SFR_MEM8(0xE3) |
---|
| 1092 | #define UADD0 0 |
---|
| 1093 | #define UADD1 1 |
---|
| 1094 | #define UADD2 2 |
---|
| 1095 | #define UADD3 3 |
---|
| 1096 | #define UADD4 4 |
---|
| 1097 | #define UADD5 5 |
---|
| 1098 | #define UADD6 6 |
---|
| 1099 | #define ADDEN 7 |
---|
| 1100 | |
---|
| 1101 | #define UDFNUM _SFR_MEM16(0xE4) |
---|
| 1102 | |
---|
| 1103 | #define UDFNUML _SFR_MEM8(0xE4) |
---|
| 1104 | #define FNUM0 0 |
---|
| 1105 | #define FNUM1 1 |
---|
| 1106 | #define FNUM2 2 |
---|
| 1107 | #define FNUM3 3 |
---|
| 1108 | #define FNUM4 4 |
---|
| 1109 | #define FNUM5 5 |
---|
| 1110 | #define FNUM6 6 |
---|
| 1111 | #define FNUM7 7 |
---|
| 1112 | |
---|
| 1113 | #define UDFNUMH _SFR_MEM8(0xE5) |
---|
| 1114 | #define FNUM8 0 |
---|
| 1115 | #define FNUM9 1 |
---|
| 1116 | #define FNUM10 2 |
---|
| 1117 | |
---|
| 1118 | #define UDMFN _SFR_MEM8(0xE6) |
---|
| 1119 | #define FNCERR 4 |
---|
| 1120 | |
---|
| 1121 | #define UEINTX _SFR_MEM8(0xE8) |
---|
| 1122 | #define TXINI 0 |
---|
| 1123 | #define STALLEDI 1 |
---|
| 1124 | #define RXOUTI 2 |
---|
| 1125 | #define RXSTPI 3 |
---|
| 1126 | #define NAKOUTI 4 |
---|
| 1127 | #define RWAL 5 |
---|
| 1128 | #define NAKINI 6 |
---|
| 1129 | #define FIFOCON 7 |
---|
| 1130 | |
---|
| 1131 | #define UENUM _SFR_MEM8(0xE9) |
---|
| 1132 | #define UENUM_0 0 |
---|
| 1133 | #define UENUM_1 1 |
---|
| 1134 | #define UENUM_2 2 |
---|
| 1135 | |
---|
| 1136 | #define UERST _SFR_MEM8(0xEA) |
---|
| 1137 | #define EPRST0 0 |
---|
| 1138 | #define EPRST1 1 |
---|
| 1139 | #define EPRST2 2 |
---|
| 1140 | #define EPRST3 3 |
---|
| 1141 | #define EPRST4 4 |
---|
| 1142 | #define EPRST5 5 |
---|
| 1143 | #define EPRST6 6 |
---|
| 1144 | |
---|
| 1145 | #define UECONX _SFR_MEM8(0xEB) |
---|
| 1146 | #define EPEN 0 |
---|
| 1147 | #define RSTDT 3 |
---|
| 1148 | #define STALLRQC 4 |
---|
| 1149 | #define STALLRQ 5 |
---|
| 1150 | |
---|
| 1151 | #define UECFG0X _SFR_MEM8(0xEC) |
---|
| 1152 | #define EPDIR 0 |
---|
| 1153 | #define EPTYPE0 6 |
---|
| 1154 | #define EPTYPE1 7 |
---|
| 1155 | |
---|
| 1156 | #define UECFG1X _SFR_MEM8(0xED) |
---|
| 1157 | #define ALLOC 1 |
---|
| 1158 | #define EPBK0 2 |
---|
| 1159 | #define EPBK1 3 |
---|
| 1160 | #define EPSIZE0 4 |
---|
| 1161 | #define EPSIZE1 5 |
---|
| 1162 | #define EPSIZE2 6 |
---|
| 1163 | |
---|
| 1164 | #define UESTA0X _SFR_MEM8(0xEE) |
---|
| 1165 | #define NBUSYBK0 0 |
---|
| 1166 | #define NBUSYBK1 1 |
---|
| 1167 | #define DTSEQ0 2 |
---|
| 1168 | #define DTSEQ1 3 |
---|
| 1169 | #define UNDERFI 5 |
---|
| 1170 | #define OVERFI 6 |
---|
| 1171 | #define CFGOK 7 |
---|
| 1172 | |
---|
| 1173 | #define UESTA1X _SFR_MEM8(0xEF) |
---|
| 1174 | #define CURRBK0 0 |
---|
| 1175 | #define CURRBK1 1 |
---|
| 1176 | #define CTRLDIR 2 |
---|
| 1177 | |
---|
| 1178 | #define UEIENX _SFR_MEM8(0xF0) |
---|
| 1179 | #define TXINE 0 |
---|
| 1180 | #define STALLEDE 1 |
---|
| 1181 | #define RXOUTE 2 |
---|
| 1182 | #define RXSTPE 3 |
---|
| 1183 | #define NAKOUTE 4 |
---|
| 1184 | #define NAKINE 6 |
---|
| 1185 | #define FLERRE 7 |
---|
| 1186 | |
---|
| 1187 | #define UEDATX _SFR_MEM8(0xF1) |
---|
| 1188 | #define DAT0 0 |
---|
| 1189 | #define DAT1 1 |
---|
| 1190 | #define DAT2 2 |
---|
| 1191 | #define DAT3 3 |
---|
| 1192 | #define DAT4 4 |
---|
| 1193 | #define DAT5 5 |
---|
| 1194 | #define DAT6 6 |
---|
| 1195 | #define DAT7 7 |
---|
| 1196 | |
---|
| 1197 | #define UEBCLX _SFR_MEM8(0xF2) |
---|
| 1198 | #define BYCT0 0 |
---|
| 1199 | #define BYCT1 1 |
---|
| 1200 | #define BYCT2 2 |
---|
| 1201 | #define BYCT3 3 |
---|
| 1202 | #define BYCT4 4 |
---|
| 1203 | #define BYCT5 5 |
---|
| 1204 | #define BYCT6 6 |
---|
| 1205 | #define BYCT7 7 |
---|
| 1206 | |
---|
| 1207 | #define UEBCHX _SFR_MEM8(0xF3) |
---|
| 1208 | |
---|
| 1209 | #define UEINT _SFR_MEM8(0xF4) |
---|
| 1210 | #define EPINT0 0 |
---|
| 1211 | #define EPINT1 1 |
---|
| 1212 | #define EPINT2 2 |
---|
| 1213 | #define EPINT3 3 |
---|
| 1214 | #define EPINT4 4 |
---|
| 1215 | #define EPINT5 5 |
---|
| 1216 | #define EPINT6 6 |
---|
| 1217 | |
---|
| 1218 | |
---|
| 1219 | /* Interrupt vectors */ |
---|
| 1220 | /* Vector 0 is the reset vector */ |
---|
| 1221 | #define INT0_vect_num 1 |
---|
| 1222 | #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ |
---|
| 1223 | #define INT1_vect_num 2 |
---|
| 1224 | #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ |
---|
| 1225 | #define INT2_vect_num 3 |
---|
| 1226 | #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ |
---|
| 1227 | #define INT3_vect_num 4 |
---|
| 1228 | #define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ |
---|
| 1229 | #define INT6_vect_num 7 |
---|
| 1230 | #define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ |
---|
| 1231 | #define PCINT0_vect_num 9 |
---|
| 1232 | #define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ |
---|
| 1233 | #define USB_GEN_vect_num 10 |
---|
| 1234 | #define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ |
---|
| 1235 | #define USB_COM_vect_num 11 |
---|
| 1236 | #define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ |
---|
| 1237 | #define WDT_vect_num 12 |
---|
| 1238 | #define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ |
---|
| 1239 | #define TIMER1_CAPT_vect_num 16 |
---|
| 1240 | #define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ |
---|
| 1241 | #define TIMER1_COMPA_vect_num 17 |
---|
| 1242 | #define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ |
---|
| 1243 | #define TIMER1_COMPB_vect_num 18 |
---|
| 1244 | #define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ |
---|
| 1245 | #define TIMER1_COMPC_vect_num 19 |
---|
| 1246 | #define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ |
---|
| 1247 | #define TIMER1_OVF_vect_num 20 |
---|
| 1248 | #define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ |
---|
| 1249 | #define TIMER0_COMPA_vect_num 21 |
---|
| 1250 | #define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ |
---|
| 1251 | #define TIMER0_COMPB_vect_num 22 |
---|
| 1252 | #define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ |
---|
| 1253 | #define TIMER0_OVF_vect_num 23 |
---|
| 1254 | #define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ |
---|
| 1255 | #define SPI_STC_vect_num 24 |
---|
| 1256 | #define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ |
---|
| 1257 | #define USART1_RX_vect_num 25 |
---|
| 1258 | #define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ |
---|
| 1259 | #define USART1_UDRE_vect_num 26 |
---|
| 1260 | #define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ |
---|
| 1261 | #define USART1_TX_vect_num 27 |
---|
| 1262 | #define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ |
---|
| 1263 | #define ANALOG_COMP_vect_num 28 |
---|
| 1264 | #define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ |
---|
| 1265 | #define ADC_vect_num 29 |
---|
| 1266 | #define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ |
---|
| 1267 | #define EE_READY_vect_num 30 |
---|
| 1268 | #define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ |
---|
| 1269 | #define TIMER3_CAPT_vect_num 31 |
---|
| 1270 | #define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ |
---|
| 1271 | #define TIMER3_COMPA_vect_num 32 |
---|
| 1272 | #define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ |
---|
| 1273 | #define TIMER3_COMPB_vect_num 33 |
---|
| 1274 | #define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ |
---|
| 1275 | #define TIMER3_COMPC_vect_num 34 |
---|
| 1276 | #define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ |
---|
| 1277 | #define TIMER3_OVF_vect_num 35 |
---|
| 1278 | #define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ |
---|
| 1279 | #define TWI_vect_num 36 |
---|
| 1280 | #define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ |
---|
| 1281 | #define SPM_READY_vect_num 37 |
---|
| 1282 | #define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ |
---|
| 1283 | #define TIMER4_COMPA_vect_num 38 |
---|
| 1284 | #define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */ |
---|
| 1285 | #define TIMER4_COMPB_vect_num 39 |
---|
| 1286 | #define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */ |
---|
| 1287 | #define TIMER4_COMPD_vect_num 40 |
---|
| 1288 | #define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */ |
---|
| 1289 | #define TIMER4_OVF_vect_num 41 |
---|
| 1290 | #define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */ |
---|
| 1291 | #define TIMER4_FPF_vect_num 42 |
---|
| 1292 | #define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */ |
---|
| 1293 | |
---|
| 1294 | #define _VECTOR_SIZE 4 /* Size of individual vector. */ |
---|
| 1295 | #define _VECTORS_SIZE (43 * _VECTOR_SIZE) |
---|
| 1296 | |
---|
| 1297 | |
---|
| 1298 | /* Constants */ |
---|
| 1299 | #define SPM_PAGESIZE (128) |
---|
| 1300 | #define RAMSTART (0x100) |
---|
| 1301 | #define RAMSIZE (1280) |
---|
| 1302 | #define RAMEND (RAMSTART + RAMSIZE - 1) |
---|
| 1303 | #define XRAMSTART (NA) |
---|
| 1304 | #define XRAMSIZE (0) |
---|
| 1305 | #define XRAMEND (RAMEND) |
---|
| 1306 | #define E2END (0x1FF) |
---|
| 1307 | #define E2PAGESIZE (4) |
---|
| 1308 | #define FLASHEND (0x3FFF) |
---|
| 1309 | |
---|
| 1310 | |
---|
| 1311 | /* Fuses */ |
---|
| 1312 | #define FUSE_MEMORY_SIZE 3 |
---|
| 1313 | |
---|
| 1314 | /* Low Fuse Byte */ |
---|
| 1315 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ |
---|
| 1316 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ |
---|
| 1317 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ |
---|
| 1318 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ |
---|
| 1319 | #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ |
---|
| 1320 | #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ |
---|
| 1321 | #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ |
---|
| 1322 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ |
---|
| 1323 | #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) |
---|
| 1324 | |
---|
| 1325 | /* High Fuse Byte */ |
---|
| 1326 | #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ |
---|
| 1327 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ |
---|
| 1328 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ |
---|
| 1329 | #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ |
---|
| 1330 | #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ |
---|
| 1331 | #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ |
---|
| 1332 | #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ |
---|
| 1333 | #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ |
---|
| 1334 | #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) |
---|
| 1335 | |
---|
| 1336 | /* Extended Fuse Byte */ |
---|
| 1337 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ |
---|
| 1338 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ |
---|
| 1339 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ |
---|
| 1340 | #define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ |
---|
| 1341 | #define EFUSE_DEFAULT (0xFF) |
---|
| 1342 | |
---|
| 1343 | |
---|
| 1344 | /* Lock Bits */ |
---|
| 1345 | #define __LOCK_BITS_EXIST |
---|
| 1346 | #define __BOOT_LOCK_BITS_0_EXIST |
---|
| 1347 | #define __BOOT_LOCK_BITS_1_EXIST |
---|
| 1348 | |
---|
| 1349 | |
---|
| 1350 | /* Signature */ |
---|
| 1351 | #define SIGNATURE_0 0x1E |
---|
| 1352 | #define SIGNATURE_1 0x94 |
---|
| 1353 | #define SIGNATURE_2 0x88 |
---|
| 1354 | |
---|
| 1355 | |
---|
| 1356 | #endif /* _AVR_ATmega16U4_H_ */ |
---|
| 1357 | |
---|