1 | /* Copyright (c) 2009 Atmel Corporation |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | |
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32 | /* avr/iom169pa.h - definitions for ATmega169PA */ |
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33 | |
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34 | /* This file should only be included from <avr/io.h>, never directly. */ |
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35 | |
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36 | #ifndef _AVR_IO_H_ |
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37 | # error "Include <avr/io.h> instead of this file." |
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38 | #endif |
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39 | |
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40 | #ifndef _AVR_IOXXX_H_ |
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41 | # define _AVR_IOXXX_H_ "iom169pa.h" |
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42 | #else |
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43 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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44 | #endif |
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45 | |
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46 | |
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47 | #ifndef _AVR_ATmega169PA_H_ |
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48 | #define _AVR_ATmega169PA_H_ 1 |
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49 | |
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50 | |
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51 | /* Registers and associated bit numbers. */ |
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52 | |
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53 | #define PINA _SFR_IO8(0x00) |
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54 | #define PINA0 0 |
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55 | #define PINA1 1 |
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56 | #define PINA2 2 |
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57 | #define PINA3 3 |
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58 | #define PINA4 4 |
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59 | #define PINA5 5 |
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60 | #define PINA6 6 |
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61 | #define PINA7 7 |
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62 | |
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63 | #define DDRA _SFR_IO8(0x01) |
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64 | #define DDA0 0 |
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65 | #define DDA1 1 |
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66 | #define DDA2 2 |
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67 | #define DDA3 3 |
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68 | #define DDA4 4 |
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69 | #define DDA5 5 |
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70 | #define DDA6 6 |
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71 | #define DDA7 7 |
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72 | |
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73 | #define PORTA _SFR_IO8(0x02) |
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74 | #define PORTA0 0 |
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75 | #define PORTA1 1 |
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76 | #define PORTA2 2 |
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77 | #define PORTA3 3 |
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78 | #define PORTA4 4 |
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79 | #define PORTA5 5 |
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80 | #define PORTA6 6 |
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81 | #define PORTA7 7 |
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82 | |
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83 | #define PINB _SFR_IO8(0x03) |
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84 | #define PINB0 0 |
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85 | #define PINB1 1 |
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86 | #define PINB2 2 |
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87 | #define PINB3 3 |
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88 | #define PINB4 4 |
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89 | #define PINB5 5 |
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90 | #define PINB6 6 |
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91 | #define PINB7 7 |
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92 | |
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93 | #define DDRB _SFR_IO8(0x04) |
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94 | #define DDB0 0 |
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95 | #define DDB1 1 |
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96 | #define DDB2 2 |
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97 | #define DDB3 3 |
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98 | #define DDB4 4 |
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99 | #define DDB5 5 |
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100 | #define DDB6 6 |
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101 | #define DDB7 7 |
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102 | |
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103 | #define PORTB _SFR_IO8(0x05) |
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104 | #define PORTB0 0 |
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105 | #define PORTB1 1 |
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106 | #define PORTB2 2 |
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107 | #define PORTB3 3 |
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108 | #define PORTB4 4 |
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109 | #define PORTB5 5 |
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110 | #define PORTB6 6 |
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111 | #define PORTB7 7 |
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112 | |
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113 | #define PINC _SFR_IO8(0x06) |
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114 | #define PINC0 0 |
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115 | #define PINC1 1 |
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116 | #define PINC2 2 |
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117 | #define PINC3 3 |
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118 | #define PINC4 4 |
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119 | #define PINC5 5 |
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120 | #define PINC6 6 |
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121 | #define PINC7 7 |
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122 | |
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123 | #define DDRC _SFR_IO8(0x07) |
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124 | #define DDC0 0 |
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125 | #define DDC1 1 |
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126 | #define DDC2 2 |
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127 | #define DDC3 3 |
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128 | #define DDC4 4 |
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129 | #define DDC5 5 |
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130 | #define DDC6 6 |
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131 | #define DDC7 7 |
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132 | |
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133 | #define PORTC _SFR_IO8(0x08) |
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134 | #define PORTC0 0 |
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135 | #define PORTC1 1 |
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136 | #define PORTC2 2 |
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137 | #define PORTC3 3 |
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138 | #define PORTC4 4 |
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139 | #define PORTC5 5 |
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140 | #define PORTC6 6 |
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141 | #define PORTC7 7 |
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142 | |
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143 | #define PIND _SFR_IO8(0x09) |
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144 | #define PIND0 0 |
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145 | #define PIND1 1 |
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146 | #define PIND2 2 |
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147 | #define PIND3 3 |
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148 | #define PIND4 4 |
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149 | #define PIND5 5 |
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150 | #define PIND6 6 |
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151 | #define PIND7 7 |
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152 | |
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153 | #define DDRD _SFR_IO8(0x0A) |
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154 | #define DDD0 0 |
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155 | #define DDD1 1 |
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156 | #define DDD2 2 |
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157 | #define DDD3 3 |
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158 | #define DDD4 4 |
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159 | #define DDD5 5 |
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160 | #define DDD6 6 |
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161 | #define DDD7 7 |
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162 | |
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163 | #define PORTD _SFR_IO8(0x0B) |
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164 | #define PORTD0 0 |
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165 | #define PORTD1 1 |
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166 | #define PORTD2 2 |
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167 | #define PORTD3 3 |
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168 | #define PORTD4 4 |
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169 | #define PORTD5 5 |
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170 | #define PORTD6 6 |
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171 | #define PORTD7 7 |
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172 | |
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173 | #define PINE _SFR_IO8(0x0C) |
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174 | #define PINE0 0 |
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175 | #define PINE1 1 |
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176 | #define PINE2 2 |
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177 | #define PINE3 3 |
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178 | #define PINE4 4 |
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179 | #define PINE5 5 |
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180 | #define PINE6 6 |
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181 | #define PINE7 7 |
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182 | |
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183 | #define DDRE _SFR_IO8(0x0D) |
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184 | #define DDE0 0 |
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185 | #define DDE1 1 |
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186 | #define DDE2 2 |
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187 | #define DDE3 3 |
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188 | #define DDE4 4 |
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189 | #define DDE5 5 |
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190 | #define DDE6 6 |
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191 | #define DDE7 7 |
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192 | |
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193 | #define PORTE _SFR_IO8(0x0E) |
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194 | #define PORTE0 0 |
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195 | #define PORTE1 1 |
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196 | #define PORTE2 2 |
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197 | #define PORTE3 3 |
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198 | #define PORTE4 4 |
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199 | #define PORTE5 5 |
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200 | #define PORTE6 6 |
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201 | #define PORTE7 7 |
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202 | |
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203 | #define PINF _SFR_IO8(0x0F) |
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204 | #define PINF0 0 |
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205 | #define PINF1 1 |
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206 | #define PINF2 2 |
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207 | #define PINF3 3 |
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208 | #define PINF4 4 |
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209 | #define PINF5 5 |
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210 | #define PINF6 6 |
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211 | #define PINF7 7 |
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212 | |
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213 | #define DDRF _SFR_IO8(0x10) |
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214 | #define DDF0 0 |
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215 | #define DDF1 1 |
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216 | #define DDF2 2 |
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217 | #define DDF3 3 |
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218 | #define DDF4 4 |
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219 | #define DDF5 5 |
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220 | #define DDF6 6 |
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221 | #define DDF7 7 |
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222 | |
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223 | #define PORTF _SFR_IO8(0x11) |
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224 | #define PORTF0 0 |
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225 | #define PORTF1 1 |
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226 | #define PORTF2 2 |
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227 | #define PORTF3 3 |
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228 | #define PORTF4 4 |
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229 | #define PORTF5 5 |
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230 | #define PORTF6 6 |
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231 | #define PORTF7 7 |
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232 | |
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233 | #define PING _SFR_IO8(0x12) |
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234 | #define PING0 0 |
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235 | #define PING1 1 |
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236 | #define PING2 2 |
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237 | #define PING3 3 |
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238 | #define PING4 4 |
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239 | #define PING5 5 |
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240 | |
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241 | #define DDRG _SFR_IO8(0x13) |
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242 | #define DDG0 0 |
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243 | #define DDG1 1 |
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244 | #define DDG2 2 |
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245 | #define DDG3 3 |
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246 | #define DDG4 4 |
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247 | #define DDG5 5 |
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248 | |
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249 | #define PORTG _SFR_IO8(0x14) |
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250 | #define PORTG0 0 |
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251 | #define PORTG1 1 |
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252 | #define PORTG2 2 |
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253 | #define PORTG3 3 |
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254 | #define PORTG4 4 |
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255 | #define PORTG5 5 |
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256 | |
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257 | #define TIFR0 _SFR_IO8(0x15) |
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258 | #define TOV0 0 |
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259 | #define OCF0A 1 |
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260 | |
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261 | #define TIFR1 _SFR_IO8(0x16) |
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262 | #define TOV1 0 |
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263 | #define OCF1A 1 |
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264 | #define OCF1B 2 |
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265 | #define ICF1 5 |
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266 | |
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267 | #define TIFR2 _SFR_IO8(0x17) |
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268 | #define TOV2 0 |
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269 | #define OCF2A 1 |
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270 | |
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271 | #define EIFR _SFR_IO8(0x1C) |
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272 | #define INTF0 0 |
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273 | #define PCIF0 4 |
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274 | #define PCIF1 5 |
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275 | |
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276 | #define EIMSK _SFR_IO8(0x1D) |
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277 | #define INT0 0 |
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278 | #define PCIE0 4 |
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279 | #define PCIE1 5 |
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280 | |
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281 | #define GPIOR0 _SFR_IO8(0x1E) |
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282 | #define GPIOR00 0 |
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283 | #define GPIOR01 1 |
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284 | #define GPIOR02 2 |
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285 | #define GPIOR03 3 |
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286 | #define GPIOR04 4 |
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287 | #define GPIOR05 5 |
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288 | #define GPIOR06 6 |
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289 | #define GPIOR07 7 |
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290 | |
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291 | #define EECR _SFR_IO8(0x1F) |
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292 | #define EERE 0 |
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293 | #define EEWE 1 |
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294 | #define EEMWE 2 |
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295 | #define EERIE 3 |
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296 | |
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297 | #define EEDR _SFR_IO8(0x20) |
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298 | #define EEDR0 0 |
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299 | #define EEDR1 1 |
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300 | #define EEDR2 2 |
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301 | #define EEDR3 3 |
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302 | #define EEDR4 4 |
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303 | #define EEDR5 5 |
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304 | #define EEDR6 6 |
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305 | #define EEDR7 7 |
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306 | |
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307 | #define EEAR _SFR_IO16(0x21) |
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308 | |
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309 | #define EEARL _SFR_IO8(0x21) |
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310 | #define EEAR0 0 |
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311 | #define EEAR1 1 |
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312 | #define EEAR2 2 |
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313 | #define EEAR3 3 |
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314 | #define EEAR4 4 |
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315 | #define EEAR5 5 |
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316 | #define EEAR6 6 |
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317 | #define EEAR7 7 |
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318 | |
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319 | #define EEARH _SFR_IO8(0x22) |
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320 | #define EEAR8 0 |
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321 | |
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322 | #define GTCCR _SFR_IO8(0x23) |
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323 | #define PSR310 0 |
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324 | #define PSR2 1 |
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325 | #define TSM 7 |
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326 | |
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327 | #define TCCR0A _SFR_IO8(0x24) |
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328 | #define CS00 0 |
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329 | #define CS01 1 |
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330 | #define CS02 2 |
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331 | #define WGM01 3 |
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332 | #define COM0A0 4 |
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333 | #define COM0A1 5 |
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334 | #define WGM00 6 |
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335 | #define FOC0A 7 |
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336 | |
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337 | #define TCNT0 _SFR_IO8(0x26) |
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338 | #define TCNT0_0 0 |
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339 | #define TCNT0_1 1 |
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340 | #define TCNT0_2 2 |
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341 | #define TCNT0_3 3 |
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342 | #define TCNT0_4 4 |
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343 | #define TCNT0_5 5 |
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344 | #define TCNT0_6 6 |
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345 | #define TCNT0_7 7 |
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346 | |
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347 | #define OCR0A _SFR_IO8(0x27) |
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348 | #define OCR0A0 0 |
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349 | #define OCR0A1 1 |
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350 | #define OCR0A2 2 |
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351 | #define OCR0A3 3 |
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352 | #define OCR0A4 4 |
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353 | #define OCR0A5 5 |
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354 | #define OCR0A6 6 |
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355 | #define OCR0A7 7 |
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356 | |
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357 | #define GPIOR1 _SFR_IO8(0x2A) |
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358 | #define GPIOR10 0 |
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359 | #define GPIOR11 1 |
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360 | #define GPIOR12 2 |
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361 | #define GPIOR13 3 |
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362 | #define GPIOR14 4 |
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363 | #define GPIOR15 5 |
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364 | #define GPIOR16 6 |
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365 | #define GPIOR17 7 |
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366 | |
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367 | #define GPIOR2 _SFR_IO8(0x2B) |
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368 | #define GPIOR20 0 |
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369 | #define GPIOR21 1 |
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370 | #define GPIOR22 2 |
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371 | #define GPIOR23 3 |
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372 | #define GPIOR24 4 |
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373 | #define GPIOR25 5 |
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374 | #define GPIOR26 6 |
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375 | #define GPIOR27 7 |
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376 | |
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377 | #define SPCR _SFR_IO8(0x2C) |
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378 | #define SPR0 0 |
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379 | #define SPR1 1 |
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380 | #define CPHA 2 |
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381 | #define CPOL 3 |
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382 | #define MSTR 4 |
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383 | #define DORD 5 |
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384 | #define SPE 6 |
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385 | #define SPIE 7 |
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386 | |
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387 | #define SPSR _SFR_IO8(0x2D) |
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388 | #define SPI2X 0 |
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389 | #define WCOL 6 |
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390 | #define SPIF 7 |
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391 | |
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392 | #define SPDR _SFR_IO8(0x2E) |
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393 | #define SPDR0 0 |
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394 | #define SPDR1 1 |
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395 | #define SPDR2 2 |
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396 | #define SPDR3 3 |
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397 | #define SPDR4 4 |
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398 | #define SPDR5 5 |
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399 | #define SPDR6 6 |
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400 | #define SPDR7 7 |
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401 | |
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402 | #define ACSR _SFR_IO8(0x30) |
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403 | #define ACIS0 0 |
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404 | #define ACIS1 1 |
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405 | #define ACIC 2 |
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406 | #define ACIE 3 |
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407 | #define ACI 4 |
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408 | #define ACO 5 |
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409 | #define ACBG 6 |
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410 | #define ACD 7 |
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411 | |
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412 | #define OCDR _SFR_IO8(0x31) |
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413 | #define OCDR0 0 |
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414 | #define OCDR1 1 |
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415 | #define OCDR2 2 |
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416 | #define OCDR3 3 |
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417 | #define OCDR4 4 |
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418 | #define OCDR5 5 |
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419 | #define OCDR6 6 |
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420 | #define OCDR7 7 |
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421 | |
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422 | #define SMCR _SFR_IO8(0x33) |
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423 | #define SE 0 |
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424 | #define SM0 1 |
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425 | #define SM1 2 |
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426 | #define SM2 3 |
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427 | |
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428 | #define MCUSR _SFR_IO8(0x34) |
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429 | #define PORF 0 |
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430 | #define EXTRF 1 |
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431 | #define BORF 2 |
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432 | #define WDRF 3 |
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433 | #define JTRF 4 |
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434 | |
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435 | #define MCUCR _SFR_IO8(0x35) |
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436 | #define IVCE 0 |
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437 | #define IVSEL 1 |
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438 | #define PUD 4 |
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439 | #define BODSE 5 |
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440 | #define BODS 6 |
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441 | #define JTD 7 |
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442 | |
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443 | #define SPMCSR _SFR_IO8(0x37) |
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444 | #define SPMEN 0 |
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445 | #define PGERS 1 |
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446 | #define PGWRT 2 |
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447 | #define BLBSET 3 |
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448 | #define RWWSRE 4 |
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449 | #define RWWSB 6 |
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450 | #define SPMIE 7 |
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451 | |
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452 | #define WDTCR _SFR_MEM8(0x60) |
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453 | #define WDP0 0 |
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454 | #define WDP1 1 |
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455 | #define WDP2 2 |
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456 | #define WDE 3 |
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457 | #define WDCE 4 |
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458 | |
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459 | #define CLKPR _SFR_MEM8(0x61) |
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460 | #define CLKPS0 0 |
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461 | #define CLKPS1 1 |
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462 | #define CLKPS2 2 |
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463 | #define CLKPS3 3 |
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464 | #define CLKPCE 7 |
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465 | |
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466 | #define PRR _SFR_MEM8(0x64) |
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467 | #define PRADC 0 |
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468 | #define PRUSART0 1 |
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469 | #define PRSPI 2 |
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470 | #define PRTIM1 3 |
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471 | #define PRLCD 4 |
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472 | |
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473 | #define OSCCAL _SFR_MEM8(0x66) |
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474 | #define CAL0 0 |
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475 | #define CAL1 1 |
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476 | #define CAL2 2 |
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477 | #define CAL3 3 |
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478 | #define CAL4 4 |
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479 | #define CAL5 5 |
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480 | #define CAL6 6 |
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481 | #define CAL7 7 |
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482 | |
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483 | #define EICRA _SFR_MEM8(0x69) |
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484 | #define ISC00 0 |
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485 | #define ISC01 1 |
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486 | |
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487 | #define PCMSK0 _SFR_MEM8(0x6B) |
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488 | #define PCINT0 0 |
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489 | #define PCINT1 1 |
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490 | #define PCINT2 2 |
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491 | #define PCINT3 3 |
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492 | #define PCINT4 4 |
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493 | #define PCINT5 5 |
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494 | #define PCINT6 6 |
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495 | #define PCINT7 7 |
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496 | |
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497 | #define PCMSK1 _SFR_MEM8(0x6C) |
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498 | #define PCINT8 0 |
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499 | #define PCINT9 1 |
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500 | #define PCINT10 2 |
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501 | #define PCINT11 3 |
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502 | #define PCINT12 4 |
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503 | #define PCINT13 5 |
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504 | #define PCINT14 6 |
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505 | #define PCINT15 7 |
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506 | |
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507 | #define TIMSK0 _SFR_MEM8(0x6E) |
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508 | #define TOIE0 0 |
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509 | #define OCIE0A 1 |
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510 | |
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511 | #define TIMSK1 _SFR_MEM8(0x6F) |
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512 | #define TOIE1 0 |
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513 | #define OCIE1A 1 |
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514 | #define OCIE1B 2 |
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515 | #define ICIE1 5 |
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516 | |
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517 | #define TIMSK2 _SFR_MEM8(0x70) |
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518 | #define TOIE2 0 |
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519 | #define OCIE2A 1 |
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520 | |
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521 | #ifndef __ASSEMBLER__ |
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522 | #define ADC _SFR_MEM16(0x78) |
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523 | #endif |
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524 | #define ADCW _SFR_MEM16(0x78) |
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525 | |
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526 | #define ADCL _SFR_MEM8(0x78) |
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527 | #define ADCL0 0 |
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528 | #define ADCL1 1 |
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529 | #define ADCL2 2 |
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530 | #define ADCL3 3 |
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531 | #define ADCL4 4 |
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532 | #define ADCL5 5 |
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533 | #define ADCL6 6 |
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534 | #define ADCL7 7 |
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535 | |
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536 | #define ADCH _SFR_MEM8(0x79) |
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537 | #define ADCH0 0 |
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538 | #define ADCH1 1 |
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539 | #define ADCH2 2 |
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540 | #define ADCH3 3 |
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541 | #define ADCH4 4 |
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542 | #define ADCH5 5 |
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543 | #define ADCH6 6 |
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544 | #define ADCH7 7 |
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545 | |
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546 | #define ADCSRA _SFR_MEM8(0x7A) |
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547 | #define ADPS0 0 |
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548 | #define ADPS1 1 |
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549 | #define ADPS2 2 |
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550 | #define ADIE 3 |
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551 | #define ADIF 4 |
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552 | #define ADATE 5 |
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553 | #define ADSC 6 |
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554 | #define ADEN 7 |
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555 | |
---|
556 | #define ADCSRB _SFR_MEM8(0x7B) |
---|
557 | #define ADTS0 0 |
---|
558 | #define ADTS1 1 |
---|
559 | #define ADTS2 2 |
---|
560 | #define ACME 6 |
---|
561 | |
---|
562 | #define ADMUX _SFR_MEM8(0x7C) |
---|
563 | #define MUX0 0 |
---|
564 | #define MUX1 1 |
---|
565 | #define MUX2 2 |
---|
566 | #define MUX3 3 |
---|
567 | #define MUX4 4 |
---|
568 | #define ADLAR 5 |
---|
569 | #define REFS0 6 |
---|
570 | #define REFS1 7 |
---|
571 | |
---|
572 | #define DIDR0 _SFR_MEM8(0x7E) |
---|
573 | #define ADC0D 0 |
---|
574 | #define ADC1D 1 |
---|
575 | #define ADC2D 2 |
---|
576 | #define ADC3D 3 |
---|
577 | #define ADC4D 4 |
---|
578 | #define ADC5D 5 |
---|
579 | #define ADC6D 6 |
---|
580 | #define ADC7D 7 |
---|
581 | |
---|
582 | #define DIDR1 _SFR_MEM8(0x7F) |
---|
583 | #define AIN0D 0 |
---|
584 | #define AIN1D 1 |
---|
585 | |
---|
586 | #define TCCR1A _SFR_MEM8(0x80) |
---|
587 | #define WGM10 0 |
---|
588 | #define WGM11 1 |
---|
589 | #define COM1B0 4 |
---|
590 | #define COM1B1 5 |
---|
591 | #define COM1A0 6 |
---|
592 | #define COM1A1 7 |
---|
593 | |
---|
594 | #define TCCR1B _SFR_MEM8(0x81) |
---|
595 | #define CS10 0 |
---|
596 | #define CS11 1 |
---|
597 | #define CS12 2 |
---|
598 | #define WGM12 3 |
---|
599 | #define WGM13 4 |
---|
600 | #define ICES1 6 |
---|
601 | #define ICNC1 7 |
---|
602 | |
---|
603 | #define TCCR1C _SFR_MEM8(0x82) |
---|
604 | #define FOC1B 6 |
---|
605 | #define FOC1A 7 |
---|
606 | |
---|
607 | #define TCNT1 _SFR_MEM16(0x84) |
---|
608 | |
---|
609 | #define TCNT1L _SFR_MEM8(0x84) |
---|
610 | #define TCNT1L0 0 |
---|
611 | #define TCNT1L1 1 |
---|
612 | #define TCNT1L2 2 |
---|
613 | #define TCNT1L3 3 |
---|
614 | #define TCNT1L4 4 |
---|
615 | #define TCNT1L5 5 |
---|
616 | #define TCNT1L6 6 |
---|
617 | #define TCNT1L7 7 |
---|
618 | |
---|
619 | #define TCNT1H _SFR_MEM8(0x85) |
---|
620 | #define TCNT1H0 0 |
---|
621 | #define TCNT1H1 1 |
---|
622 | #define TCNT1H2 2 |
---|
623 | #define TCNT1H3 3 |
---|
624 | #define TCNT1H4 4 |
---|
625 | #define TCNT1H5 5 |
---|
626 | #define TCNT1H6 6 |
---|
627 | #define TCNT1H7 7 |
---|
628 | |
---|
629 | #define ICR1 _SFR_MEM16(0x86) |
---|
630 | |
---|
631 | #define ICR1L _SFR_MEM8(0x86) |
---|
632 | #define ICR1L0 0 |
---|
633 | #define ICR1L1 1 |
---|
634 | #define ICR1L2 2 |
---|
635 | #define ICR1L3 3 |
---|
636 | #define ICR1L4 4 |
---|
637 | #define ICR1L5 5 |
---|
638 | #define ICR1L6 6 |
---|
639 | #define ICR1L7 7 |
---|
640 | |
---|
641 | #define ICR1H _SFR_MEM8(0x87) |
---|
642 | #define ICR1H0 0 |
---|
643 | #define ICR1H1 1 |
---|
644 | #define ICR1H2 2 |
---|
645 | #define ICR1H3 3 |
---|
646 | #define ICR1H4 4 |
---|
647 | #define ICR1H5 5 |
---|
648 | #define ICR1H6 6 |
---|
649 | #define ICR1H7 7 |
---|
650 | |
---|
651 | #define OCR1A _SFR_MEM16(0x88) |
---|
652 | |
---|
653 | #define OCR1AL _SFR_MEM8(0x88) |
---|
654 | #define OCR1AL0 0 |
---|
655 | #define OCR1AL1 1 |
---|
656 | #define OCR1AL2 2 |
---|
657 | #define OCR1AL3 3 |
---|
658 | #define OCR1AL4 4 |
---|
659 | #define OCR1AL5 5 |
---|
660 | #define OCR1AL6 6 |
---|
661 | #define OCR1AL7 7 |
---|
662 | |
---|
663 | #define OCR1AH _SFR_MEM8(0x89) |
---|
664 | #define OCR1AH0 0 |
---|
665 | #define OCR1AH1 1 |
---|
666 | #define OCR1AH2 2 |
---|
667 | #define OCR1AH3 3 |
---|
668 | #define OCR1AH4 4 |
---|
669 | #define OCR1AH5 5 |
---|
670 | #define OCR1AH6 6 |
---|
671 | #define OCR1AH7 7 |
---|
672 | |
---|
673 | #define OCR1B _SFR_MEM16(0x8A) |
---|
674 | |
---|
675 | #define OCR1BL _SFR_MEM8(0x8A) |
---|
676 | #define OCR1BL0 0 |
---|
677 | #define OCR1BL1 1 |
---|
678 | #define OCR1BL2 2 |
---|
679 | #define OCR1BL3 3 |
---|
680 | #define OCR1BL4 4 |
---|
681 | #define OCR1BL5 5 |
---|
682 | #define OCR1BL6 6 |
---|
683 | #define OCR1BL7 7 |
---|
684 | |
---|
685 | #define OCR1BH _SFR_MEM8(0x8B) |
---|
686 | #define OCR1BH0 0 |
---|
687 | #define OCR1BH1 1 |
---|
688 | #define OCR1BH2 2 |
---|
689 | #define OCR1BH3 3 |
---|
690 | #define OCR1BH4 4 |
---|
691 | #define OCR1BH5 5 |
---|
692 | #define OCR1BH6 6 |
---|
693 | #define OCR1BH7 7 |
---|
694 | |
---|
695 | #define TCCR2A _SFR_MEM8(0xB0) |
---|
696 | #define CS20 0 |
---|
697 | #define CS21 1 |
---|
698 | #define CS22 2 |
---|
699 | #define WGM21 3 |
---|
700 | #define COM2A0 4 |
---|
701 | #define COM2A1 5 |
---|
702 | #define WGM20 6 |
---|
703 | #define FOC2A 7 |
---|
704 | |
---|
705 | #define TCCR2B _SFR_MEM8(0xB1) |
---|
706 | |
---|
707 | #define TCNT2 _SFR_MEM8(0xB2) |
---|
708 | #define TCNT2_0 0 |
---|
709 | #define TCNT2_1 1 |
---|
710 | #define TCNT2_2 2 |
---|
711 | #define TCNT2_3 3 |
---|
712 | #define TCNT2_4 4 |
---|
713 | #define TCNT2_5 5 |
---|
714 | #define TCNT2_6 6 |
---|
715 | #define TCNT2_7 7 |
---|
716 | |
---|
717 | #define OCR2A _SFR_MEM8(0xB3) |
---|
718 | #define OCR2A0 0 |
---|
719 | #define OCR2A1 1 |
---|
720 | #define OCR2A2 2 |
---|
721 | #define OCR2A3 3 |
---|
722 | #define OCR2A4 4 |
---|
723 | #define OCR2A5 5 |
---|
724 | #define OCR2A6 6 |
---|
725 | #define OCR2A7 7 |
---|
726 | |
---|
727 | #define ASSR _SFR_MEM8(0xB6) |
---|
728 | #define TCR2UB 0 |
---|
729 | #define OCR2UB 1 |
---|
730 | #define TCN2UB 2 |
---|
731 | #define AS2 3 |
---|
732 | #define EXCLK 4 |
---|
733 | |
---|
734 | #define USICR _SFR_MEM8(0xB8) |
---|
735 | #define USITC 0 |
---|
736 | #define USICLK 1 |
---|
737 | #define USICS0 2 |
---|
738 | #define USICS1 3 |
---|
739 | #define USIWM0 4 |
---|
740 | #define USIWM1 5 |
---|
741 | #define USIOIE 6 |
---|
742 | #define USISIE 7 |
---|
743 | |
---|
744 | #define USISR _SFR_MEM8(0xB9) |
---|
745 | #define USICNT0 0 |
---|
746 | #define USICNT1 1 |
---|
747 | #define USICNT2 2 |
---|
748 | #define USICNT3 3 |
---|
749 | #define USIDC 4 |
---|
750 | #define USIPF 5 |
---|
751 | #define USIOIF 6 |
---|
752 | #define USISIF 7 |
---|
753 | |
---|
754 | #define USIDR _SFR_MEM8(0xBA) |
---|
755 | #define USIDR0 0 |
---|
756 | #define USIDR1 1 |
---|
757 | #define USIDR2 2 |
---|
758 | #define USIDR3 3 |
---|
759 | #define USIDR4 4 |
---|
760 | #define USIDR5 5 |
---|
761 | #define USIDR6 6 |
---|
762 | #define USIDR7 7 |
---|
763 | |
---|
764 | #define UCSR0A _SFR_MEM8(0xC0) |
---|
765 | #define MPCM0 0 |
---|
766 | #define U2X0 1 |
---|
767 | #define UPE0 2 |
---|
768 | #define DOR0 3 |
---|
769 | #define FE0 4 |
---|
770 | #define UDRE0 5 |
---|
771 | #define TXC0 6 |
---|
772 | #define RXC0 7 |
---|
773 | |
---|
774 | #define UCSR0B _SFR_MEM8(0xC1) |
---|
775 | #define TXB80 0 |
---|
776 | #define RXB80 1 |
---|
777 | #define UCSZ02 2 |
---|
778 | #define TXEN0 3 |
---|
779 | #define RXEN0 4 |
---|
780 | #define UDRIE0 5 |
---|
781 | #define TXCIE0 6 |
---|
782 | #define RXCIE0 7 |
---|
783 | |
---|
784 | #define UCSR0C _SFR_MEM8(0xC2) |
---|
785 | #define UCPOL0 0 |
---|
786 | #define UCSZ00 1 |
---|
787 | #define UCSZ01 2 |
---|
788 | #define USBS0 3 |
---|
789 | #define UPM00 4 |
---|
790 | #define UPM01 5 |
---|
791 | #define UMSEL0 6 |
---|
792 | |
---|
793 | #define UBRR0 _SFR_MEM16(0xC4) |
---|
794 | |
---|
795 | #define UBRR0L _SFR_MEM8(0xC4) |
---|
796 | #define UBRR0 0 |
---|
797 | #define UBRR1 1 |
---|
798 | #define UBRR2 2 |
---|
799 | #define UBRR3 3 |
---|
800 | #define UBRR4 4 |
---|
801 | #define UBRR5 5 |
---|
802 | #define UBRR6 6 |
---|
803 | #define UBRR7 7 |
---|
804 | |
---|
805 | #define UBRR0H _SFR_MEM8(0xC5) |
---|
806 | #define UBRR8 0 |
---|
807 | #define UBRR9 1 |
---|
808 | #define UBRR10 2 |
---|
809 | #define UBRR11 3 |
---|
810 | |
---|
811 | #define UDR0 _SFR_MEM8(0xC6) |
---|
812 | #define UDR00 0 |
---|
813 | #define UDR01 1 |
---|
814 | #define UDR02 2 |
---|
815 | #define UDR03 3 |
---|
816 | #define UDR04 4 |
---|
817 | #define UDR05 5 |
---|
818 | #define UDR06 6 |
---|
819 | #define UDR07 7 |
---|
820 | |
---|
821 | #define LCDCRA _SFR_MEM8(0xE4) |
---|
822 | #define LCDBL 0 |
---|
823 | #define LCDCCD 1 |
---|
824 | #define LCDBD 2 |
---|
825 | #define LCDIE 3 |
---|
826 | #define LCDIF 4 |
---|
827 | #define LCDAB 6 |
---|
828 | #define LCDEN 7 |
---|
829 | |
---|
830 | #define LCDCRB _SFR_MEM8(0xE5) |
---|
831 | #define LCDPM0 0 |
---|
832 | #define LCDPM1 1 |
---|
833 | #define LCDPM2 2 |
---|
834 | #define LCDMUX0 4 |
---|
835 | #define LCDMUX1 5 |
---|
836 | #define LCD2B 6 |
---|
837 | #define LCDCS 7 |
---|
838 | |
---|
839 | #define LCDFRR _SFR_MEM8(0xE6) |
---|
840 | #define LCDCD0 0 |
---|
841 | #define LCDCD1 1 |
---|
842 | #define LCDCD2 2 |
---|
843 | #define LCDPS0 4 |
---|
844 | #define LCDPS1 5 |
---|
845 | #define LCDPS2 6 |
---|
846 | |
---|
847 | #define LCDCCR _SFR_MEM8(0xE7) |
---|
848 | #define LCDCC0 0 |
---|
849 | #define LCDCC1 1 |
---|
850 | #define LCDCC2 2 |
---|
851 | #define LCDCC3 3 |
---|
852 | #define LCDMDT 4 |
---|
853 | #define LCDDC0 5 |
---|
854 | #define LCDDC1 6 |
---|
855 | #define LCDDC2 7 |
---|
856 | |
---|
857 | #define LCDDR0 _SFR_MEM8(0xEC) |
---|
858 | #define SEG000 0 |
---|
859 | #define SEG001 1 |
---|
860 | #define SEG002 2 |
---|
861 | #define SEG003 3 |
---|
862 | #define SEG004 4 |
---|
863 | #define SEG005 5 |
---|
864 | #define SEG006 6 |
---|
865 | #define SEG007 7 |
---|
866 | |
---|
867 | #define LCDDR1 _SFR_MEM8(0xED) |
---|
868 | #define SEG008 0 |
---|
869 | #define SEG009 1 |
---|
870 | #define SEG010 2 |
---|
871 | #define SEG011 3 |
---|
872 | #define SEG012 4 |
---|
873 | #define SEG013 5 |
---|
874 | #define SEG014 6 |
---|
875 | #define SEG015 7 |
---|
876 | |
---|
877 | #define LCDDR2 _SFR_MEM8(0xEE) |
---|
878 | #define SEG016 0 |
---|
879 | #define SEG017 1 |
---|
880 | #define SEG018 2 |
---|
881 | #define SEG019 3 |
---|
882 | #define SEG020 4 |
---|
883 | #define SEG021 5 |
---|
884 | #define SEG022 6 |
---|
885 | #define SEG023 7 |
---|
886 | |
---|
887 | #define LCDDR3 _SFR_MEM8(0xEF) |
---|
888 | #define SEG024 0 |
---|
889 | |
---|
890 | #define LCDDR5 _SFR_MEM8(0xF1) |
---|
891 | #define SEG100 0 |
---|
892 | #define SEG101 1 |
---|
893 | #define SEG102 2 |
---|
894 | #define SEG103 3 |
---|
895 | #define SEG104 4 |
---|
896 | #define SEG105 5 |
---|
897 | #define SEG106 6 |
---|
898 | #define SEG107 7 |
---|
899 | |
---|
900 | #define LCDDR6 _SFR_MEM8(0xF2) |
---|
901 | #define SEG108 0 |
---|
902 | #define SEG109 1 |
---|
903 | #define SEG110 2 |
---|
904 | #define SEG111 3 |
---|
905 | #define SEG112 4 |
---|
906 | #define SEG113 5 |
---|
907 | #define SEG114 6 |
---|
908 | #define SEG115 7 |
---|
909 | |
---|
910 | #define LCDDR7 _SFR_MEM8(0xF3) |
---|
911 | #define SEG116 0 |
---|
912 | #define SEG117 1 |
---|
913 | #define SEG118 2 |
---|
914 | #define SEG119 3 |
---|
915 | #define SEG120 4 |
---|
916 | #define SEG121 5 |
---|
917 | #define SEG122 6 |
---|
918 | #define SEG123 7 |
---|
919 | |
---|
920 | #define LCDDR8 _SFR_MEM8(0xF4) |
---|
921 | #define SEG124 0 |
---|
922 | |
---|
923 | #define LCDDR10 _SFR_MEM8(0xF6) |
---|
924 | #define SEG200 0 |
---|
925 | #define SEG201 1 |
---|
926 | #define SEG202 2 |
---|
927 | #define SEG203 3 |
---|
928 | #define SEG204 4 |
---|
929 | #define SEG205 5 |
---|
930 | #define SEG206 6 |
---|
931 | #define SEG207 7 |
---|
932 | |
---|
933 | #define LCDDR11 _SFR_MEM8(0xF7) |
---|
934 | #define SEG208 0 |
---|
935 | #define SEG209 1 |
---|
936 | #define SEG210 2 |
---|
937 | #define SEG211 3 |
---|
938 | #define SEG212 4 |
---|
939 | #define SEG213 5 |
---|
940 | #define SEG214 6 |
---|
941 | #define SEG215 7 |
---|
942 | |
---|
943 | #define LCDDR12 _SFR_MEM8(0xF8) |
---|
944 | #define SEG216 0 |
---|
945 | #define SEG217 1 |
---|
946 | #define SEG218 2 |
---|
947 | #define SEG219 3 |
---|
948 | #define SEG220 4 |
---|
949 | #define SEG221 5 |
---|
950 | #define SEG222 6 |
---|
951 | #define SEG223 7 |
---|
952 | |
---|
953 | #define LCDDR13 _SFR_MEM8(0xF9) |
---|
954 | #define SEG224 0 |
---|
955 | |
---|
956 | #define LCDDR15 _SFR_MEM8(0xFB) |
---|
957 | #define SEG300 0 |
---|
958 | #define SEG301 1 |
---|
959 | #define SEG302 2 |
---|
960 | #define SEG303 3 |
---|
961 | #define SEG304 4 |
---|
962 | #define SEG305 5 |
---|
963 | #define SEG306 6 |
---|
964 | #define SEG307 7 |
---|
965 | |
---|
966 | #define LCDDR16 _SFR_MEM8(0xFC) |
---|
967 | #define SEG308 0 |
---|
968 | #define SEG309 1 |
---|
969 | #define SEG310 2 |
---|
970 | #define SEG311 3 |
---|
971 | #define SEG312 4 |
---|
972 | #define SEG313 5 |
---|
973 | #define SEG314 6 |
---|
974 | #define SEG315 7 |
---|
975 | |
---|
976 | #define LCDDR17 _SFR_MEM8(0xFD) |
---|
977 | #define SEG316 0 |
---|
978 | #define SEG317 1 |
---|
979 | #define SEG318 2 |
---|
980 | #define SEG319 3 |
---|
981 | #define SEG320 4 |
---|
982 | #define SEG321 5 |
---|
983 | #define SEG322 6 |
---|
984 | #define SEG323 7 |
---|
985 | |
---|
986 | #define LCDDR18 _SFR_MEM8(0xFE) |
---|
987 | #define SEG324 0 |
---|
988 | |
---|
989 | |
---|
990 | /* Interrupt vectors */ |
---|
991 | /* Vector 0 is the reset vector */ |
---|
992 | #define INT0_vect_num 1 |
---|
993 | #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ |
---|
994 | #define PCINT0_vect_num 2 |
---|
995 | #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ |
---|
996 | #define PCINT1_vect_num 3 |
---|
997 | #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ |
---|
998 | #define TIMER2_COMP_vect_num 4 |
---|
999 | #define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */ |
---|
1000 | #define TIMER2_OVF_vect_num 5 |
---|
1001 | #define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */ |
---|
1002 | #define TIMER1_CAPT_vect_num 6 |
---|
1003 | #define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ |
---|
1004 | #define TIMER1_COMPA_vect_num 7 |
---|
1005 | #define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ |
---|
1006 | #define TIMER1_COMPB_vect_num 8 |
---|
1007 | #define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */ |
---|
1008 | #define TIMER1_OVF_vect_num 9 |
---|
1009 | #define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ |
---|
1010 | #define TIMER0_COMP_vect_num 10 |
---|
1011 | #define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */ |
---|
1012 | #define TIMER0_OVF_vect_num 11 |
---|
1013 | #define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ |
---|
1014 | #define SPI_STC_vect_num 12 |
---|
1015 | #define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */ |
---|
1016 | #define USART0_RX_vect_num 13 |
---|
1017 | #define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */ |
---|
1018 | #define USART0_UDRE_vect_num 14 |
---|
1019 | #define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */ |
---|
1020 | #define USART0_TX_vect_num 15 |
---|
1021 | #define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */ |
---|
1022 | #define USI_START_vect_num 16 |
---|
1023 | #define USI_START_vect _VECTOR(16) /* USI Start Condition */ |
---|
1024 | #define USI_OVERFLOW_vect_num 17 |
---|
1025 | #define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */ |
---|
1026 | #define ANALOG_COMP_vect_num 18 |
---|
1027 | #define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */ |
---|
1028 | #define ADC_vect_num 19 |
---|
1029 | #define ADC_vect _VECTOR(19) /* ADC Conversion Complete */ |
---|
1030 | #define EE_READY_vect_num 20 |
---|
1031 | #define EE_READY_vect _VECTOR(20) /* EEPROM Ready */ |
---|
1032 | #define SPM_READY_vect_num 21 |
---|
1033 | #define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */ |
---|
1034 | #define LCD_vect_num 22 |
---|
1035 | #define LCD_vect _VECTOR(22) /* LCD Start of Frame */ |
---|
1036 | |
---|
1037 | #define _VECTOR_SIZE 4 /* Size of individual vector. */ |
---|
1038 | #define _VECTORS_SIZE (23 * _VECTOR_SIZE) |
---|
1039 | |
---|
1040 | |
---|
1041 | /* Constants */ |
---|
1042 | #define SPM_PAGESIZE (128) |
---|
1043 | #define RAMSTART (0x100) |
---|
1044 | #define RAMSIZE (1024) |
---|
1045 | #define RAMEND (RAMSTART + RAMSIZE - 1) |
---|
1046 | #define XRAMSTART (NA) |
---|
1047 | #define XRAMSIZE (0) |
---|
1048 | #define XRAMEND (RAMEND) |
---|
1049 | #define E2END (0x1FF) |
---|
1050 | #define E2PAGESIZE (4) |
---|
1051 | #define FLASHEND (0x3FFF) |
---|
1052 | |
---|
1053 | |
---|
1054 | /* Fuses */ |
---|
1055 | #define FUSE_MEMORY_SIZE 3 |
---|
1056 | |
---|
1057 | /* Low Fuse Byte */ |
---|
1058 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ |
---|
1059 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ |
---|
1060 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ |
---|
1061 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ |
---|
1062 | #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ |
---|
1063 | #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ |
---|
1064 | #define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ |
---|
1065 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ |
---|
1066 | #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) |
---|
1067 | |
---|
1068 | /* High Fuse Byte */ |
---|
1069 | #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ |
---|
1070 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ |
---|
1071 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ |
---|
1072 | #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ |
---|
1073 | #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ |
---|
1074 | #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ |
---|
1075 | #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ |
---|
1076 | #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ |
---|
1077 | #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) |
---|
1078 | |
---|
1079 | /* Extended Fuse Byte */ |
---|
1080 | #define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */ |
---|
1081 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ |
---|
1082 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ |
---|
1083 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown out detector trigger level */ |
---|
1084 | #define EFUSE_DEFAULT (0xFF) |
---|
1085 | |
---|
1086 | |
---|
1087 | /* Lock Bits */ |
---|
1088 | #define __LOCK_BITS_EXIST |
---|
1089 | #define __BOOT_LOCK_BITS_0_EXIST |
---|
1090 | #define __BOOT_LOCK_BITS_1_EXIST |
---|
1091 | |
---|
1092 | |
---|
1093 | /* Signature */ |
---|
1094 | #define SIGNATURE_0 0x1E |
---|
1095 | #define SIGNATURE_1 0x94 |
---|
1096 | #define SIGNATURE_2 0x05 |
---|
1097 | |
---|
1098 | |
---|
1099 | /* Device Pin Definitions */ |
---|
1100 | #define RXD_DDR DDRE |
---|
1101 | #define RXD_PORT PORTE |
---|
1102 | #define RXD_PIN PINE |
---|
1103 | #define RXD_BIT 0 |
---|
1104 | |
---|
1105 | #define PCINT0_DDR DDRE |
---|
1106 | #define PCINT0_PORT PORTE |
---|
1107 | #define PCINT0_PIN PINE |
---|
1108 | #define PCINT0_BIT 0 |
---|
1109 | |
---|
1110 | #define TXD_DDR DDRE |
---|
1111 | #define TXD_PORT PORTE |
---|
1112 | #define TXD_PIN PINE |
---|
1113 | #define TXD_BIT 1 |
---|
1114 | |
---|
1115 | #define PCINT1_DDR DDRE |
---|
1116 | #define PCINT1_PORT PORTE |
---|
1117 | #define PCINT1_PIN PINE |
---|
1118 | #define PCINT1_BIT 1 |
---|
1119 | |
---|
1120 | #define XCK_DDR DDRE |
---|
1121 | #define XCK_PORT PORTE |
---|
1122 | #define XCK_PIN PINE |
---|
1123 | #define XCK_BIT 2 |
---|
1124 | |
---|
1125 | #define AIN0_DDR DDRE |
---|
1126 | #define AIN0_PORT PORTE |
---|
1127 | #define AIN0_PIN PINE |
---|
1128 | #define AIN0_BIT 2 |
---|
1129 | |
---|
1130 | #define PCINT2_DDR DDRE |
---|
1131 | #define PCINT2_PORT PORTE |
---|
1132 | #define PCINT2_PIN PINE |
---|
1133 | #define PCINT2_BIT 2 |
---|
1134 | |
---|
1135 | #define AIN1_DDR DDRE |
---|
1136 | #define AIN1_PORT PORTE |
---|
1137 | #define AIN1_PIN PINE |
---|
1138 | #define AIN1_BIT 3 |
---|
1139 | |
---|
1140 | #define PCINT3_DDR DDRE |
---|
1141 | #define PCINT3_PORT PORTE |
---|
1142 | #define PCINT3_PIN PINE |
---|
1143 | #define PCINT3_BIT 3 |
---|
1144 | |
---|
1145 | #define USCK_DDR DDRE |
---|
1146 | #define USCK_PORT PORTE |
---|
1147 | #define USCK_PIN PINE |
---|
1148 | #define USCK_BIT 4 |
---|
1149 | |
---|
1150 | #define SCL_DDR DDRE |
---|
1151 | #define SCL_PORT PORTE |
---|
1152 | #define SCL_PIN PINE |
---|
1153 | #define SCL_BIT 4 |
---|
1154 | |
---|
1155 | #define PCINT4_DDR DDRE |
---|
1156 | #define PCINT4_PORT PORTE |
---|
1157 | #define PCINT4_PIN PINE |
---|
1158 | #define PCINT4_BIT 4 |
---|
1159 | |
---|
1160 | #define DI_DDR DDRE |
---|
1161 | #define DI_PORT PORTE |
---|
1162 | #define DI_PIN PINE |
---|
1163 | #define DI_BIT 5 |
---|
1164 | |
---|
1165 | #define SDA_DDR DDRE |
---|
1166 | #define SDA_PORT PORTE |
---|
1167 | #define SDA_PIN PINE |
---|
1168 | #define SDA_BIT 5 |
---|
1169 | |
---|
1170 | #define PCINT5_DDR DDRE |
---|
1171 | #define PCINT5_PORT PORTE |
---|
1172 | #define PCINT5_PIN PINE |
---|
1173 | #define PCINT5_BIT 5 |
---|
1174 | |
---|
1175 | #define DO_DDR DDRE |
---|
1176 | #define DO_PORT PORTE |
---|
1177 | #define DO_PIN PINE |
---|
1178 | #define DO_BIT 6 |
---|
1179 | |
---|
1180 | #define PCINT6_DDR DDRE |
---|
1181 | #define PCINT6_PORT PORTE |
---|
1182 | #define PCINT6_PIN PINE |
---|
1183 | #define PCINT6_BIT 6 |
---|
1184 | |
---|
1185 | #define PCINT7_DDR DDRE |
---|
1186 | #define PCINT7_PORT PORTE |
---|
1187 | #define PCINT7_PIN PINE |
---|
1188 | #define PCINT7_BIT 7 |
---|
1189 | |
---|
1190 | #define SS_DDR DDRB |
---|
1191 | #define SS_PORT PORTB |
---|
1192 | #define SS_PIN PINB |
---|
1193 | #define SS_BIT 0 |
---|
1194 | |
---|
1195 | #define PCINT8_DDR DDRB |
---|
1196 | #define PCINT8_PORT PORTB |
---|
1197 | #define PCINT8_PIN PINB |
---|
1198 | #define PCINT8_BIT 0 |
---|
1199 | |
---|
1200 | #define SCK_DDR DDRB |
---|
1201 | #define SCK_PORT PORTB |
---|
1202 | #define SCK_PIN PINB |
---|
1203 | #define SCK_BIT 1 |
---|
1204 | |
---|
1205 | #define PCINT9_DDR DDRB |
---|
1206 | #define PCINT9_PORT PORTB |
---|
1207 | #define PCINT9_PIN PINB |
---|
1208 | #define PCINT9_BIT 1 |
---|
1209 | |
---|
1210 | #define MOSI_DDR DDRB |
---|
1211 | #define MOSI_PORT PORTB |
---|
1212 | #define MOSI_PIN PINB |
---|
1213 | #define MOSI_BIT 2 |
---|
1214 | |
---|
1215 | #define PCINT10_DDR DDRB |
---|
1216 | #define PCINT10_PORT PORTB |
---|
1217 | #define PCINT10_PIN PINB |
---|
1218 | #define PCINT10_BIT 2 |
---|
1219 | |
---|
1220 | #define MISO_DDR DDRB |
---|
1221 | #define MISO_PORT PORTB |
---|
1222 | #define MISO_PIN PINB |
---|
1223 | #define MISO_BIT 3 |
---|
1224 | |
---|
1225 | #define PCINT11_DDR DDRB |
---|
1226 | #define PCINT11_PORT PORTB |
---|
1227 | #define PCINT11_PIN PINB |
---|
1228 | #define PCINT11_BIT 3 |
---|
1229 | |
---|
1230 | #define OC0_DDR DDRB |
---|
1231 | #define OC0_PORT PORTB |
---|
1232 | #define OC0_PIN PINB |
---|
1233 | #define OC0_BIT 4 |
---|
1234 | |
---|
1235 | #define PCINT12_DDR DDRB |
---|
1236 | #define PCINT12_PORT PORTB |
---|
1237 | #define PCINT12_PIN PINB |
---|
1238 | #define PCINT12_BIT 4 |
---|
1239 | |
---|
1240 | #define OC1A_DDR DDRB |
---|
1241 | #define OC1A_PORT PORTB |
---|
1242 | #define OC1A_PIN PINB |
---|
1243 | #define OC1A_BIT 5 |
---|
1244 | |
---|
1245 | #define PCINT13_DDR DDRB |
---|
1246 | #define PCINT13_PORT PORTB |
---|
1247 | #define PCINT13_PIN PINB |
---|
1248 | #define PCINT13_BIT 5 |
---|
1249 | |
---|
1250 | #define OC1B_DDR DDRB |
---|
1251 | #define OC1B_PORT PORTB |
---|
1252 | #define OC1B_PIN PINB |
---|
1253 | #define OC1B_BIT 6 |
---|
1254 | |
---|
1255 | #define PCINT14_DDR DDRB |
---|
1256 | #define PCINT14_PORT PORTB |
---|
1257 | #define PCINT14_PIN PINB |
---|
1258 | #define PCINT14_BIT 6 |
---|
1259 | |
---|
1260 | #define OC2_DDR DDRB |
---|
1261 | #define OC2_PORT PORTB |
---|
1262 | #define OC2_PIN PINB |
---|
1263 | #define OC2_BIT 7 |
---|
1264 | |
---|
1265 | #define PCINT15_DDR DDRB |
---|
1266 | #define PCINT15_PORT PORTB |
---|
1267 | #define PCINT15_PIN PINB |
---|
1268 | #define PCINT15_BIT 7 |
---|
1269 | |
---|
1270 | #define T1_DDR DDRG |
---|
1271 | #define T1_PORT PORTG |
---|
1272 | #define T1_PIN PING |
---|
1273 | #define T1_BIT 3 |
---|
1274 | |
---|
1275 | #define SEG24_DDR DDRG |
---|
1276 | #define SEG24_PORT PORTG |
---|
1277 | #define SEG24_PIN PING |
---|
1278 | #define SEG24_BIT 3 |
---|
1279 | |
---|
1280 | #define T0_DDR DDRG |
---|
1281 | #define T0_PORT PORTG |
---|
1282 | #define T0_PIN PING |
---|
1283 | #define T0_BIT 4 |
---|
1284 | |
---|
1285 | #define SEG23_DDR DDRG |
---|
1286 | #define SEG23_PORT PORTG |
---|
1287 | #define SEG23_PIN PING |
---|
1288 | #define SEG23_BIT 4 |
---|
1289 | |
---|
1290 | #define ICP/SEG22_DDR DDRD |
---|
1291 | #define ICP/SEG22_PORT PORTD |
---|
1292 | #define ICP/SEG22_PIN PIND |
---|
1293 | #define ICP/SEG22_BIT 0 |
---|
1294 | |
---|
1295 | #define INT0/SEG21_DDR DDRD |
---|
1296 | #define INT0/SEG21_PORT PORTD |
---|
1297 | #define INT0/SEG21_PIN PIND |
---|
1298 | #define INT0/SEG21_BIT 1 |
---|
1299 | |
---|
1300 | #define SEG20_DDR DDRD |
---|
1301 | #define SEG20_PORT PORTD |
---|
1302 | #define SEG20_PIN PIND |
---|
1303 | #define SEG20_BIT 2 |
---|
1304 | |
---|
1305 | #define SEG19_DDR DDRD |
---|
1306 | #define SEG19_PORT PORTD |
---|
1307 | #define SEG19_PIN PIND |
---|
1308 | #define SEG19_BIT 3 |
---|
1309 | |
---|
1310 | #define SEG18_DDR DDRD |
---|
1311 | #define SEG18_PORT PORTD |
---|
1312 | #define SEG18_PIN PIND |
---|
1313 | #define SEG18_BIT 4 |
---|
1314 | |
---|
1315 | #define SEG17_DDR DDRD |
---|
1316 | #define SEG17_PORT PORTD |
---|
1317 | #define SEG17_PIN PIND |
---|
1318 | #define SEG17_BIT 5 |
---|
1319 | |
---|
1320 | #define SEG16_DDR DDRD |
---|
1321 | #define SEG16_PORT PORTD |
---|
1322 | #define SEG16_PIN PIND |
---|
1323 | #define SEG16_BIT 6 |
---|
1324 | |
---|
1325 | #define SEG15_DDR DDRD |
---|
1326 | #define SEG15_PORT PORTD |
---|
1327 | #define SEG15_PIN PIND |
---|
1328 | #define SEG15_BIT 7 |
---|
1329 | |
---|
1330 | #define SEG14_DDR DDRG |
---|
1331 | #define SEG14_PORT PORTG |
---|
1332 | #define SEG14_PIN PING |
---|
1333 | #define SEG14_BIT 0 |
---|
1334 | |
---|
1335 | #define SEG13_DDR DDRG |
---|
1336 | #define SEG13_PORT PORTG |
---|
1337 | #define SEG13_PIN PING |
---|
1338 | #define SEG13_BIT 1 |
---|
1339 | |
---|
1340 | #define SEG12_DDR DDRC |
---|
1341 | #define SEG12_PORT PORTC |
---|
1342 | #define SEG12_PIN PINC |
---|
1343 | #define SEG12_BIT 0 |
---|
1344 | |
---|
1345 | #define SEG11_DDR DDRC |
---|
1346 | #define SEG11_PORT PORTC |
---|
1347 | #define SEG11_PIN PINC |
---|
1348 | #define SEG11_BIT 1 |
---|
1349 | |
---|
1350 | #define SEG10_DDR DDRC |
---|
1351 | #define SEG10_PORT PORTC |
---|
1352 | #define SEG10_PIN PINC |
---|
1353 | #define SEG10_BIT 2 |
---|
1354 | |
---|
1355 | #define SEG9_DDR DDRC |
---|
1356 | #define SEG9_PORT PORTC |
---|
1357 | #define SEG9_PIN PINC |
---|
1358 | #define SEG9_BIT 3 |
---|
1359 | |
---|
1360 | #define SEG8_DDR DDRC |
---|
1361 | #define SEG8_PORT PORTC |
---|
1362 | #define SEG8_PIN PINC |
---|
1363 | #define SEG8_BIT 4 |
---|
1364 | |
---|
1365 | #define SEG7_DDR DDRC |
---|
1366 | #define SEG7_PORT PORTC |
---|
1367 | #define SEG7_PIN PINC |
---|
1368 | #define SEG7_BIT 5 |
---|
1369 | |
---|
1370 | #define SEG6_DDR DDRC |
---|
1371 | #define SEG6_PORT PORTC |
---|
1372 | #define SEG6_PIN PINC |
---|
1373 | #define SEG6_BIT 6 |
---|
1374 | |
---|
1375 | #define SEG5_DDR DDRC |
---|
1376 | #define SEG5_PORT PORTC |
---|
1377 | #define SEG5_PIN PINC |
---|
1378 | #define SEG5_BIT 7 |
---|
1379 | |
---|
1380 | #define SEG4_DDR DDRG |
---|
1381 | #define SEG4_PORT PORTG |
---|
1382 | #define SEG4_PIN PING |
---|
1383 | #define SEG4_BIT 2 |
---|
1384 | |
---|
1385 | #define SEG3_DDR DDRA |
---|
1386 | #define SEG3_PORT PORTA |
---|
1387 | #define SEG3_PIN PINA |
---|
1388 | #define SEG3_BIT 7 |
---|
1389 | |
---|
1390 | #define SEG2_DDR DDRA |
---|
1391 | #define SEG2_PORT PORTA |
---|
1392 | #define SEG2_PIN PINA |
---|
1393 | #define SEG2_BIT 6 |
---|
1394 | |
---|
1395 | #define SEG1_DDR DDRA |
---|
1396 | #define SEG1_PORT PORTA |
---|
1397 | #define SEG1_PIN PINA |
---|
1398 | #define SEG1_BIT 5 |
---|
1399 | |
---|
1400 | #define SEG0_DDR DDRA |
---|
1401 | #define SEG0_PORT PORTA |
---|
1402 | #define SEG0_PIN PINA |
---|
1403 | #define SEG0_BIT 4 |
---|
1404 | |
---|
1405 | #define COM3_DDR DDRA |
---|
1406 | #define COM3_PORT PORTA |
---|
1407 | #define COM3_PIN PINA |
---|
1408 | #define COM3_BIT 3 |
---|
1409 | |
---|
1410 | #define COM2_DDR DDRA |
---|
1411 | #define COM2_PORT PORTA |
---|
1412 | #define COM2_PIN PINA |
---|
1413 | #define COM2_BIT 2 |
---|
1414 | |
---|
1415 | #define COM1_DDR DDRA |
---|
1416 | #define COM1_PORT PORTA |
---|
1417 | #define COM1_PIN PINA |
---|
1418 | #define COM1_BIT 1 |
---|
1419 | |
---|
1420 | #define COM0_DDR DDRA |
---|
1421 | #define COM0_PORT PORTA |
---|
1422 | #define COM0_PIN PINA |
---|
1423 | #define COM0_BIT 0 |
---|
1424 | |
---|
1425 | #define ADC7_DDR DDRF |
---|
1426 | #define ADC7_PORT PORTF |
---|
1427 | #define ADC7_PIN PINF |
---|
1428 | #define ADC7_BIT 7 |
---|
1429 | |
---|
1430 | #define ADC6_DDR DDRF |
---|
1431 | #define ADC6_PORT PORTF |
---|
1432 | #define ADC6_PIN PINF |
---|
1433 | #define ADC6_BIT 6 |
---|
1434 | |
---|
1435 | #define TD0_DDR DDRF |
---|
1436 | #define TD0_PORT PORTF |
---|
1437 | #define TD0_PIN PINF |
---|
1438 | #define TD0_BIT 6 |
---|
1439 | |
---|
1440 | #define ADC5_DDR DDRF |
---|
1441 | #define ADC5_PORT PORTF |
---|
1442 | #define ADC5_PIN PINF |
---|
1443 | #define ADC5_BIT 5 |
---|
1444 | |
---|
1445 | #define ADC4_DDR DDRF |
---|
1446 | #define ADC4_PORT PORTF |
---|
1447 | #define ADC4_PIN PINF |
---|
1448 | #define ADC4_BIT 4 |
---|
1449 | |
---|
1450 | #define ADC3_DDR DDRF |
---|
1451 | #define ADC3_PORT PORTF |
---|
1452 | #define ADC3_PIN PINF |
---|
1453 | #define ADC3_BIT 3 |
---|
1454 | |
---|
1455 | #define ADC2_DDR DDRF |
---|
1456 | #define ADC2_PORT PORTF |
---|
1457 | #define ADC2_PIN PINF |
---|
1458 | #define ADC2_BIT 2 |
---|
1459 | |
---|
1460 | #define ADC1_DDR DDRF |
---|
1461 | #define ADC1_PORT PORTF |
---|
1462 | #define ADC1_PIN PINF |
---|
1463 | #define ADC1_BIT 1 |
---|
1464 | |
---|
1465 | #define ADC0_DDR DDRF |
---|
1466 | #define ADC0_PORT PORTF |
---|
1467 | #define ADC0_PIN PINF |
---|
1468 | #define ADC0_BIT 0 |
---|
1469 | |
---|
1470 | #endif /* _AVR_ATmega169PA_H_ */ |
---|
1471 | |
---|