source: rtems/cpukit/score/cpu/avr/avr/iom169p.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 20.6 KB
Line 
1/* Copyright (c) 2002, 2003, 2004, 2005, 2006
2   Juergen Schilling <juergen.schilling@honeywell.com>
3   Eric B. Weddington <ericw@evcohs.com>
4   Anatoly Sokolov <aesok@post.ru>
5   All rights reserved.
6
7   Redistribution and use in source and binary forms, with or without
8   modification, are permitted provided that the following conditions are met:
9
10   * Redistributions of source code must retain the above copyright
11     notice, this list of conditions and the following disclaimer.
12
13   * Redistributions in binary form must reproduce the above copyright
14     notice, this list of conditions and the following disclaimer in
15     the documentation and/or other materials provided with the
16     distribution.
17
18   * Neither the name of the copyright holders nor the names of
19     contributors may be used to endorse or promote products derived
20     from this software without specific prior written permission.
21
22  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32  POSSIBILITY OF SUCH DAMAGE. */
33
34/* $Id$ */
35
36/* iom169p.h - definitions for ATmega169P */
37
38#ifndef _AVR_IOM169P_H_
39#define _AVR_IOM169P_H_ 1
40
41/* This file should only be included from <avr/io.h>, never directly. */
42
43#ifndef _AVR_IO_H_
44#  error "Include <avr/io.h> instead of this file."
45#endif
46
47#ifndef _AVR_IOXXX_H_
48#  define _AVR_IOXXX_H_ "iom169p.h"
49#else
50#  error "Attempt to include more than one <avr/ioXXX.h> file."
51#endif
52
53/* I/O registers */
54
55/* Port A */
56#define PINA   _SFR_IO8(0x00)
57#define PINA7   7
58#define PINA6   6
59#define PINA5   5
60#define PINA4   4
61#define PINA3   3
62#define PINA2   2
63#define PINA1   1
64#define PINA0   0
65
66#define DDRA   _SFR_IO8(0x01)
67#define DDA7    7
68#define DDA6    6
69#define DDA5    5
70#define DDA4    4
71#define DDA3    3
72#define DDA2    2
73#define DDA1    1
74#define DDA0    0
75
76#define PORTA  _SFR_IO8(0x02)
77#define PA7     7
78#define PA6     6
79#define PA5     5
80#define PA4     4
81#define PA3     3
82#define PA2     2
83#define PA1     1
84#define PA0     0
85
86/* Port B */
87#define PINB   _SFR_IO8(0x03)
88#define PINB7   7
89#define PINB6   6
90#define PINB5   5
91#define PINB4   4
92#define PINB3   3
93#define PINB2   2
94#define PINB1   1
95#define PINB0   0
96
97#define DDRB   _SFR_IO8(0x04)
98#define DDB7    7
99#define DDB6    6
100#define DDB5    5
101#define DDB4    4
102#define DDB3    3
103#define DDB2    2
104#define DDB1    1
105#define DDB0    0
106
107#define PORTB  _SFR_IO8(0x05)
108#define PB7     7
109#define PB6     6
110#define PB5     5
111#define PB4     4
112#define PB3     3
113#define PB2     2
114#define PB1     1
115#define PB0     0
116
117/* Port C */
118#define PINC   _SFR_IO8(0x06)
119#define PINC7   7
120#define PINC6   6
121#define PINC5   5
122#define PINC4   4
123#define PINC3   3
124#define PINC2   2
125#define PINC1   1
126#define PINC0   0
127
128#define DDRC   _SFR_IO8(0x07)
129#define DDC7    7
130#define DDC6    6
131#define DDC5    5
132#define DDC4    4
133#define DDC3    3
134#define DDC2    2
135#define DDC1    1
136#define DDC0    0
137
138#define PORTC  _SFR_IO8(0x08)
139#define PC7      7
140#define PC6      6
141#define PC5      5
142#define PC4      4
143#define PC3      3
144#define PC2      2
145#define PC1      1
146#define PC0      0
147
148/* Port D */
149#define PIND   _SFR_IO8(0x09)
150#define PIND7   7
151#define PIND6   6
152#define PIND5   5
153#define PIND4   4
154#define PIND3   3
155#define PIND2   2
156#define PIND1   1
157#define PIND0   0
158
159#define DDRD   _SFR_IO8(0x0A)
160#define DDD7    7
161#define DDD6    6
162#define DDD5    5
163#define DDD4    4
164#define DDD3    3
165#define DDD2    2
166#define DDD1    1
167#define DDD0    0
168
169#define PORTD  _SFR_IO8(0x0B)
170#define PD7      7
171#define PD6      6
172#define PD5      5
173#define PD4      4
174#define PD3      3
175#define PD2      2
176#define PD1      1
177#define PD0      0
178
179/* Port E */
180#define PINE   _SFR_IO8(0x0C)
181#define PINE7   7
182#define PINE6   6
183#define PINE5   5
184#define PINE4   4
185#define PINE3   3
186#define PINE2   2
187#define PINE1   1
188#define PINE0   0
189
190#define DDRE   _SFR_IO8(0x0D)
191#define DDE7    7
192#define DDE6    6
193#define DDE5    5
194#define DDE4    4
195#define DDE3    3
196#define DDE2    2
197#define DDE1    1
198#define DDE0    0
199
200#define PORTE  _SFR_IO8(0x0E)
201#define PE7     7
202#define PE6     6
203#define PE5     5
204#define PE4     4
205#define PE3     3
206#define PE2     2
207#define PE1     1
208#define PE0     0
209
210/* Port F */
211#define PINF   _SFR_IO8(0x0F)
212#define PINF7   7
213#define PINF6   6
214#define PINF5   5
215#define PINF4   4
216#define PINF3   3
217#define PINF2   2
218#define PINF1   1
219#define PINF0   0
220
221#define DDRF   _SFR_IO8(0x10)
222#define DDF7    7
223#define DDF6    6
224#define DDF5    5
225#define DDF4    4
226#define DDF3    3
227#define DDF2    2
228#define DDF1    1
229#define DDF0    0
230
231#define PORTF  _SFR_IO8(0x11)
232#define PF7     7
233#define PF6     6
234#define PF5     5
235#define PF4     4
236#define PF3     3
237#define PF2     2
238#define PF1     1
239#define PF0     0
240
241/* Port G */
242#define PING   _SFR_IO8(0x12)
243#define PING5   5
244#define PING4   4
245#define PING3   3
246#define PING2   2
247#define PING1   1
248#define PING0   0
249
250#define DDRG   _SFR_IO8(0x13)
251#define DDG4    4
252#define DDG3    3
253#define DDG2    2
254#define DDG1    1
255#define DDG0    0
256
257#define PORTG  _SFR_IO8(0x14)
258#define PG4     4
259#define PG3     3
260#define PG2     2
261#define PG1     1
262#define PG0     0
263
264/* Timer/Counter 0 interrupt Flag Register */
265#define TIFR0  _SFR_IO8(0x15)
266#define OCF0A   1
267#define TOV0    0
268
269/* Timer/Counter 1 interrupt Flag Register */
270#define TIFR1  _SFR_IO8(0x16)
271#define ICF1    5
272#define OCF1B   2
273#define OCF1A   1
274#define TOV1    0
275
276/* Timer/Counter 2 interrupt Flag Register */
277#define TIFR2  _SFR_IO8(0x17)
278#define OCF2A   1
279#define TOV2    0
280
281/* External Interrupt Flag Register */
282#define EIFR   _SFR_IO8(0x1C)
283#define PCIF1  7
284#define PCIF0  6
285#define INTF0  0
286
287/* External Interrupt Mask Register */
288#define EIMSK  _SFR_IO8(0x1D)
289#define PCIE1  7
290#define PCIE0  6
291#define INT0   0
292
293/* General Purpose I/O Register 0 */
294#define GPIOR0 _SFR_IO8(0x1E)
295
296#define EECR   _SFR_IO8(0x1F)
297#define EERIE   3
298#define EEMWE   2
299#define EEWE    1
300#define EERE    0
301
302#define EEDR   _SFR_IO8(0X20)
303
304/* Combine EEARL and EEARH */
305#define EEAR   _SFR_IO16(0x21)
306#define EEARL  _SFR_IO8(0x21)
307#define EEARH  _SFR_IO8(0X22)
308
309/* 6-char sequence denoting where to find the EEPROM registers in memory space.
310   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
311   subroutines.
312   First two letters:  EECR address.
313   Second two letters: EEDR address.
314   Last two letters:   EEAR address.  */
315#define __EEPROM_REG_LOCATIONS__ 1F2021
316
317/* General Timer/Counter Control Register */
318#define GTCCR  _SFR_IO8(0x23)
319#define TSM    7
320#define PSR2   1
321#define PSR10  0
322
323/* Timer/Counter Control Register A */
324#define TCCR0A _SFR_IO8(0x24)
325#define FOC0A   7
326#define WGM00   6
327#define COM0A1  5
328#define COM0A0  4
329#define WGM01   3
330#define CS02    2
331#define CS01    1
332#define CS00    0
333
334/* Timer/Counter Register */
335#define TCNT0  _SFR_IO8(0x26)
336
337/* Output Compare Register A */
338#define OCR0A  _SFR_IO8(0x27)
339
340/* General Purpose I/O Register 1 */
341#define GPIOR1 _SFR_IO8(0x2A)
342
343/* General Purpose I/O Register 2 */
344#define GPIOR2 _SFR_IO8(0x2B)
345
346/* SPI Control Register */
347#define SPCR   _SFR_IO8(0x2C)
348#define SPIE    7
349#define SPE     6
350#define DORD    5
351#define MSTR    4
352#define CPOL    3
353#define CPHA    2
354#define SPR1    1
355#define SPR0    0
356
357/* SPI Status Register */
358#define SPSR   _SFR_IO8(0x2D)
359#define SPIF    7
360#define WCOL    6
361#define SPI2X   0
362
363/* SPI Data Register */
364#define SPDR   _SFR_IO8(0x2E)
365
366/* Analog Comperator Control and Status Register */
367#define ACSR   _SFR_IO8(0x30)
368#define ACD     7
369#define ACBG    6
370#define ACO     5
371#define ACI     4
372#define ACIE    3
373#define ACIC    2
374#define ACIS1   1
375#define ACIS0   0
376
377/* On-chip Debug Register */
378#define OCDR   _SFR_IO8(0x31)
379#define IDRD   7
380#define OCDR7  7
381#define OCDR6  6
382#define OCDR5  5
383#define OCDR4  4
384#define OCDR3  3
385#define OCDR2  2
386#define OCDR1  1
387#define OCDR0  0
388
389/* Sleep Mode Control Register */
390#define SMCR   _SFR_IO8(0x33)
391#define SM2    3
392#define SM1    2
393#define SM0    1
394#define SE     0
395
396/* MCU Status Register */
397#define MCUSR  _SFR_IO8(0x34)
398#define JTRF   4
399#define WDRF   3
400#define BORF   2
401#define EXTRF  1
402#define PORF   0
403
404/* MCU Control Rgeister */
405#define MCUCR  _SFR_IO8(0x35)
406#define JTD    7
407#define PUD    4
408#define IVSEL  1
409#define IVCE   0
410
411/* Store Program Memory Control and Status Register */
412#define SPMCSR _SFR_IO8(0x37)
413#define SPMIE  7
414#define RWWSB  6
415#define RWWSRE 4
416#define BLBSET 3
417#define PGWRT  2
418#define PGERS  1
419#define SPMEN  0
420
421/* Watchdog Timer Control Register */
422#define WDTCR  _SFR_MEM8(0x60)
423#define WDCE    4
424#define WDE     3
425#define WDP2    2
426#define WDP1    1
427#define WDP0    0
428
429/* Clock Prescale Register */
430#define CLKPR  _SFR_MEM8(0x61)
431#define CLKPCE 7
432#define CLKPS3 3
433#define CLKPS2 2
434#define CLKPS1 1
435#define CLKPS0 0
436
437#define PRR    _SFR_MEM8(0x64)
438#define PRADC       0
439#define PRUSART0    1
440#define PRSPI       2
441#define PRTIM1      3
442#define PRLCD       4
443
444/* Oscillator Calibration Register */
445#define OSCCAL _SFR_MEM8(0x66)
446
447/* External Interrupt Control Register A */
448#define EICRA  _SFR_MEM8(0x69)
449#define ISC01  1
450#define ISC00  0
451
452/* Pin Change Mask Register */
453#define PCMSK   _SFR_MEM16(0x6B)
454
455#define PCMSK0  _SFR_MEM8(0x6B)
456#define PCINT7  7
457#define PCINT6  6
458#define PCINT5  5
459#define PCINT4  4
460#define PCINT3  3
461#define PCINT2  2
462#define PCINT1  1
463#define PCINT0  0
464
465#define PCMSK1  _SFR_MEM8(0x6C)
466#define PCINT15 7
467#define PCINT14 6
468#define PCINT13 5
469#define PCINT12 4
470#define PCINT11 3
471#define PCINT10 2
472#define PCINT9  1
473#define PCINT8  0
474
475/* Timer/Counter 0 Interrupt Mask Register */
476#define TIMSK0 _SFR_MEM8(0x6E)
477#define OCIE0A 1
478#define TOIE0  0
479
480/* Timer/Counter 1 Interrupt Mask Register */
481#define TIMSK1 _SFR_MEM8(0x6F)
482#define ICIE1  5
483#define OCIE1B 2
484#define OCIE1A 1
485#define TOIE1  0
486
487/* Timer/Counter 2 Interrupt Mask Register */
488#define TIMSK2 _SFR_MEM8(0x70)
489#define OCIE2A 1
490#define TOIE2  0
491
492/* ADC Data Register */
493#ifndef __ASSEMBLER__
494#define ADC    _SFR_MEM16(0x78)
495#endif
496#define ADCW   _SFR_MEM16(0x78)
497#define ADCL   _SFR_MEM8(0x78)
498#define ADCH   _SFR_MEM8(0x79)
499
500/* ADC Control and Status Register A */
501#define ADCSRA _SFR_MEM8(0x7A)
502#define ADEN   7
503#define ADSC   6
504#define ADATE  5
505#define ADIF   4
506#define ADIE   3
507#define ADPS2  2
508#define ADPS1  1
509#define ADPS0  0
510
511
512/* ADC Control and Status Register B */
513#define ADCSRB _SFR_MEM8(0x7B)
514#define ACME   6
515#define ADTS2  2
516#define ADTS1  1
517#define ADTS0  0
518
519/* ADC Multiplex Selection Register */
520#define ADMUX  _SFR_MEM8(0x7C)
521/* ADMUX */
522#define REFS1  7
523#define REFS0  6
524#define ADLAR  5
525#define MUX4   4
526#define MUX3   3
527#define MUX2   2
528#define MUX1   1
529#define MUX0   0
530
531/* Digital Input Disable Register 0 */
532#define DIDR0  _SFR_MEM8(0x7E)
533#define ADC7D  7
534#define ADC6D  6
535#define ADC5D  5
536#define ADC4D  4
537#define ADC3D  3
538#define ADC2D  2
539#define ADC1D  1
540#define ADC0D  0
541
542/* Digital Input Disable Register 1 */
543#define DIDR1  _SFR_MEM8(0x7F)
544#define AIN1D  1
545#define AIN0D  0
546
547/* Timer/Counter1 Control Register A */
548#define TCCR1A _SFR_MEM8(0x80)
549#define COM1A1  7
550#define COM1A0  6
551#define COM1B1  5
552#define COM1B0  4
553#define WGM11   1
554#define WGM10   0
555
556/* Timer/Counter1 Control Register B */
557#define TCCR1B _SFR_MEM8(0x81)
558#define ICNC1   7
559#define ICES1   6
560#define WGM13   4
561#define WGM12   3
562#define CS12    2
563#define CS11    1
564#define CS10    0
565
566/* Timer/Counter1 Control Register C */
567#define TCCR1C _SFR_MEM8(0x82)
568#define FOC1A  7
569#define FOC1B  6
570
571/* Timer/Counter1 Register */
572#define TCNT1  _SFR_MEM16(0x84)
573#define TCNT1L _SFR_MEM8(0x84)
574#define TCNT1H _SFR_MEM8(0x85)
575
576/* Timer/Counter1 Input Capture Register */
577#define ICR1   _SFR_MEM16(0x86)
578#define ICR1L  _SFR_MEM8(0x86)
579#define ICR1H  _SFR_MEM8(0x87)
580
581/* Timer/Counter1 Output Compare Register A */
582#define OCR1A  _SFR_MEM16(0x88)
583#define OCR1AL _SFR_MEM8(0x88)
584#define OCR1AH _SFR_MEM8(0x89)
585
586/* Timer/Counter1 Output Compare Registare B */
587#define OCR1B  _SFR_MEM16(0x8A)
588#define OCR1BL _SFR_MEM8(0x8A)
589#define OCR1BH _SFR_MEM8(0x8B)
590
591/* Timer/Counter2 Control Register A */
592#define TCCR2A _SFR_MEM8(0xB0)
593#define FOC2A   7
594#define WGM20   6
595#define COM2A1  5
596#define COM2A0  4
597#define WGM21   3
598#define CS22    2
599#define CS21    1
600#define CS20    0
601
602/* Timer/Counter2 Register */
603#define TCNT2  _SFR_MEM8(0xB2)
604
605/* Timer/Counter2 Output Compare Register */
606#define OCR2A  _SFR_MEM8(0xB3)
607
608/* Asynchronous Status Register */
609#define ASSR   _SFR_MEM8(0xB6)
610#define EXCLK   4
611#define AS2     3
612#define TCN2UB  2
613#define OCR2UB  1
614#define TCR2UB  0
615
616/* USI Control Register */
617#define USICR  _SFR_MEM8(0xB8)
618#define USISIE 7
619#define USIOIE 6
620#define USIWM1 5
621#define USIWM0 4
622#define USICS1 3
623#define USICS0 2
624#define USICLK 1
625#define USITC  0
626
627/* USI Status Register */
628#define USISR  _SFR_MEM8(0xB9)
629#define USISIF  7
630#define USIOIF  6
631#define USIPF   5
632#define USIDC   4
633#define USICNT3 3
634#define USICNT2 2
635#define USICNT1 1
636#define USICNT0 0
637
638/* USI Data Register */
639#define USIDR  _SFR_MEM8(0xBA)
640
641/* USART0 Control and Status Register A */
642#define UCSR0A  _SFR_MEM8(0xC0)
643#define RXC0    7
644#define TXC0    6
645#define UDRE0   5
646#define FE0     4
647#define DOR0    3
648#define UPE0    2
649#define U2X0    1
650#define MPCM0   0
651
652/* USART0 Control and Status Register B */
653#define UCSR0B  _SFR_MEM8(0xC1)
654#define RXCIE0  7
655#define TXCIE0  6
656#define UDRIE0  5
657#define RXEN0   4
658#define TXEN0   3
659#define UCSZ02  2
660#define RXB80   1
661#define TXB80   0
662
663/* USART0 Control and Status Register C */
664#define UCSR0C  _SFR_MEM8(0xC2)
665#define UMSEL0  6
666#define UPM01   5
667#define UPM00   4
668#define USBS0   3
669#define UCSZ01  2
670#define UCSZ00  1
671#define UCPOL0  0
672
673/* USART0 Baud Rate Register */
674#define UBRR0   _SFR_MEM16(0xC4)
675#define UBRR0L  _SFR_MEM8(0xC4)
676#define UBRR0H  _SFR_MEM8(0xC5)
677
678/* USART0 I/O Data Register */
679#define UDR0    _SFR_MEM8(0xC6)
680
681/* LCD Control and Status Register A */
682#define LCDCRA  _SFR_MEM8(0xE4)
683#define LCDEN   7
684#define LCDAB   6
685#define LCDIF   4
686#define LCDIE   3
687#define LCDBD   2
688#define LCDCCD  1
689#define LCDBL   0
690
691/* LCD Control and Status Register B */
692#define LCDCRB  _SFR_MEM8(0xE5)
693#define LCDCS   7
694#define LCD2B   6
695#define LCDMUX1 5
696#define LCDMUX0 4
697#define LCDPM2  2
698#define LCDPM1  1
699#define LCDPM0  0
700
701/* LCD Frame Rate Register */
702#define LCDFRR  _SFR_MEM8(0xE6)
703#define LCDPS2  6
704#define LCDPS1  5
705#define LCDPS0  4
706#define LCDCD2  2
707#define LCDCD1  1
708#define LCDCD0  0
709
710/* LCD Contrast Control Register */
711#define LCDCCR  _SFR_MEM8(0xE7)
712#define LCDDC2  7
713#define LCDDC1  6
714#define LCDDC0  5
715#define LCDMDT  4
716#define LCDCC3  3
717#define LCDCC2  2
718#define LCDCC1  1
719#define LCDCC0  0
720
721/* LCD Memory mapping */
722#define LCDDR0 _SFR_MEM8(0xEC)
723#define SEG007 7
724#define SEG006 6
725#define SEG005 5
726#define SEG004 4
727#define SEG003 3
728#define SEG002 2
729#define SEG001 1
730#define SEG000 0
731
732#define LCDDR1 _SFR_MEM8(0xED)
733#define SEG015 7
734#define SEG014 6
735#define SEG013 5
736#define SEG012 4
737#define SEG011 3
738#define SEG010 2
739#define SEG009 1
740#define SEG008 0
741
742#define LCDDR2 _SFR_MEM8(0xEE)
743#define SEG023 7
744#define SEG022 6
745#define SEG021 5
746#define SEG020 4
747#define SEG019 3
748#define SEG018 2
749#define SEG017 1
750#define SEG016 0
751
752#define LCDDR3 _SFR_MEM8(0xEF)
753#define SEG024 0
754
755#define LCDDR5 _SFR_MEM8(0xF1)
756#define SEG107 7
757#define SEG106 6
758#define SEG105 5
759#define SEG104 4
760#define SEG103 3
761#define SEG102 2
762#define SEG101 1
763#define SEG100 0
764
765#define LCDDR6 _SFR_MEM8(0xF2)
766#define SEG115 7
767#define SEG114 6
768#define SEG113 5
769#define SEG112 4
770#define SEG111 3
771#define SEG110 2
772#define SEG109 1
773#define SEG108 0
774
775#define LCDDR7 _SFR_MEM8(0xF3)
776#define SEG123 7
777#define SEG122 6
778#define SEG121 5
779#define SEG120 4
780#define SEG119 3
781#define SEG118 2
782#define SEG117 1
783#define SEG116 0
784
785#define LCDDR8 _SFR_MEM8(0xF4)
786#define SEG124 0
787
788#define LCDDR10 _SFR_MEM8(0xF6)
789#define SEG207 7
790#define SEG206 6
791#define SEG205 5
792#define SEG204 4
793#define SEG203 3
794#define SEG202 2
795#define SEG201 1
796#define SEG200 0
797
798#define LCDDR11 _SFR_MEM8(0xF7)
799#define SEG215 7
800#define SEG214 6
801#define SEG213 5
802#define SEG212 4
803#define SEG211 3
804#define SEG210 2
805#define SEG209 1
806#define SEG208 0
807
808#define LCDDR12 _SFR_MEM8(0xF8)
809#define SEG223 7
810#define SEG222 6
811#define SEG221 5
812#define SEG220 4
813#define SEG219 3
814#define SEG218 2
815#define SEG217 1
816#define SEG216 0
817
818#define LCDDR13 _SFR_MEM8(0xF9)
819#define SEG224 0
820
821#define LCDDR15 _SFR_MEM8(0xFB)
822#define SEG307 7
823#define SEG306 6
824#define SEG305 5
825#define SEG304 4
826#define SEG303 3
827#define SEG302 2
828#define SEG301 1
829#define SEG300 0
830
831#define LCDDR16 _SFR_MEM8(0xFC)
832#define SEG315 7
833#define SEG314 6
834#define SEG313 5
835#define SEG312 4
836#define SEG311 3
837#define SEG310 2
838#define SEG309 1
839#define SEG308 0
840
841#define LCDDR17 _SFR_MEM8(0xFD)
842#define SEG323 7
843#define SEG322 6
844#define SEG321 5
845#define SEG320 4
846#define SEG319 3
847#define SEG318 2
848#define SEG317 1
849#define SEG316 0
850
851#define LCDDR18 _SFR_MEM8(0xFE)
852#define SEG324 0
853
854/* LCDDR0-18 */
855#define SEG24  0
856
857#define SEG23  7
858#define SEG22  6
859#define SEG21  5
860#define SEG20  4
861#define SEG19  3
862#define SEG18  2
863#define SEG17  1
864#define SEG16  0
865
866#define SEG15  7
867#define SEG14  6
868#define SEG13  5
869#define SEG12  4
870#define SEG11  3
871#define SEG10  2
872#define SEG9   1
873#define SEG8   0
874
875#define SEG7   7
876#define SEG6   6
877#define SEG5   5
878#define SEG4   4
879#define SEG3   3
880#define SEG2   2
881#define SEG1   1
882#define SEG0   0
883
884/* Interrupt vectors */
885
886/* External Interrupt Request 0 */
887#define INT0_vect                       _VECTOR(1)
888#define SIG_INTERRUPT0                  _VECTOR(1)
889
890/* Pin Change Interrupt Request 0 */
891#define PCINT0_vect                     _VECTOR(2)
892#define SIG_PIN_CHANGE0                 _VECTOR(2)
893
894/* Pin Change Interrupt Request 1 */
895#define PCINT1_vect                     _VECTOR(3)
896#define SIG_PIN_CHANGE1                 _VECTOR(3)
897
898/* Timer/Counter2 Compare Match */
899#define TIMER2_COMP_vect                _VECTOR(4)
900#define SIG_OUTPUT_COMPARE2             _VECTOR(4)
901
902/* Timer/Counter2 Overflow */
903#define TIMER2_OVF_vect                 _VECTOR(5)
904#define SIG_OVERFLOW2                   _VECTOR(5)
905
906/* Timer/Counter1 Capture Event */
907#define TIMER1_CAPT_vect                _VECTOR(6)
908#define SIG_INPUT_CAPTURE1              _VECTOR(6)
909
910/* Timer/Counter1 Compare Match A */
911#define TIMER1_COMPA_vect               _VECTOR(7)
912#define SIG_OUTPUT_COMPARE1A            _VECTOR(7)
913
914/* Timer/Counter Compare Match B */
915#define TIMER1_COMPB_vect               _VECTOR(8)
916#define SIG_OUTPUT_COMPARE1B            _VECTOR(8)
917
918/* Timer/Counter1 Overflow */
919#define TIMER1_OVF_vect                 _VECTOR(9)
920#define SIG_OVERFLOW1                   _VECTOR(9)
921
922/* Timer/Counter0 Compare Match */
923#define TIMER0_COMP_vect                _VECTOR(10)
924#define SIG_OUTPUT_COMPARE0             _VECTOR(10)
925
926/* Timer/Counter0 Overflow */
927#define TIMER0_OVF_vect                 _VECTOR(11)
928#define SIG_OVERFLOW0                   _VECTOR(11)
929
930/* SPI Serial Transfer Complete */
931#define SPI_STC_vect                    _VECTOR(12)
932#define SIG_SPI                         _VECTOR(12)
933
934/* USART0, Rx Complete */
935#define USART0_RX_vect                  _VECTOR(13)
936#define SIG_USART_RECV                  _VECTOR(13)
937
938/* USART0 Data register Empty */
939#define USART0_UDRE_vect                _VECTOR(14)
940#define SIG_USART_DATA                  _VECTOR(14)
941
942/* USART0, Tx Complete */
943#define USART0_TX_vect                  _VECTOR(15)
944#define SIG_USART_TRANS                 _VECTOR(15)
945
946/* USI Start Condition */
947#define USI_START_vect                  _VECTOR(16)
948#define SIG_USI_START                   _VECTOR(16)
949
950/* USI Overflow */
951#define USI_OVERFLOW_vect               _VECTOR(17)
952#define SIG_USI_OVERFLOW                _VECTOR(17)
953
954/* Analog Comparator */
955#define ANALOG_COMP_vect                _VECTOR(18)
956#define SIG_COMPARATOR                  _VECTOR(18)
957
958/* ADC Conversion Complete */
959#define ADC_vect                        _VECTOR(19)
960#define SIG_ADC                         _VECTOR(19)
961
962/* EEPROM Ready */
963#define EE_READY_vect                   _VECTOR(20)
964#define SIG_EEPROM_READY                _VECTOR(20)
965
966/* Store Program Memory Read */
967#define SPM_READY_vect                  _VECTOR(21)
968#define SIG_SPM_READY                   _VECTOR(21)
969
970/* LCD Start of Frame */
971#define LCD_vect                        _VECTOR(22)
972#define SIG_LCD                         _VECTOR(22)
973
974#define _VECTORS_SIZE 92
975
976/* Constants */
977#define SPM_PAGESIZE 128
978#define RAMEND          0x4FF
979#define XRAMEND         RAMEND
980#define E2END           0x1FF
981#define E2PAGESIZE  4
982#define FLASHEND        0x3FFF
983
984
985/* Fuses */
986
987#define FUSE_MEMORY_SIZE 3
988
989/* Low Fuse Byte */
990#define FUSE_CKSEL0      (unsigned char)~_BV(0)
991#define FUSE_CKSEL1      (unsigned char)~_BV(1)
992#define FUSE_CKSEL2      (unsigned char)~_BV(2)
993#define FUSE_CKSEL3      (unsigned char)~_BV(3)
994#define FUSE_SUT0        (unsigned char)~_BV(4)
995#define FUSE_SUT1        (unsigned char)~_BV(5)
996#define FUSE_CKOUT       (unsigned char)~_BV(6)
997#define FUSE_CKDIV8      (unsigned char)~_BV(7)
998#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
999
1000/* High Fuse Byte */
1001#define FUSE_BOOTRST     (unsigned char)~_BV(0)
1002#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
1003#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
1004#define FUSE_EESAVE      (unsigned char)~_BV(3)
1005#define FUSE_WDTON       (unsigned char)~_BV(4)
1006#define FUSE_SPIEN       (unsigned char)~_BV(5)
1007#define FUSE_JTAGEN      (unsigned char)~_BV(6)
1008#define FUSE_OCDEN       (unsigned char)~_BV(7)
1009#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
1010
1011/* Extended Fuse Byte */
1012#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
1013#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
1014#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
1015#define EFUSE_DEFAULT (0xFF)
1016
1017
1018/* Lock Bits */
1019#define __LOCK_BITS_EXIST
1020#define __BOOT_LOCK_BITS_0_EXIST
1021#define __BOOT_LOCK_BITS_1_EXIST
1022
1023
1024/* Signature */
1025#define SIGNATURE_0 0x1E
1026#define SIGNATURE_1 0x94
1027#define SIGNATURE_2 0x05
1028
1029
1030#endif  /* _AVR_IOM169P_H_ */
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