1 | /* Copyright (c) 2002, 2003, 2004, 2005 |
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2 | Juergen Schilling <juergen.schilling@honeywell.com> |
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3 | Eric B. Weddington |
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4 | All rights reserved. |
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5 | |
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6 | Redistribution and use in source and binary forms, with or without |
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7 | modification, are permitted provided that the following conditions are met: |
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8 | |
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9 | * Redistributions of source code must retain the above copyright |
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10 | notice, this list of conditions and the following disclaimer. |
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11 | |
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12 | * Redistributions in binary form must reproduce the above copyright |
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13 | notice, this list of conditions and the following disclaimer in |
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14 | the documentation and/or other materials provided with the |
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15 | distribution. |
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16 | |
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17 | * Neither the name of the copyright holders nor the names of |
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18 | contributors may be used to endorse or promote products derived |
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19 | from this software without specific prior written permission. |
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20 | |
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21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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24 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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31 | POSSIBILITY OF SUCH DAMAGE. */ |
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32 | |
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33 | /* $Id$ */ |
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34 | |
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35 | /* iom169.h - definitions for ATmega169 */ |
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36 | |
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37 | /* This should be up to date with data sheet version 2514J-AVR-12/03. */ |
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38 | |
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39 | #ifndef _AVR_IOM169_H_ |
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40 | #define _AVR_IOM169_H_ 1 |
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41 | |
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42 | /* This file should only be included from <avr/io.h>, never directly. */ |
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43 | |
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44 | #ifndef _AVR_IO_H_ |
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45 | # error "Include <avr/io.h> instead of this file." |
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46 | #endif |
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47 | |
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48 | #ifndef _AVR_IOXXX_H_ |
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49 | # define _AVR_IOXXX_H_ "iom169.h" |
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50 | #else |
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51 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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52 | #endif |
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53 | |
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54 | /* I/O registers */ |
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55 | |
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56 | /* Port A */ |
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57 | #define PINA _SFR_IO8(0x00) |
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58 | #define DDRA _SFR_IO8(0x01) |
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59 | #define PORTA _SFR_IO8(0x02) |
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60 | |
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61 | /* Port B */ |
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62 | #define PINB _SFR_IO8(0x03) |
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63 | #define DDRB _SFR_IO8(0x04) |
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64 | #define PORTB _SFR_IO8(0x05) |
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65 | |
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66 | /* Port C */ |
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67 | #define PINC _SFR_IO8(0x06) |
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68 | #define DDRC _SFR_IO8(0x07) |
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69 | #define PORTC _SFR_IO8(0x08) |
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70 | |
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71 | /* Port D */ |
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72 | #define PIND _SFR_IO8(0x09) |
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73 | #define DDRD _SFR_IO8(0x0A) |
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74 | #define PORTD _SFR_IO8(0x0B) |
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75 | |
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76 | /* Port E */ |
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77 | #define PINE _SFR_IO8(0x0C) |
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78 | #define DDRE _SFR_IO8(0x0D) |
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79 | #define PORTE _SFR_IO8(0x0E) |
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80 | |
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81 | /* Port F */ |
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82 | #define PINF _SFR_IO8(0x0F) |
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83 | #define DDRF _SFR_IO8(0x10) |
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84 | #define PORTF _SFR_IO8(0x11) |
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85 | |
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86 | /* Port G */ |
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87 | #define PING _SFR_IO8(0x12) |
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88 | #define DDRG _SFR_IO8(0x13) |
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89 | #define PORTG _SFR_IO8(0x14) |
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90 | |
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91 | /* Timer/Counter 0 interrupt Flag Register */ |
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92 | #define TIFR0 _SFR_IO8(0x15) |
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93 | |
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94 | /* Timer/Counter 1 interrupt Flag Register */ |
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95 | #define TIFR1 _SFR_IO8(0x16) |
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96 | |
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97 | /* Timer/Counter 2 interrupt Flag Register */ |
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98 | #define TIFR2 _SFR_IO8(0x17) |
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99 | |
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100 | /* External Interrupt Flag Register */ |
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101 | #define EIFR _SFR_IO8(0x1C) |
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102 | |
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103 | /* External Interrupt Mask Register */ |
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104 | #define EIMSK _SFR_IO8(0x1D) |
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105 | |
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106 | /* General Purpose I/O Register 0 */ |
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107 | #define GPIOR0 _SFR_IO8(0x1E) |
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108 | |
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109 | #define EECR _SFR_IO8(0x1F) |
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110 | |
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111 | #define EEDR _SFR_IO8(0X20) |
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112 | |
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113 | /* Combine EEARL and EEARH */ |
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114 | #define EEAR _SFR_IO16(0x21) |
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115 | #define EEARL _SFR_IO8(0x21) |
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116 | #define EEARH _SFR_IO8(0X22) |
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117 | |
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118 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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119 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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120 | subroutines. |
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121 | First two letters: EECR address. |
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122 | Second two letters: EEDR address. |
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123 | Last two letters: EEAR address. */ |
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124 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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125 | |
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126 | /* General Timer/Counter Control Register */ |
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127 | #define GTCCR _SFR_IO8(0x23) |
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128 | |
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129 | /* Timer/Counter Control Register A */ |
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130 | #define TCCR0A _SFR_IO8(0x24) |
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131 | |
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132 | /* Timer/Counter Register */ |
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133 | #define TCNT0 _SFR_IO8(0x26) |
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134 | |
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135 | /* Output Compare Register A */ |
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136 | #define OCR0A _SFR_IO8(0x27) |
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137 | |
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138 | /* General Purpose I/O Register 1 */ |
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139 | #define GPIOR1 _SFR_IO8(0x2A) |
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140 | |
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141 | /* General Purpose I/O Register 2 */ |
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142 | #define GPIOR2 _SFR_IO8(0x2B) |
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143 | |
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144 | /* SPI Control Register */ |
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145 | #define SPCR _SFR_IO8(0x2C) |
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146 | |
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147 | /* SPI Status Register */ |
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148 | #define SPSR _SFR_IO8(0x2D) |
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149 | |
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150 | /* SPI Data Register */ |
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151 | #define SPDR _SFR_IO8(0x2E) |
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152 | |
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153 | /* Analog Comperator Control and Status Register */ |
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154 | #define ACSR _SFR_IO8(0x30) |
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155 | |
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156 | /* On-chip Debug Register */ |
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157 | #define OCDR _SFR_IO8(0x31) |
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158 | |
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159 | /* Sleep Mode Control Register */ |
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160 | #define SMCR _SFR_IO8(0x33) |
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161 | |
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162 | /* MCU Status Register */ |
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163 | #define MCUSR _SFR_IO8(0x34) |
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164 | |
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165 | /* MCU Control Rgeister */ |
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166 | #define MCUCR _SFR_IO8(0x35) |
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167 | |
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168 | /* Store Program Memory Control and Status Register */ |
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169 | #define SPMCSR _SFR_IO8(0x37) |
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170 | |
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171 | /* Watchdog Timer Control Register */ |
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172 | #define WDTCR _SFR_MEM8(0x60) |
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173 | |
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174 | /* Clock Prescale Register */ |
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175 | #define CLKPR _SFR_MEM8(0x61) |
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176 | |
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177 | #define PRR _SFR_MEM8(0x64) |
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178 | #define PRADC 0 |
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179 | #define PRUSART0 1 |
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180 | #define PRSPI 2 |
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181 | #define PRTIM1 3 |
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182 | #define PRLCD 4 |
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183 | |
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184 | /* Oscillator Calibration Register */ |
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185 | #define OSCCAL _SFR_MEM8(0x66) |
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186 | |
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187 | /* External Interrupt Control Register A */ |
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188 | #define EICRA _SFR_MEM8(0x69) |
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189 | |
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190 | /* Pin Change Mask Register */ |
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191 | #define PCMSK _SFR_MEM16(0x6B) |
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192 | #define PCMSK0 _SFR_MEM8(0x6B) |
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193 | #define PCMSK1 _SFR_MEM8(0x6C) |
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194 | |
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195 | /* Timer/Counter 0 Interrupt Mask Register */ |
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196 | #define TIMSK0 _SFR_MEM8(0x6E) |
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197 | |
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198 | /* Timer/Counter 1 Interrupt Mask Register */ |
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199 | #define TIMSK1 _SFR_MEM8(0x6F) |
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200 | |
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201 | /* Timer/Counter 2 Interrupt Mask Register */ |
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202 | #define TIMSK2 _SFR_MEM8(0x70) |
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203 | |
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204 | /* ADC Data Register */ |
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205 | #ifndef __ASSEMBLER__ |
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206 | #define ADC _SFR_MEM16(0x78) |
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207 | #endif |
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208 | #define ADCW _SFR_MEM16(0x78) |
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209 | #define ADCL _SFR_MEM8(0x78) |
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210 | #define ADCH _SFR_MEM8(0x79) |
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211 | |
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212 | /* ADC Control and Status Register A */ |
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213 | #define ADCSRA _SFR_MEM8(0x7A) |
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214 | |
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215 | /* ADC Control and Status Register B */ |
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216 | #define ADCSRB _SFR_MEM8(0x7B) |
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217 | |
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218 | /* ADC Multiplex Selection Register */ |
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219 | #define ADMUX _SFR_MEM8(0x7C) |
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220 | |
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221 | /* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet |
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222 | (2514D-AVR-01/03), but seem to be correct in the discussions of the |
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223 | registers. */ |
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224 | |
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225 | /* Digital Input Disable Register 0 */ |
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226 | #define DIDR0 _SFR_MEM8(0x7E) |
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227 | |
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228 | /* Digital Input Disable Register 1 */ |
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229 | #define DIDR1 _SFR_MEM8(0x7F) |
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230 | |
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231 | /* Timer/Counter1 Control Register A */ |
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232 | #define TCCR1A _SFR_MEM8(0x80) |
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233 | |
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234 | /* Timer/Counter1 Control Register B */ |
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235 | #define TCCR1B _SFR_MEM8(0x81) |
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236 | |
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237 | /* Timer/Counter1 Control Register C */ |
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238 | #define TCCR1C _SFR_MEM8(0x82) |
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239 | |
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240 | /* Timer/Counter1 Register */ |
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241 | #define TCNT1 _SFR_MEM16(0x84) |
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242 | #define TCNT1L _SFR_MEM8(0x84) |
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243 | #define TCNT1H _SFR_MEM8(0x85) |
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244 | |
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245 | /* Timer/Counter1 Input Capture Register */ |
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246 | #define ICR1 _SFR_MEM16(0x86) |
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247 | #define ICR1L _SFR_MEM8(0x86) |
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248 | #define ICR1H _SFR_MEM8(0x87) |
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249 | |
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250 | /* Timer/Counter1 Output Compare Register A */ |
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251 | #define OCR1A _SFR_MEM16(0x88) |
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252 | #define OCR1AL _SFR_MEM8(0x88) |
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253 | #define OCR1AH _SFR_MEM8(0x89) |
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254 | |
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255 | /* Timer/Counter1 Output Compare Registare B */ |
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256 | #define OCR1B _SFR_MEM16(0x8A) |
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257 | #define OCR1BL _SFR_MEM8(0x8A) |
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258 | #define OCR1BH _SFR_MEM8(0x8B) |
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259 | |
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260 | /* Timer/Counter2 Control Register A */ |
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261 | #define TCCR2A _SFR_MEM8(0xB0) |
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262 | |
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263 | /* Timer/Counter2 Register */ |
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264 | #define TCNT2 _SFR_MEM8(0xB2) |
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265 | |
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266 | /* Timer/Counter2 Output Compare Register */ |
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267 | #define OCR2A _SFR_MEM8(0xB3) |
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268 | |
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269 | /* Asynchronous Status Register */ |
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270 | #define ASSR _SFR_MEM8(0xB6) |
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271 | |
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272 | /* USI Control Register */ |
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273 | #define USICR _SFR_MEM8(0xB8) |
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274 | |
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275 | /* USI Status Register */ |
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276 | #define USISR _SFR_MEM8(0xB9) |
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277 | |
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278 | /* USI Data Register */ |
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279 | #define USIDR _SFR_MEM8(0xBA) |
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280 | |
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281 | /* USART0 Control and Status Register A */ |
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282 | #define UCSRA _SFR_MEM8(0xC0) |
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283 | |
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284 | /* USART0 Control and Status Register B */ |
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285 | #define UCSRB _SFR_MEM8(0xC1) |
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286 | |
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287 | /* USART0 Control and Status Register C */ |
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288 | #define UCSRC _SFR_MEM8(0xC2) |
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289 | |
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290 | /* USART0 Baud Rate Register */ |
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291 | #define UBRR _SFR_MEM16(0xC4) |
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292 | #define UBRRL _SFR_MEM8(0xC4) |
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293 | #define UBRRH _SFR_MEM8(0xC5) |
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294 | |
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295 | /* USART0 I/O Data Register */ |
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296 | #define UDR _SFR_MEM8(0xC6) |
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297 | |
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298 | /* LCD Control and Status Register A */ |
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299 | #define LCDCRA _SFR_MEM8(0xE4) |
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300 | |
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301 | /* LCD Control and Status Register B */ |
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302 | #define LCDCRB _SFR_MEM8(0xE5) |
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303 | |
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304 | /* LCD Frame Rate Register */ |
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305 | #define LCDFRR _SFR_MEM8(0xE6) |
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306 | |
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307 | /* LCD Contrast Control Register */ |
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308 | #define LCDCCR _SFR_MEM8(0xE7) |
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309 | |
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310 | /* LCD Memory mapping */ |
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311 | #define LCDDR0 _SFR_MEM8(0xEC) |
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312 | #define LCDDR1 _SFR_MEM8(0xED) |
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313 | #define LCDDR2 _SFR_MEM8(0xEE) |
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314 | #define LCDDR3 _SFR_MEM8(0xEF) |
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315 | #define LCDDR5 _SFR_MEM8(0xF1) |
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316 | #define LCDDR6 _SFR_MEM8(0xF2) |
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317 | #define LCDDR7 _SFR_MEM8(0xF3) |
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318 | #define LCDDR8 _SFR_MEM8(0xF4) |
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319 | #define LCDDR10 _SFR_MEM8(0xF6) |
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320 | #define LCDDR11 _SFR_MEM8(0xF7) |
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321 | #define LCDDR12 _SFR_MEM8(0xF8) |
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322 | #define LCDDR13 _SFR_MEM8(0xF9) |
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323 | #define LCDDR15 _SFR_MEM8(0xFB) |
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324 | #define LCDDR16 _SFR_MEM8(0xFC) |
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325 | #define LCDDR17 _SFR_MEM8(0xFD) |
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326 | #define LCDDR18 _SFR_MEM8(0xFE) |
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327 | |
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328 | /* Interrupt vectors */ |
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329 | |
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330 | /* External Interrupt Request 0 */ |
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331 | #define INT0_vect _VECTOR(1) |
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332 | #define SIG_INTERRUPT0 _VECTOR(1) |
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333 | |
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334 | /* Pin Change Interrupt Request 0 */ |
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335 | #define PCINT0_vect _VECTOR(2) |
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336 | #define SIG_PIN_CHANGE0 _VECTOR(2) |
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337 | |
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338 | /* Pin Change Interrupt Request 1 */ |
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339 | #define PCINT1_vect _VECTOR(3) |
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340 | #define SIG_PIN_CHANGE1 _VECTOR(3) |
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341 | |
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342 | /* Timer/Counter2 Compare Match */ |
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343 | #define TIMER2_COMP_vect _VECTOR(4) |
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344 | #define SIG_OUTPUT_COMPARE2 _VECTOR(4) |
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345 | |
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346 | /* Timer/Counter2 Overflow */ |
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347 | #define TIMER2_OVF_vect _VECTOR(5) |
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348 | #define SIG_OVERFLOW2 _VECTOR(5) |
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349 | |
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350 | /* Timer/Counter1 Capture Event */ |
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351 | #define TIMER1_CAPT_vect _VECTOR(6) |
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352 | #define SIG_INPUT_CAPTURE1 _VECTOR(6) |
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353 | |
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354 | /* Timer/Counter1 Compare Match A */ |
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355 | #define TIMER1_COMPA_vect _VECTOR(7) |
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356 | #define SIG_OUTPUT_COMPARE1A _VECTOR(7) |
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357 | |
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358 | /* Timer/Counter Compare Match B */ |
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359 | #define TIMER1_COMPB_vect _VECTOR(8) |
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360 | #define SIG_OUTPUT_COMPARE1B _VECTOR(8) |
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361 | |
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362 | /* Timer/Counter1 Overflow */ |
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363 | #define TIMER1_OVF_vect _VECTOR(9) |
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364 | #define SIG_OVERFLOW1 _VECTOR(9) |
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365 | |
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366 | /* Timer/Counter0 Compare Match */ |
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367 | #define TIMER0_COMP_vect _VECTOR(10) |
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368 | #define SIG_OUTPUT_COMPARE0 _VECTOR(10) |
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369 | |
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370 | /* Timer/Counter0 Overflow */ |
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371 | #define TIMER0_OVF_vect _VECTOR(11) |
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372 | #define SIG_OVERFLOW0 _VECTOR(11) |
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373 | |
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374 | /* SPI Serial Transfer Complete */ |
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375 | #define SPI_STC_vect _VECTOR(12) |
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376 | #define SIG_SPI _VECTOR(12) |
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377 | |
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378 | /* USART0, Rx Complete */ |
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379 | #define USART0_RX_vect _VECTOR(13) |
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380 | #define SIG_USART_RECV _VECTOR(13) |
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381 | |
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382 | /* USART0 Data register Empty */ |
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383 | #define USART0_UDRE_vect _VECTOR(14) |
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384 | #define SIG_USART_DATA _VECTOR(14) |
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385 | |
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386 | /* USART0, Tx Complete */ |
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387 | #define USART0_TX_vect _VECTOR(15) |
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388 | #define SIG_USART_TRANS _VECTOR(15) |
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389 | |
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390 | /* USI Start Condition */ |
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391 | #define USI_START_vect _VECTOR(16) |
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392 | #define SIG_USI_START _VECTOR(16) |
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393 | |
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394 | /* USI Overflow */ |
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395 | #define USI_OVERFLOW_vect _VECTOR(17) |
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396 | #define SIG_USI_OVERFLOW _VECTOR(17) |
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397 | |
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398 | /* Analog Comparator */ |
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399 | #define ANALOG_COMP_vect _VECTOR(18) |
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400 | #define SIG_COMPARATOR _VECTOR(18) |
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401 | |
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402 | /* ADC Conversion Complete */ |
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403 | #define ADC_vect _VECTOR(19) |
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404 | #define SIG_ADC _VECTOR(19) |
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405 | |
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406 | /* EEPROM Ready */ |
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407 | #define EE_READY_vect _VECTOR(20) |
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408 | #define SIG_EEPROM_READY _VECTOR(20) |
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409 | |
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410 | /* Store Program Memory Read */ |
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411 | #define SPM_READY_vect _VECTOR(21) |
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412 | #define SIG_SPM_READY _VECTOR(21) |
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413 | |
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414 | /* LCD Start of Frame */ |
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415 | #define LCD_vect _VECTOR(22) |
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416 | #define SIG_LCD _VECTOR(22) |
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417 | |
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418 | #define _VECTORS_SIZE 92 |
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419 | |
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420 | /* Bit numbers */ |
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421 | |
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422 | /* |
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423 | PA7 = SEG3 |
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424 | PA6 = SEG2 |
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425 | PA5 = SEG1 |
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426 | PA4 = SEG0 |
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427 | PA3 = COM3 |
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428 | PA2 = COM2 |
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429 | PA1 = COM1 |
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430 | PA0 = COM0 |
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431 | */ |
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432 | |
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433 | /* PORTA */ |
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434 | #define PA7 7 |
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435 | #define PA6 6 |
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436 | #define PA5 5 |
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437 | #define PA4 4 |
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438 | #define PA3 3 |
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439 | #define PA2 2 |
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440 | #define PA1 1 |
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441 | #define PA0 0 |
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442 | |
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443 | /* DDRA */ |
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444 | #define DDA7 7 |
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445 | #define DDA6 6 |
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446 | #define DDA5 5 |
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447 | #define DDA4 4 |
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448 | #define DDA3 3 |
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449 | #define DDA2 2 |
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450 | #define DDA1 1 |
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451 | #define DDA0 0 |
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452 | |
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453 | /* PINA */ |
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454 | #define PINA7 7 |
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455 | #define PINA6 6 |
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456 | #define PINA5 5 |
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457 | #define PINA4 4 |
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458 | #define PINA3 3 |
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459 | #define PINA2 2 |
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460 | #define PINA1 1 |
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461 | #define PINA0 0 |
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462 | |
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463 | /* |
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464 | PB7 = OC2A / PCINT15 |
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465 | PB6 = OC1B / PCINT14 |
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466 | PB5 = OC1A / PCINT13 |
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467 | PB4 = OC0A / PCINT12 |
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468 | PB3 = MISO / PCINT11 |
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469 | PB2 = MOSI / PCINT10 |
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470 | PB1 = SCK / PCINT9 |
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471 | PB0 = SS# / PCINT8 |
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472 | */ |
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473 | |
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474 | /* PORTB */ |
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475 | #define PB7 7 |
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476 | #define PB6 6 |
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477 | #define PB5 5 |
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478 | #define PB4 4 |
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479 | #define PB3 3 |
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480 | #define PB2 2 |
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481 | #define PB1 1 |
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482 | #define PB0 0 |
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483 | |
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484 | /* DDRB */ |
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485 | #define DDB7 7 |
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486 | #define DDB6 6 |
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487 | #define DDB5 5 |
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488 | #define DDB4 4 |
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489 | #define DDB3 3 |
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490 | #define DDB2 2 |
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491 | #define DDB1 1 |
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492 | #define DDB0 0 |
---|
493 | |
---|
494 | /* PINB */ |
---|
495 | #define PINB7 7 |
---|
496 | #define PINB6 6 |
---|
497 | #define PINB5 5 |
---|
498 | #define PINB4 4 |
---|
499 | #define PINB3 3 |
---|
500 | #define PINB2 2 |
---|
501 | #define PINB1 1 |
---|
502 | #define PINB0 0 |
---|
503 | |
---|
504 | /* |
---|
505 | PC7 = SEG5 |
---|
506 | PC6 = SEG6 |
---|
507 | PC5 = SEG7 |
---|
508 | PC4 = SEG8 |
---|
509 | PC3 = SEG9 |
---|
510 | PC2 = SEG10 |
---|
511 | PC1 = SEG11 |
---|
512 | PC0 = SEG12 |
---|
513 | */ |
---|
514 | |
---|
515 | /* PORTC */ |
---|
516 | #define PC7 7 |
---|
517 | #define PC6 6 |
---|
518 | #define PC5 5 |
---|
519 | #define PC4 4 |
---|
520 | #define PC3 3 |
---|
521 | #define PC2 2 |
---|
522 | #define PC1 1 |
---|
523 | #define PC0 0 |
---|
524 | |
---|
525 | /* DDRC */ |
---|
526 | #define DDC7 7 |
---|
527 | #define DDC6 6 |
---|
528 | #define DDC5 5 |
---|
529 | #define DDC4 4 |
---|
530 | #define DDC3 3 |
---|
531 | #define DDC2 2 |
---|
532 | #define DDC1 1 |
---|
533 | #define DDC0 0 |
---|
534 | |
---|
535 | /* PINC */ |
---|
536 | #define PINC7 7 |
---|
537 | #define PINC6 6 |
---|
538 | #define PINC5 5 |
---|
539 | #define PINC4 4 |
---|
540 | #define PINC3 3 |
---|
541 | #define PINC2 2 |
---|
542 | #define PINC1 1 |
---|
543 | #define PINC0 0 |
---|
544 | |
---|
545 | /* |
---|
546 | PD7 = SEG15 |
---|
547 | PD6 = SEG16 |
---|
548 | PD5 = SEG17 |
---|
549 | PD4 = SEG18 |
---|
550 | PD3 = SEG19 |
---|
551 | PD2 = SEG20 |
---|
552 | PD1 = INT0 / SEG21 |
---|
553 | PD0 = ICP / SEG22 |
---|
554 | */ |
---|
555 | |
---|
556 | /* PORTD */ |
---|
557 | #define PD7 7 |
---|
558 | #define PD6 6 |
---|
559 | #define PD5 5 |
---|
560 | #define PD4 4 |
---|
561 | #define PD3 3 |
---|
562 | #define PD2 2 |
---|
563 | #define PD1 1 |
---|
564 | #define PD0 0 |
---|
565 | |
---|
566 | /* DDRD */ |
---|
567 | #define DDD7 7 |
---|
568 | #define DDD6 6 |
---|
569 | #define DDD5 5 |
---|
570 | #define DDD4 4 |
---|
571 | #define DDD3 3 |
---|
572 | #define DDD2 2 |
---|
573 | #define DDD1 1 |
---|
574 | #define DDD0 0 |
---|
575 | |
---|
576 | /* PIND */ |
---|
577 | #define PIND7 7 |
---|
578 | #define PIND6 6 |
---|
579 | #define PIND5 5 |
---|
580 | #define PIND4 4 |
---|
581 | #define PIND3 3 |
---|
582 | #define PIND2 2 |
---|
583 | #define PIND1 1 |
---|
584 | #define PIND0 0 |
---|
585 | |
---|
586 | /* |
---|
587 | PE7 = CLK0 / PCINT7 |
---|
588 | PE6 = DO / PCINT6 |
---|
589 | PE5 = DI / SDA / PCINT5 |
---|
590 | PE4 = USCK / SCL / PCINT4 |
---|
591 | PE3 = AIN1 / PCINT3 |
---|
592 | PE2 = XCK / AIN0 / PCINT2 |
---|
593 | PE1 = TXD / PCINT1 |
---|
594 | PE0 = RXD / PCINT0 |
---|
595 | */ |
---|
596 | |
---|
597 | /* PORTE */ |
---|
598 | #define PE7 7 |
---|
599 | #define PE6 6 |
---|
600 | #define PE5 5 |
---|
601 | #define PE4 4 |
---|
602 | #define PE3 3 |
---|
603 | #define PE2 2 |
---|
604 | #define PE1 1 |
---|
605 | #define PE0 0 |
---|
606 | |
---|
607 | /* DDRE */ |
---|
608 | #define DDE7 7 |
---|
609 | #define DDE6 6 |
---|
610 | #define DDE5 5 |
---|
611 | #define DDE4 4 |
---|
612 | #define DDE3 3 |
---|
613 | #define DDE2 2 |
---|
614 | #define DDE1 1 |
---|
615 | #define DDE0 0 |
---|
616 | |
---|
617 | /* PINE */ |
---|
618 | #define PINE7 7 |
---|
619 | #define PINE6 6 |
---|
620 | #define PINE5 5 |
---|
621 | #define PINE4 4 |
---|
622 | #define PINE3 3 |
---|
623 | #define PINE2 2 |
---|
624 | #define PINE1 1 |
---|
625 | #define PINE0 0 |
---|
626 | |
---|
627 | /* |
---|
628 | PF7 = ADC7 / TDI |
---|
629 | PF6 = ADC6 / TDO |
---|
630 | PF5 = ADC5 / TMS |
---|
631 | PF4 = ADC4 / TCK |
---|
632 | PF3 = ADC3 |
---|
633 | PF2 = ADC2 |
---|
634 | PF1 = ADC1 |
---|
635 | PF0 = ADC0 |
---|
636 | */ |
---|
637 | |
---|
638 | /* PORTF */ |
---|
639 | #define PF7 7 |
---|
640 | #define PF6 6 |
---|
641 | #define PF5 5 |
---|
642 | #define PF4 4 |
---|
643 | #define PF3 3 |
---|
644 | #define PF2 2 |
---|
645 | #define PF1 1 |
---|
646 | #define PF0 0 |
---|
647 | |
---|
648 | /* DDRF */ |
---|
649 | #define DDF7 7 |
---|
650 | #define DDF6 6 |
---|
651 | #define DDF5 5 |
---|
652 | #define DDF4 4 |
---|
653 | #define DDF3 3 |
---|
654 | #define DDF2 2 |
---|
655 | #define DDF1 1 |
---|
656 | #define DDF0 0 |
---|
657 | |
---|
658 | /* PINF */ |
---|
659 | #define PINF7 7 |
---|
660 | #define PINF6 6 |
---|
661 | #define PINF5 5 |
---|
662 | #define PINF4 4 |
---|
663 | #define PINF3 3 |
---|
664 | #define PINF2 2 |
---|
665 | #define PINF1 1 |
---|
666 | #define PINF0 0 |
---|
667 | |
---|
668 | /* |
---|
669 | PG5 = RESET# |
---|
670 | PG4 = T0 / SEG23 |
---|
671 | PG3 = T1 / SEG24 |
---|
672 | PG2 = SEG4 |
---|
673 | PG1 = SEG13 |
---|
674 | PG0 = SEG14 |
---|
675 | */ |
---|
676 | |
---|
677 | /* PORTG */ |
---|
678 | #define PG4 4 |
---|
679 | #define PG3 3 |
---|
680 | #define PG2 2 |
---|
681 | #define PG1 1 |
---|
682 | #define PG0 0 |
---|
683 | |
---|
684 | /* DDRG */ |
---|
685 | #define DDG4 4 |
---|
686 | #define DDG3 3 |
---|
687 | #define DDG2 2 |
---|
688 | #define DDG1 1 |
---|
689 | #define DDG0 0 |
---|
690 | |
---|
691 | /* PING */ |
---|
692 | #define PING5 5 |
---|
693 | #define PING4 4 |
---|
694 | #define PING3 3 |
---|
695 | #define PING2 2 |
---|
696 | #define PING1 1 |
---|
697 | #define PING0 0 |
---|
698 | |
---|
699 | /* TIFR0 */ |
---|
700 | #define OCF0A 1 |
---|
701 | #define TOV0 0 |
---|
702 | |
---|
703 | /* TIFR1 */ |
---|
704 | #define ICF1 5 |
---|
705 | #define OCF1B 2 |
---|
706 | #define OCF1A 1 |
---|
707 | #define TOV1 0 |
---|
708 | |
---|
709 | /* TIFR2 */ |
---|
710 | #define OCF2A 1 |
---|
711 | #define TOV2 0 |
---|
712 | |
---|
713 | /* EIFR */ |
---|
714 | #define PCIF1 7 |
---|
715 | #define PCIF0 6 |
---|
716 | #define INTF0 0 |
---|
717 | |
---|
718 | /* EIMSK */ |
---|
719 | #define PCIE1 7 |
---|
720 | #define PCIE0 6 |
---|
721 | #define INT0 0 |
---|
722 | |
---|
723 | /* EECR */ |
---|
724 | #define EERIE 3 |
---|
725 | #define EEMWE 2 |
---|
726 | #define EEWE 1 |
---|
727 | #define EERE 0 |
---|
728 | |
---|
729 | /* GTCCR */ |
---|
730 | #define TSM 7 |
---|
731 | #define PSR2 1 |
---|
732 | #define PSR10 0 |
---|
733 | |
---|
734 | /* TCCR0A */ |
---|
735 | #define FOC0A 7 |
---|
736 | #define WGM00 6 |
---|
737 | #define COM0A1 5 |
---|
738 | #define COM0A0 4 |
---|
739 | #define WGM01 3 |
---|
740 | #define CS02 2 |
---|
741 | #define CS01 1 |
---|
742 | #define CS00 0 |
---|
743 | |
---|
744 | /* SPCR */ |
---|
745 | #define SPIE 7 |
---|
746 | #define SPE 6 |
---|
747 | #define DORD 5 |
---|
748 | #define MSTR 4 |
---|
749 | #define CPOL 3 |
---|
750 | #define CPHA 2 |
---|
751 | #define SPR1 1 |
---|
752 | #define SPR0 0 |
---|
753 | |
---|
754 | /* SPSR */ |
---|
755 | #define SPIF 7 |
---|
756 | #define WCOL 6 |
---|
757 | #define SPI2X 0 |
---|
758 | |
---|
759 | /* ACSR */ |
---|
760 | #define ACD 7 |
---|
761 | #define ACBG 6 |
---|
762 | #define ACO 5 |
---|
763 | #define ACI 4 |
---|
764 | #define ACIE 3 |
---|
765 | #define ACIC 2 |
---|
766 | #define ACIS1 1 |
---|
767 | #define ACIS0 0 |
---|
768 | |
---|
769 | /* OCDR */ |
---|
770 | #define IDRD 7 |
---|
771 | #define OCD 7 |
---|
772 | #define OCDR6 6 |
---|
773 | #define OCDR5 5 |
---|
774 | #define OCDR4 4 |
---|
775 | #define OCDR3 3 |
---|
776 | #define OCDR2 2 |
---|
777 | #define OCDR1 1 |
---|
778 | #define OCDR0 0 |
---|
779 | |
---|
780 | /* SMCR */ |
---|
781 | #define SM2 3 |
---|
782 | #define SM1 2 |
---|
783 | #define SM0 1 |
---|
784 | #define SE 0 |
---|
785 | |
---|
786 | /* MCUSR */ |
---|
787 | #define JTRF 4 |
---|
788 | #define WDRF 3 |
---|
789 | #define BORF 2 |
---|
790 | #define EXTRF 1 |
---|
791 | #define PORF 0 |
---|
792 | |
---|
793 | /* MCUCR */ |
---|
794 | #define JTD 7 |
---|
795 | #define PUD 4 |
---|
796 | #define IVSEL 1 |
---|
797 | #define IVCE 0 |
---|
798 | |
---|
799 | /* SPMCSR */ |
---|
800 | #define SPMIE 7 |
---|
801 | #define RWWSB 6 |
---|
802 | #define RWWSRE 4 |
---|
803 | #define BLBSET 3 |
---|
804 | #define PGWRT 2 |
---|
805 | #define PGERS 1 |
---|
806 | #define SPMEN 0 |
---|
807 | |
---|
808 | /* WDTCR */ |
---|
809 | #define WDCE 4 |
---|
810 | #define WDE 3 |
---|
811 | #define WDP2 2 |
---|
812 | #define WDP1 1 |
---|
813 | #define WDP0 0 |
---|
814 | |
---|
815 | /* CLKPR */ |
---|
816 | #define CLKPCE 7 |
---|
817 | #define CLKPS3 3 |
---|
818 | #define CLKPS2 2 |
---|
819 | #define CLKPS1 1 |
---|
820 | #define CLKPS0 0 |
---|
821 | |
---|
822 | /* EICRA */ |
---|
823 | #define ISC01 1 |
---|
824 | #define ISC00 0 |
---|
825 | |
---|
826 | /* PCMSK0 */ |
---|
827 | #define PCINT7 7 |
---|
828 | #define PCINT6 6 |
---|
829 | #define PCINT5 5 |
---|
830 | #define PCINT4 4 |
---|
831 | #define PCINT3 3 |
---|
832 | #define PCINT2 2 |
---|
833 | #define PCINT1 1 |
---|
834 | #define PCINT0 0 |
---|
835 | |
---|
836 | /* PCMSK1 */ |
---|
837 | #define PCINT15 7 |
---|
838 | #define PCINT14 6 |
---|
839 | #define PCINT13 5 |
---|
840 | #define PCINT12 4 |
---|
841 | #define PCINT11 3 |
---|
842 | #define PCINT10 2 |
---|
843 | #define PCINT9 1 |
---|
844 | #define PCINT8 0 |
---|
845 | |
---|
846 | /* TIMSK0 */ |
---|
847 | #define OCIE0A 1 |
---|
848 | #define TOIE0 0 |
---|
849 | |
---|
850 | /* TIMSK1 */ |
---|
851 | #define ICIE1 5 |
---|
852 | #define OCIE1B 2 |
---|
853 | #define OCIE1A 1 |
---|
854 | #define TOIE1 0 |
---|
855 | |
---|
856 | /* TIMSK2 */ |
---|
857 | #define OCIE2A 1 |
---|
858 | #define TOIE2 0 |
---|
859 | |
---|
860 | /* ADCSRA */ |
---|
861 | #define ADEN 7 |
---|
862 | #define ADSC 6 |
---|
863 | #define ADATE 5 |
---|
864 | #define ADIF 4 |
---|
865 | #define ADIE 3 |
---|
866 | #define ADPS2 2 |
---|
867 | #define ADPS1 1 |
---|
868 | #define ADPS0 0 |
---|
869 | |
---|
870 | /* ADCSRB */ |
---|
871 | #define ACME 6 |
---|
872 | #define ADTS2 2 |
---|
873 | #define ADTS1 1 |
---|
874 | #define ADTS0 0 |
---|
875 | |
---|
876 | /* ADMUX */ |
---|
877 | #define REFS1 7 |
---|
878 | #define REFS0 6 |
---|
879 | #define ADLAR 5 |
---|
880 | #define MUX4 4 |
---|
881 | #define MUX3 3 |
---|
882 | #define MUX2 2 |
---|
883 | #define MUX1 1 |
---|
884 | #define MUX0 0 |
---|
885 | |
---|
886 | /* DIDR1 */ |
---|
887 | #define AIN1D 1 |
---|
888 | #define AIN0D 0 |
---|
889 | |
---|
890 | /* DIDR0 */ |
---|
891 | #define ADC7D 7 |
---|
892 | #define ADC6D 6 |
---|
893 | #define ADC5D 5 |
---|
894 | #define ADC4D 4 |
---|
895 | #define ADC3D 3 |
---|
896 | #define ADC2D 2 |
---|
897 | #define ADC1D 1 |
---|
898 | #define ADC0D 0 |
---|
899 | |
---|
900 | /* TCCR1A */ |
---|
901 | #define COM1A1 7 |
---|
902 | #define COM1A0 6 |
---|
903 | #define COM1B1 5 |
---|
904 | #define COM1B0 4 |
---|
905 | #define WGM11 1 |
---|
906 | #define WGM10 0 |
---|
907 | |
---|
908 | /* TCCR1B */ |
---|
909 | #define ICNC1 7 |
---|
910 | #define ICES1 6 |
---|
911 | #define WGM13 4 |
---|
912 | #define WGM12 3 |
---|
913 | #define CS12 2 |
---|
914 | #define CS11 1 |
---|
915 | #define CS10 0 |
---|
916 | |
---|
917 | /* TCCR1C */ |
---|
918 | #define FOC1A 7 |
---|
919 | #define FOC1B 6 |
---|
920 | |
---|
921 | /* TCCR2A */ |
---|
922 | #define FOC2A 7 |
---|
923 | #define WGM20 6 |
---|
924 | #define COM2A1 5 |
---|
925 | #define COM2A0 4 |
---|
926 | #define WGM21 3 |
---|
927 | #define CS22 2 |
---|
928 | #define CS21 1 |
---|
929 | #define CS20 0 |
---|
930 | |
---|
931 | /* ASSR */ |
---|
932 | #define EXCLK 4 |
---|
933 | #define AS2 3 |
---|
934 | #define TCN2UB 2 |
---|
935 | #define OCR2UB 1 |
---|
936 | #define TCR2UB 0 |
---|
937 | |
---|
938 | /* USICR */ |
---|
939 | #define USISIE 7 |
---|
940 | #define USIOIE 6 |
---|
941 | #define USIWM1 5 |
---|
942 | #define USIWM0 4 |
---|
943 | #define USICS1 3 |
---|
944 | #define USICS0 2 |
---|
945 | #define USICLK 1 |
---|
946 | #define USITC 0 |
---|
947 | |
---|
948 | /* USISR */ |
---|
949 | #define USISIF 7 |
---|
950 | #define USIOIF 6 |
---|
951 | #define USIPF 5 |
---|
952 | #define USIDC 4 |
---|
953 | #define USICNT3 3 |
---|
954 | #define USICNT2 2 |
---|
955 | #define USICNT1 1 |
---|
956 | #define USICNT0 0 |
---|
957 | |
---|
958 | /* UCSRA */ |
---|
959 | #define RXC 7 |
---|
960 | #define TXC 6 |
---|
961 | #define UDRE 5 |
---|
962 | #define FE 4 |
---|
963 | #define DOR 3 |
---|
964 | #define UPE 2 |
---|
965 | #define U2X 1 |
---|
966 | #define MPCM 0 |
---|
967 | |
---|
968 | /* UCSRB */ |
---|
969 | #define RXCIE 7 |
---|
970 | #define TXCIE 6 |
---|
971 | #define UDRIE 5 |
---|
972 | #define RXEN 4 |
---|
973 | #define TXEN 3 |
---|
974 | #define UCSZ2 2 |
---|
975 | #define RXB8 1 |
---|
976 | #define TXB8 0 |
---|
977 | |
---|
978 | /* UCSRC */ |
---|
979 | #define UMSEL 6 |
---|
980 | #define UPM1 5 |
---|
981 | #define UPM0 4 |
---|
982 | #define USBS 3 |
---|
983 | #define UCSZ1 2 |
---|
984 | #define UCSZ0 1 |
---|
985 | #define UCPOL 0 |
---|
986 | |
---|
987 | /* LCDCRA */ |
---|
988 | #define LCDEN 7 |
---|
989 | #define LCDAB 6 |
---|
990 | #define LCDIF 4 |
---|
991 | #define LCDIE 3 |
---|
992 | #define LCDBD 2 /* Only in Rev. F */ |
---|
993 | #define LCDCCD 1 /* Only in Rev. F */ |
---|
994 | #define LCDBL 0 |
---|
995 | |
---|
996 | /* LCDCRB */ |
---|
997 | #define LCDCS 7 |
---|
998 | #define LCD2B 6 |
---|
999 | #define LCDMUX1 5 |
---|
1000 | #define LCDMUX0 4 |
---|
1001 | #define LCDPM2 2 |
---|
1002 | #define LCDPM1 1 |
---|
1003 | #define LCDPM0 0 |
---|
1004 | |
---|
1005 | /* LCDFRR */ |
---|
1006 | #define LCDPS2 6 |
---|
1007 | #define LCDPS1 5 |
---|
1008 | #define LCDPS0 4 |
---|
1009 | #define LCDCD2 2 |
---|
1010 | #define LCDCD1 1 |
---|
1011 | #define LCDCD0 0 |
---|
1012 | |
---|
1013 | /* LCDCCR */ |
---|
1014 | #define LCDDC2 7 |
---|
1015 | #define LCDDC1 6 |
---|
1016 | #define LCDDC0 5 |
---|
1017 | #define LCDMDT 4 /* Only in Rev. F */ |
---|
1018 | #define LCDCC3 3 |
---|
1019 | #define LCDCC2 2 |
---|
1020 | #define LCDCC1 1 |
---|
1021 | #define LCDCC0 0 |
---|
1022 | |
---|
1023 | /* LCDDR0-18 */ |
---|
1024 | #define SEG24 0 |
---|
1025 | |
---|
1026 | #define SEG23 7 |
---|
1027 | #define SEG22 6 |
---|
1028 | #define SEG21 5 |
---|
1029 | #define SEG20 4 |
---|
1030 | #define SEG19 3 |
---|
1031 | #define SEG18 2 |
---|
1032 | #define SEG17 1 |
---|
1033 | #define SEG16 0 |
---|
1034 | |
---|
1035 | #define SEG15 7 |
---|
1036 | #define SEG14 6 |
---|
1037 | #define SEG13 5 |
---|
1038 | #define SEG12 4 |
---|
1039 | #define SEG11 3 |
---|
1040 | #define SEG10 2 |
---|
1041 | #define SEG9 1 |
---|
1042 | #define SEG8 0 |
---|
1043 | |
---|
1044 | #define SEG7 7 |
---|
1045 | #define SEG6 6 |
---|
1046 | #define SEG5 5 |
---|
1047 | #define SEG4 4 |
---|
1048 | #define SEG3 3 |
---|
1049 | #define SEG2 2 |
---|
1050 | #define SEG1 1 |
---|
1051 | #define SEG0 0 |
---|
1052 | |
---|
1053 | /* Constants */ |
---|
1054 | #define SPM_PAGESIZE 128 |
---|
1055 | #define RAMEND 0x4FF |
---|
1056 | #define XRAMEND RAMEND |
---|
1057 | #define E2END 0x1FF |
---|
1058 | #define E2PAGESIZE 4 |
---|
1059 | #define FLASHEND 0x3FFF |
---|
1060 | |
---|
1061 | |
---|
1062 | /* Fuses */ |
---|
1063 | |
---|
1064 | #define FUSE_MEMORY_SIZE 3 |
---|
1065 | |
---|
1066 | /* Low Fuse Byte */ |
---|
1067 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
---|
1068 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
---|
1069 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
---|
1070 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
---|
1071 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
---|
1072 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
---|
1073 | #define FUSE_CKOUT (unsigned char)~_BV(6) |
---|
1074 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) |
---|
1075 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
---|
1076 | |
---|
1077 | /* High Fuse Byte */ |
---|
1078 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
---|
1079 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
---|
1080 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
---|
1081 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
---|
1082 | #define FUSE_WDTON (unsigned char)~_BV(4) |
---|
1083 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
---|
1084 | #define FUSE_JTAGEN (unsigned char)~_BV(6) |
---|
1085 | #define FUSE_OCDEN (unsigned char)~_BV(7) |
---|
1086 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
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1087 | |
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1088 | /* Extended Fuse Byte */ |
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1089 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) |
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1090 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) |
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1091 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) |
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1092 | #define EFUSE_DEFAULT (0xFF) |
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1093 | |
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1094 | |
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1095 | /* Lock Bits */ |
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1096 | #define __LOCK_BITS_EXIST |
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1097 | #define __BOOT_LOCK_BITS_0_EXIST |
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1098 | #define __BOOT_LOCK_BITS_1_EXIST |
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1099 | |
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1100 | |
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1101 | /* Signature */ |
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1102 | #define SIGNATURE_0 0x1E |
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1103 | #define SIGNATURE_1 0x94 |
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1104 | #define SIGNATURE_2 0x05 |
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1105 | |
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1106 | |
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1107 | #endif /* _AVR_IOM169_H_ */ |
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