source: rtems/cpukit/score/cpu/avr/avr/iom163.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 11.7 KB
Line 
1/* Copyright (c) 2002, Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom163.h - definitions for ATmega163 */
34
35#ifndef _AVR_IOM163_H_
36#define _AVR_IOM163_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom163.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52#define TWBR    _SFR_IO8(0x00)
53#define TWSR    _SFR_IO8(0x01)
54#define TWAR    _SFR_IO8(0x02)
55#define TWDR    _SFR_IO8(0x03)
56
57/* ADC */
58#ifndef __ASSEMBLER__
59#define ADC     _SFR_IO16(0x04)
60#endif
61#define ADCW    _SFR_IO16(0x04)
62#define ADCL    _SFR_IO8(0x04)
63#define ADCH    _SFR_IO8(0x05)
64#define ADCSR   _SFR_IO8(0x06)
65#define ADMUX   _SFR_IO8(0x07)
66
67/* analog comparator */
68#define ACSR    _SFR_IO8(0x08)
69
70/* UART */
71#define UBRR    _SFR_IO8(0x09)
72#define UCSRB   _SFR_IO8(0x0A)
73#define UCSRA   _SFR_IO8(0x0B)
74#define UDR     _SFR_IO8(0x0C)
75
76/* SPI */
77#define SPCR    _SFR_IO8(0x0D)
78#define SPSR    _SFR_IO8(0x0E)
79#define SPDR    _SFR_IO8(0x0F)
80
81/* Port D */
82#define PIND    _SFR_IO8(0x10)
83#define DDRD    _SFR_IO8(0x11)
84#define PORTD   _SFR_IO8(0x12)
85
86/* Port C */
87#define PINC    _SFR_IO8(0x13)
88#define DDRC    _SFR_IO8(0x14)
89#define PORTC   _SFR_IO8(0x15)
90
91/* Port B */
92#define PINB    _SFR_IO8(0x16)
93#define DDRB    _SFR_IO8(0x17)
94#define PORTB   _SFR_IO8(0x18)
95
96/* Port A */
97#define PINA    _SFR_IO8(0x19)
98#define DDRA    _SFR_IO8(0x1A)
99#define PORTA   _SFR_IO8(0x1B)
100
101/* EEPROM Control Register */
102#define EECR    _SFR_IO8(0x1C)
103
104/* EEPROM Data Register */
105#define EEDR    _SFR_IO8(0x1D)
106
107/* EEPROM Address Register */
108#define EEAR    _SFR_IO16(0x1E)
109#define EEARL   _SFR_IO8(0x1E)
110#define EEARH   _SFR_IO8(0x1F)
111
112#define UBRRHI  _SFR_IO8(0x20)
113
114#define WDTCR   _SFR_IO8(0x21)
115
116#define ASSR    _SFR_IO8(0x22)
117
118/* Timer 2 */
119#define OCR2    _SFR_IO8(0x23)
120#define TCNT2   _SFR_IO8(0x24)
121#define TCCR2   _SFR_IO8(0x25)
122
123/* Timer 1 */
124#define ICR1    _SFR_IO16(0x26)
125#define ICR1L   _SFR_IO8(0x26)
126#define ICR1H   _SFR_IO8(0x27)
127#define OCR1B   _SFR_IO16(0x28)
128#define OCR1BL  _SFR_IO8(0x28)
129#define OCR1BH  _SFR_IO8(0x29)
130#define OCR1A   _SFR_IO16(0x2A)
131#define OCR1AL  _SFR_IO8(0x2A)
132#define OCR1AH  _SFR_IO8(0x2B)
133#define TCNT1   _SFR_IO16(0x2C)
134#define TCNT1L  _SFR_IO8(0x2C)
135#define TCNT1H  _SFR_IO8(0x2D)
136#define TCCR1B  _SFR_IO8(0x2E)
137#define TCCR1A  _SFR_IO8(0x2F)
138
139#define SFIOR   _SFR_IO8(0x30)
140
141#define OSCCAL  _SFR_IO8(0x31)
142
143/* Timer 0 */
144#define TCNT0   _SFR_IO8(0x32)
145#define TCCR0   _SFR_IO8(0x33)
146
147#define MCUSR   _SFR_IO8(0x34)
148#define MCUCR   _SFR_IO8(0x35)
149
150#define TWCR    _SFR_IO8(0x36)
151
152#define SPMCR   _SFR_IO8(0x37)
153
154#define TIFR    _SFR_IO8(0x38)
155#define TIMSK   _SFR_IO8(0x39)
156
157#define GIFR    _SFR_IO8(0x3A)
158#define GIMSK   _SFR_IO8(0x3B)
159
160/* 0x3C reserved */
161
162/* 0x3D..0x3E SP */
163
164/* 0x3F SREG */
165
166/* Interrupt vectors */
167
168/* External Interrupt 0 */
169#define INT0_vect                       _VECTOR(1)
170#define SIG_INTERRUPT0                  _VECTOR(1)
171
172/* External Interrupt 1 */
173#define INT1_vect                       _VECTOR(2)
174#define SIG_INTERRUPT1                  _VECTOR(2)
175
176/* Timer/Counter2 Compare Match */
177#define TIMER2_COMP_vect                _VECTOR(3)
178#define SIG_OUTPUT_COMPARE2             _VECTOR(3)
179
180/* Timer/Counter2 Overflow */
181#define TIMER2_OVF_vect                 _VECTOR(4)
182#define SIG_OVERFLOW2                   _VECTOR(4)
183
184/* Timer/Counter1 Capture Event */
185#define TIMER1_CAPT_vect                _VECTOR(5)
186#define SIG_INPUT_CAPTURE1              _VECTOR(5)
187
188/* Timer/Counter1 Compare Match A */
189#define TIMER1_COMPA_vect               _VECTOR(6)
190#define SIG_OUTPUT_COMPARE1A            _VECTOR(6)
191
192/* Timer/Counter1 Compare Match B */
193#define TIMER1_COMPB_vect               _VECTOR(7)
194#define SIG_OUTPUT_COMPARE1B            _VECTOR(7)
195
196/* Timer/Counter1 Overflow */
197#define TIMER1_OVF_vect                 _VECTOR(8)
198#define SIG_OVERFLOW1                   _VECTOR(8)
199
200/* Timer/Counter0 Overflow */
201#define TIMER0_OVF_vect                 _VECTOR(9)
202#define SIG_OVERFLOW0                   _VECTOR(9)
203
204/* SPI Serial Transfer Complete */
205#define SPI_STC_vect                    _VECTOR(10)
206#define SIG_SPI                         _VECTOR(10)
207
208/* UART, RX Complete */
209#define UART_RX_vect                    _VECTOR(11)
210#define SIG_UART_RECV                   _VECTOR(11)
211
212/* UART Data Register Empty */
213#define UART_UDRE_vect                  _VECTOR(12)
214#define SIG_UART_DATA                   _VECTOR(12)
215
216/* UART, TX Complete */
217#define UART_TX_vect                    _VECTOR(13)
218#define SIG_UART_TRANS                  _VECTOR(13)
219
220/* ADC Conversion Complete */
221#define ADC_vect                        _VECTOR(14)
222#define SIG_ADC                         _VECTOR(14)
223
224/* EEPROM Ready */
225#define EE_RDY_vect                     _VECTOR(15)
226#define SIG_EEPROM_READY                _VECTOR(15)
227
228/* Analog Comparator */
229#define ANA_COMP_vect                   _VECTOR(16)
230#define SIG_COMPARATOR                  _VECTOR(16)
231
232/* 2-Wire Serial Interface */
233#define TWI_vect                        _VECTOR(17)
234#define SIG_2WIRE_SERIAL                _VECTOR(17)
235
236#define _VECTORS_SIZE 72
237
238/* Bit numbers */
239
240/* GIMSK */
241#define INT1    7
242#define INT0    6
243/* bit 5 reserved, undefined */
244/* bits 4-0 reserved */
245
246/* GIFR */
247#define INTF1   7
248#define INTF0   6
249/* bits 5-0 reserved */
250
251/* TIMSK */
252#define OCIE2   7
253#define TOIE2   6
254#define TICIE1  5
255#define OCIE1A  4
256#define OCIE1B  3
257#define TOIE1   2
258/* bit 1 reserved */
259#define TOIE0   0
260
261/* TIFR */
262#define OCF2    7
263#define TOV2    6
264#define ICF1    5
265#define OCF1A   4
266#define OCF1B   3
267#define TOV1    2
268/* bit 1 reserved, undefined */
269#define TOV0    0
270
271/* SPMCR */
272/* bit 7 reserved */
273#define ASB     6
274/* bit 5 reserved */
275#define ASRE    4
276#define BLBSET  3
277#define PGWRT   2
278#define PGERS   1
279#define SPMEN   0
280
281/* TWCR */
282#define TWINT   7
283#define TWEA    6
284#define TWSTA   5
285#define TWSTO   4
286#define TWWC    3
287#define TWEN    2
288/* bit 1 reserved */
289#define TWIE    0
290
291/* TWAR */
292#define TWGCE   0
293
294/* TWSR */
295#define    TWS7         7
296#define    TWS6         6
297#define    TWS5         5
298#define    TWS4         4
299#define    TWS3         3
300/* bits 2-0 reserved */
301
302/* MCUCR */
303/* bit 7 reserved */
304#define SE      6
305#define SM1     5
306#define SM0     4
307#define ISC11   3
308#define ISC10   2
309#define ISC01   1
310#define ISC00   0
311
312/* MCUSR */
313/* bits 7-4 reserved */
314#define WDRF    3
315#define BORF    2
316#define EXTRF   1
317#define PORF    0
318
319/* SFIOR */
320/* bits 7-4 reserved */
321#define ACME    3
322#define PUD     2
323#define PSR2    1
324#define PSR10   0
325
326/* TCCR0 */
327/* bits 7-3 reserved */
328#define CS02    2
329#define CS01    1
330#define CS00    0
331
332/* TCCR2 */
333#define FOC2    7
334#define PWM2    6
335#define COM21   5
336#define COM20   4
337#define CTC2    3
338#define CS22    2
339#define CS21    1
340#define CS20    0
341
342/* ASSR */
343/* bits 7-4 reserved */
344#define AS2     3
345#define TCN2UB  2
346#define OCR2UB  1
347#define TCR2UB  0
348
349/* TCCR1A */
350#define COM1A1  7
351#define COM1A0  6
352#define COM1B1  5
353#define COM1B0  4
354#define FOC1A   3
355#define FOC1B   2
356#define PWM11   1
357#define PWM10   0
358
359/* TCCR1B */
360#define ICNC1   7
361#define ICES1   6
362/* bits 5-4 reserved */
363#define CTC1    3
364#define CS12    2
365#define CS11    1
366#define CS10    0
367
368/* WDTCR */
369/* bits 7-5 reserved */
370#define WDTOE   4
371#define WDE     3
372#define WDP2    2
373#define WDP1    1
374#define WDP0    0
375
376/* PA7-PA0 = ADC7-ADC0 */
377/* PORTA */
378#define PA7     7
379#define PA6     6
380#define PA5     5
381#define PA4     4
382#define PA3     3
383#define PA2     2
384#define PA1     1
385#define PA0     0
386
387/* DDRA */
388#define DDA7    7
389#define DDA6    6
390#define DDA5    5
391#define DDA4    4
392#define DDA3    3
393#define DDA2    2
394#define DDA1    1
395#define DDA0    0
396
397/* PINA */
398#define PINA7   7
399#define PINA6   6
400#define PINA5   5
401#define PINA4   4
402#define PINA3   3
403#define PINA2   2
404#define PINA1   1
405#define PINA0   0
406
407/*
408   PB7 = SCK
409   PB6 = MISO
410   PB5 = MOSI
411   PB4 = SS#
412   PB3 = AIN1
413   PB2 = AIN0
414   PB1 = T1
415   PB0 = T0
416 */
417
418/* PORTB */
419#define PB7     7
420#define PB6     6
421#define PB5     5
422#define PB4     4
423#define PB3     3
424#define PB2     2
425#define PB1     1
426#define PB0     0
427
428/* DDRB */
429#define DDB7    7
430#define DDB6    6
431#define DDB5    5
432#define DDB4    4
433#define DDB3    3
434#define DDB2    2
435#define DDB1    1
436#define DDB0    0
437
438/* PINB */
439#define PINB7   7
440#define PINB6   6
441#define PINB5   5
442#define PINB4   4
443#define PINB3   3
444#define PINB2   2
445#define PINB1   1
446#define PINB0   0
447
448/*
449   PC7 = TOSC2
450   PC6 = TOSC1
451   PC1 = SDA
452   PC0 = SCL
453 */
454/* PORTC */
455#define PC7      7
456#define PC6      6
457#define PC5      5
458#define PC4      4
459#define PC3      3
460#define PC2      2
461#define PC1      1
462#define PC0      0
463
464/* DDRC */
465#define DDC7    7
466#define DDC6    6
467#define DDC5    5
468#define DDC4    4
469#define DDC3    3
470#define DDC2    2
471#define DDC1    1
472#define DDC0    0
473
474/* PINC */
475#define PINC7   7
476#define PINC6   6
477#define PINC5   5
478#define PINC4   4
479#define PINC3   3
480#define PINC2   2
481#define PINC1   1
482#define PINC0   0
483
484/*
485   PD7 = OC2
486   PD6 = ICP
487   PD5 = OC1A
488   PD4 = OC1B
489   PD3 = INT1
490   PD2 = INT0
491   PD1 = TXD
492   PD0 = RXD
493 */
494
495/* PORTD */
496#define PD7      7
497#define PD6      6
498#define PD5      5
499#define PD4      4
500#define PD3      3
501#define PD2      2
502#define PD1      1
503#define PD0      0
504
505/* DDRD */
506#define DDD7    7
507#define DDD6    6
508#define DDD5    5
509#define DDD4    4
510#define DDD3    3
511#define DDD2    2
512#define DDD1    1
513#define DDD0    0
514
515/* PIND */
516#define PIND7   7
517#define PIND6   6
518#define PIND5   5
519#define PIND4   4
520#define PIND3   3
521#define PIND2   2
522#define PIND1   1
523#define PIND0   0
524
525/* SPSR */
526#define SPIF    7
527#define WCOL    6
528/* bits 5-1 reserved */
529#define SPI2X   0
530
531/* SPCR */
532#define SPIE    7
533#define SPE     6
534#define DORD    5
535#define MSTR    4
536#define CPOL    3
537#define CPHA    2
538#define SPR1    1
539#define SPR0    0
540
541/* UCSRA */
542#define RXC     7
543#define TXC     6
544#define UDRE    5
545#define FE      4
546#define DOR     3
547/* bit 2 reserved */
548#define U2X     1
549#define MPCM    0
550
551/* UCSRB */
552#define RXCIE   7
553#define TXCIE   6
554#define UDRIE   5
555#define RXEN    4
556#define TXEN    3
557#define CHR9    2
558#define RXB8    1
559#define TXB8    0
560
561/* ACSR */
562#define ACD     7
563#define AINBG   6
564#define ACO     5
565#define ACI     4
566#define ACIE    3
567#define ACIC    2
568#define ACIS1   1
569#define ACIS0   0
570
571/* ADCSR */
572#define ADEN    7
573#define ADSC    6
574#define ADFR    5
575#define ADIF    4
576#define ADIE    3
577#define ADPS2   2
578#define ADPS1   1
579#define ADPS0   0
580
581/* ADMUX */
582#define REFS1   7
583#define REFS0   6
584#define ADLAR   5
585#define MUX4    4
586#define MUX3    3
587#define MUX2    2
588#define MUX1    1
589#define MUX0    0
590
591/* EEPROM Control Register */
592#define EERIE   3
593#define EEMWE   2
594#define EEWE    1
595#define EERE    0
596
597/* Constants */
598#define SPM_PAGESIZE 128
599#define RAMEND          0x45F
600#define XRAMEND         RAMEND
601#define E2END           0x1FF
602#define E2PAGESIZE  0
603#define FLASHEND        0x3FFF
604
605
606/* Fuses */
607
608#define FUSE_MEMORY_SIZE 2
609
610/* Low Fuse Byte */
611#define FUSE_CKSEL0      (unsigned char)~_BV(0)
612#define FUSE_CKSEL1      (unsigned char)~_BV(1)
613#define FUSE_CKSEL2      (unsigned char)~_BV(2)
614#define FUSE_CKSEL3      (unsigned char)~_BV(3)
615#define FUSE_SPIEN       (unsigned char)~_BV(5)
616#define FUSE_BODEN       (unsigned char)~_BV(6)
617#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
618#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN)
619
620/* High Fuse Byte */
621#define FUSE_BOOTRST     (unsigned char)~_BV(0)
622#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
623#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
624#define HFUSE_DEFAULT (0xFF)
625
626
627/* Lock Bits */
628#define __LOCK_BITS_EXIST
629#define __BOOT_LOCK_BITS_0_EXIST
630#define __BOOT_LOCK_BITS_1_EXIST
631
632
633/* Signature */
634#define SIGNATURE_0 0x1E
635#define SIGNATURE_1 0x94
636#define SIGNATURE_2 0x02
637
638
639#endif /* _AVR_IOM163_H_ */
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