source: rtems/cpukit/score/cpu/avr/avr/iom162.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 19.5 KB
Line 
1/* Copyright (c) 2002, Nils Kristian Strom <nilsst@omegav.ntnu.no>
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* iom162.h - definitions for ATmega162 */
34
35#ifndef _AVR_IOM162_H_
36#define _AVR_IOM162_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom162.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Memory mapped I/O registers */
51
52/* Timer/Counter3 Control Register A */
53#define TCCR3A  _SFR_MEM8(0x8B)
54
55/* Timer/Counter3 Control Register B */
56#define TCCR3B  _SFR_MEM8(0x8A)
57
58/* Timer/Counter3 - Counter Register */
59#define TCNT3H  _SFR_MEM8(0x89)
60#define TCNT3L  _SFR_MEM8(0x88)
61#define TCNT3   _SFR_MEM16(0x88)
62
63/* Timer/Counter3 - Output Compare Register A */
64#define OCR3AH  _SFR_MEM8(0x87)
65#define OCR3AL  _SFR_MEM8(0x86)
66#define OCR3A   _SFR_MEM16(0x86)
67
68/* Timer/Counter3 - Output Compare Register B */
69#define OCR3BH  _SFR_MEM8(0x85)
70#define OCR3BL  _SFR_MEM8(0x84)
71#define OCR3B   _SFR_MEM16(0x84)
72
73/* Timer/Counter3 - Input Capture Register */
74#define ICR3H   _SFR_MEM8(0x81)
75#define ICR3L   _SFR_MEM8(0x80)
76#define ICR3    _SFR_MEM16(0x80)
77
78/* Extended Timer/Counter Interrupt Mask */
79#define ETIMSK  _SFR_MEM8(0x7D)
80
81/* Extended Timer/Counter Interrupt Flag Register */
82#define ETIFR   _SFR_MEM8(0x7C)
83
84/* Pin Change Mask Register 1 */
85#define PCMSK1  _SFR_MEM8(0x6C)
86
87/* Pin Change Mask Register 0 */
88#define PCMSK0  _SFR_MEM8(0x6B)
89
90/* Clock PRescale */
91#define CLKPR   _SFR_MEM8(0x61)
92
93
94/* Standard I/O registers */
95
96/* 0x3F SREG */
97/* 0x3D..0x3E SP */
98#define UBRR1H  _SFR_IO8(0x3C)  /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */
99#define UCSR1C  _SFR_IO8(0x3C)  /* USART 1 Control and Status Register, Shared with UBRR1H */
100#define GICR    _SFR_IO8(0x3B)  /* General Interrupt Control Register */
101#define GIFR    _SFR_IO8(0x3A)  /* General Interrupt Flag Register */
102#define TIMSK   _SFR_IO8(0x39)  /* Timer Interrupt Mask */
103#define TIFR    _SFR_IO8(0x38)  /* Timer Interrupt Flag Register */
104#define SPMCR   _SFR_IO8(0x37)  /* Store Program Memory Control Register */
105#define EMCUCR  _SFR_IO8(0x36)  /* Extended MCU Control Register */
106#define MCUCR   _SFR_IO8(0x35)  /* MCU Control Register */
107#define MCUCSR  _SFR_IO8(0x34)  /* MCU Control and Status Register */
108#define TCCR0   _SFR_IO8(0x33)  /* Timer/Counter 0 Control Register */
109#define TCNT0   _SFR_IO8(0x32)  /* TImer/Counter 0 */
110#define OCR0    _SFR_IO8(0x31)  /* Output Compare Register 0 */
111#define SFIOR   _SFR_IO8(0x30)  /* Special Function I/O Register */
112#define TCCR1A  _SFR_IO8(0x2F)  /* Timer/Counter 1 Control Register A */
113#define TCCR1B  _SFR_IO8(0x2E)  /* Timer/Counter 1 Control Register A */
114#define TCNT1H  _SFR_IO8(0x2D)  /* Timer/Counter 1 High Byte */
115#define TCNT1L  _SFR_IO8(0x2C)  /* Timer/Counter 1 Low Byte */
116#define TCNT1   _SFR_IO16(0x2C) /* Timer/Counter 1 */
117#define OCR1AH  _SFR_IO8(0x2B)  /* Timer/Counter 1 Output Compare Register A High Byte */
118#define OCR1AL  _SFR_IO8(0x2A)  /* Timer/Counter 1 Output Compare Register A Low Byte */
119#define OCR1A   _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */
120#define OCR1BH  _SFR_IO8(0x29)  /* Timer/Counter 1 Output Compare Register B High Byte */
121#define OCR1BL  _SFR_IO8(0x28)  /* Timer/Counter 1 Output Compare Register B Low Byte */
122#define OCR1B   _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */
123#define TCCR2   _SFR_IO8(0x27)  /* Timer/Counter 2 Control Register */
124#define ASSR    _SFR_IO8(0x26)  /* Asynchronous Status Register */
125#define ICR1H   _SFR_IO8(0x25)  /* Input Capture Register 1 High Byte */
126#define ICR1L   _SFR_IO8(0x24)  /* Input Capture Register 1 Low Byte */
127#define ICR1    _SFR_IO16(0x24) /* Input Capture Register 1 */
128#define TCNT2   _SFR_IO8(0x23)  /* Timer/Counter 2 */
129#define OCR2    _SFR_IO8(0x22)  /* Timer/Counter 2 Output Compare Register */
130#define WDTCR   _SFR_IO8(0x21)  /* Watchdow Timer Control Register */
131#define UBRR0H  _SFR_IO8(0x20)  /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */
132#define UCSR0C  _SFR_IO8(0x20)  /* USART 0 Control and Status Register C, Shared with UBRR0H */
133#define EEARH   _SFR_IO8(0x1F)  /* EEPROM Address Register High Byte */
134#define EEARL   _SFR_IO8(0x1E)  /* EEPROM Address Register Low Byte */
135#define EEAR    _SFR_IO16(0x1E) /* EEPROM Address Register */
136#define EEDR    _SFR_IO8(0x1D)  /* EEPROM Data Register */
137#define EECR    _SFR_IO8(0x1C)  /* EEPROM Control Register */
138#define PORTA   _SFR_IO8(0x1B)  /* Port A */
139#define DDRA    _SFR_IO8(0x1A)  /* Port A Data Direction Register */
140#define PINA    _SFR_IO8(0x19)  /* Port A Pin Register */
141#define PORTB   _SFR_IO8(0x18)  /* Port B */
142#define DDRB    _SFR_IO8(0x17)  /* Port B Data Direction Register */
143#define PINB    _SFR_IO8(0x16)  /* Port B Pin Register */
144#define PORTC   _SFR_IO8(0x15)  /* Port C */
145#define DDRC    _SFR_IO8(0x14)  /* Port C Data Direction Register */
146#define PINC    _SFR_IO8(0x13)  /* Port C Pin Register */
147#define PORTD   _SFR_IO8(0x12)  /* Port D */
148#define DDRD    _SFR_IO8(0x11)  /* Port D Data Direction Register */
149#define PIND    _SFR_IO8(0x10)  /* Port D Pin Register */
150#define SPDR    _SFR_IO8(0x0F)  /* SPI Data Register */
151#define SPSR    _SFR_IO8(0x0E)  /* SPI Status Register */
152#define SPCR    _SFR_IO8(0x0D)  /* SPI Control Register */
153#define UDR0    _SFR_IO8(0x0C)  /* USART 0 Data Register */
154#define UCSR0A  _SFR_IO8(0x0B)  /* USART 0 Control and Status Register A */
155#define UCSR0B  _SFR_IO8(0x0A)  /* USART 0 Control and Status Register B */
156#define UBRR0L  _SFR_IO8(0x09)  /* USART 0 Baud-Rate Register Low Byte */
157#define ACSR    _SFR_IO8(0x08)  /* Analog Comparator Status Register */
158#define PORTE   _SFR_IO8(0x07)  /* Port E */
159#define DDRE    _SFR_IO8(0x06)  /* Port E Data Direction Register */
160#define PINE    _SFR_IO8(0x05)  /* Port E Pin Register */
161#define OSCCAL  _SFR_IO8(0x04)  /* Oscillator Calibration, Shared with OCDR */
162#define OCDR    _SFR_IO8(0x04)  /* On-Chip Debug Register, Shared with OSCCAL */
163#define UDR1    _SFR_IO8(0x03)  /* USART 1 Data Register */
164#define UCSR1A  _SFR_IO8(0x02)  /* USART 1 Control and Status Register A */
165#define UCSR1B  _SFR_IO8(0x01)  /* USART 1 Control and Status Register B */
166#define UBRR1L  _SFR_IO8(0x00)  /* USART 0 Baud Rate Register High Byte */
167 
168
169/* Interrupt vectors (byte addresses) */
170
171/* External Interrupt Request 0 */
172#define INT0_vect                       _VECTOR(1)
173#define SIG_INTERRUPT0                  _VECTOR(1)
174
175/* External Interrupt Request 1 */
176#define INT1_vect                       _VECTOR(2)
177#define SIG_INTERRUPT1                  _VECTOR(2)
178
179/* External Interrupt Request 2 */
180#define INT2_vect                       _VECTOR(3)
181#define SIG_INTERRUPT2                  _VECTOR(3)
182
183/* Pin Change Interrupt Request 0 */
184#define PCINT0_vect                     _VECTOR(4)
185#define SIG_PIN_CHANGE0                 _VECTOR(4)
186
187/* Pin Change Interrupt Request 1 */
188#define PCINT1_vect                     _VECTOR(5)
189#define SIG_PIN_CHANGE1                 _VECTOR(5)
190
191/* Timer/Counter3 Capture Event */
192#define TIMER3_CAPT_vect                _VECTOR(6)
193#define SIG_INPUT_CAPTURE3              _VECTOR(6)
194
195/* Timer/Counter3 Compare Match A */
196#define TIMER3_COMPA_vect               _VECTOR(7)
197#define SIG_OUTPUT_COMPARE3A            _VECTOR(7)
198
199/* Timer/Counter3 Compare Match B */
200#define TIMER3_COMPB_vect               _VECTOR(8)
201#define SIG_OUTPUT_COMPARE3B            _VECTOR(8)
202
203/* Timer/Counter3 Overflow */
204#define TIMER3_OVF_vect                 _VECTOR(9)
205#define SIG_OVERFLOW3                   _VECTOR(9)
206
207/* Timer/Counter2 Compare Match */
208#define TIMER2_COMP_vect                _VECTOR(10)
209#define SIG_OUTPUT_COMPARE2             _VECTOR(10)
210
211/* Timer/Counter2 Overflow */
212#define TIMER2_OVF_vect                 _VECTOR(11)
213#define SIG_OVERFLOW2                   _VECTOR(11)
214
215/* Timer/Counter1 Capture Event */
216#define TIMER1_CAPT_vect                _VECTOR(12)
217#define SIG_INPUT_CAPTURE1              _VECTOR(12)
218
219/* Timer/Counter1 Compare Match A */
220#define TIMER1_COMPA_vect               _VECTOR(13)
221#define SIG_OUTPUT_COMPARE1A            _VECTOR(13)
222
223/* Timer/Counter Compare Match B */
224#define TIMER1_COMPB_vect               _VECTOR(14)
225#define SIG_OUTPUT_COMPARE1B            _VECTOR(14)
226
227/* Timer/Counter1 Overflow */
228#define TIMER1_OVF_vect                 _VECTOR(15)
229#define SIG_OVERFLOW1                   _VECTOR(15)
230
231/* Timer/Counter0 Compare Match */
232#define TIMER0_COMP_vect                _VECTOR(16)
233#define SIG_OUTPUT_COMPARE0             _VECTOR(16)
234
235/* Timer/Counter0 Overflow */
236#define TIMER0_OVF_vect                 _VECTOR(17)
237#define SIG_OVERFLOW0                   _VECTOR(17)
238
239/* SPI Serial Transfer Complete */
240#define SPI_STC_vect                    _VECTOR(18)
241#define SIG_SPI                         _VECTOR(18)
242
243/* USART0, Rx Complete */
244#define USART0_RXC_vect                 _VECTOR(19)
245#define SIG_USART0_RECV                 _VECTOR(19)
246
247/* USART1, Rx Complete */
248#define USART1_RXC_vect                 _VECTOR(20)
249#define SIG_USART1_RECV                 _VECTOR(20)
250
251/* USART0 Data register Empty */
252#define USART0_UDRE_vect                _VECTOR(21)
253#define SIG_USART0_DATA                 _VECTOR(21)
254
255/* USART1, Data register Empty */
256#define USART1_UDRE_vect                _VECTOR(22)
257#define SIG_USART1_DATA                 _VECTOR(22)
258
259/* USART0, Tx Complete */
260#define USART0_TXC_vect                 _VECTOR(23)
261#define SIG_USART0_TRANS                _VECTOR(23)
262
263/* USART1, Tx Complete */
264#define USART1_TXC_vect                 _VECTOR(24)
265#define SIG_USART1_TRANS                _VECTOR(24)
266
267/* EEPROM Ready */
268#define EE_RDY_vect                     _VECTOR(25)
269#define SIG_EEPROM_READY                _VECTOR(25)
270
271/* Analog Comparator */
272#define ANA_COMP_vect                   _VECTOR(26)
273#define SIG_COMPARATOR                  _VECTOR(26)
274
275/* Store Program Memory Read */
276#define SPM_RDY_vect                    _VECTOR(27)
277#define SIG_SPM_READY                   _VECTOR(27)
278
279#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */
280
281
282
283
284
285/* TCCR3B bit definitions, memory mapped I/O */
286
287#define ICNC3   7
288#define ICES3   6
289#define WGM33   4
290#define WGM32   3
291#define CS32    2
292#define CS31    1
293#define CS30    0
294
295
296
297/* TCCR3A bit definitions, memory mapped I/O */
298
299#define COM3A1  7
300#define COM3A0  6
301#define COM3B1  5
302#define COM3B0  4
303#define FOC3A   3
304#define FOC3B   2
305#define WGM31   1
306#define WGM30   0
307
308
309
310/* ETIMSK bit definitions, memory mapped I/O */
311
312#define TICIE3          5
313#define OCIE3A          4
314#define OCIE3B          3
315#define TOIE3           2
316
317
318
319/* ETIFR bit definitions, memory mapped I/O */
320
321#define ICF3            5
322#define OCF3A           4
323#define OCF3B           3
324#define TOV3            2
325
326
327
328/* PCMSK1 bit definitions, memory mapped I/O */
329#define PCINT15 7
330#define PCINT14 6
331#define PCINT13 5
332#define PCINT12 4
333#define PCINT11 3
334#define PCINT10 2
335#define PCINT9  1
336#define PCINT8  0
337
338
339
340/* PCMSK0 bit definitions, memory mapped I/O */
341
342#define PCINT7  7
343#define PCINT6  6
344#define PCINT5  5
345#define PCINT4  4
346#define PCINT3  3
347#define PCINT2  2
348#define PCINT1  1
349#define PCINT0  0
350
351
352
353/* CLKPR bit definitions, memory mapped I/O */
354
355#define CLKPCE  7
356#define CLKPS3  3
357#define CLKPS2  2
358#define CLKPS1  1
359#define CLKPS0  0
360
361
362
363/* SPH bit definitions */
364
365#define SP15    15
366#define SP14    14
367#define SP13    13
368#define SP12    12
369#define SP11    11
370#define SP10    10
371#define SP9     9
372#define SP8     8
373
374
375
376/* SPL bit definitions */
377
378#define SP7     7
379#define SP6     6
380#define SP5     5
381#define SP4     4
382#define SP3     3
383#define SP2     2
384#define SP1     1
385#define SP0     0
386
387
388
389/* UBRR1H bit definitions */
390
391#define URSEL1  7
392#define UBRR111 3
393#define UBRR110 2
394#define UBRR19  1
395#define UBRR18  0
396
397
398
399/* UCSR1C bit definitions */
400
401#define URSEL1  7
402#define UMSEL1  6
403#define UPM11   5
404#define UPM10   4
405#define USBS1   3
406#define UCSZ11  2
407#define UCSZ10  1
408#define UCPOL1  0
409
410
411
412/* GICR bit definitions */
413
414#define INT1    7
415#define INT0    6
416#define INT2    5
417#define PCIE1   4
418#define PCIE0   3
419#define IVSEL   1
420#define IVCE    0
421
422
423
424/* GIFR bit definitions */
425
426#define INTF1   7
427#define INTF0   6
428#define INTF2   5
429#define PCIF1   4
430#define PCIF0   3
431
432
433
434/* TIMSK bit definitions */
435
436#define TOIE1   7
437#define OCIE1A  6
438#define OCIE1B  5
439#define OCIE2   4
440#define TICIE1  3
441#define TOIE2   2
442#define TOIE0   1
443#define OCIE0   0
444
445
446
447/* TIFR bit definitions */
448
449#define TOV1    7
450#define OCF1A   6
451#define OCF1B   5
452#define OCF2    4
453#define ICF1    3
454#define TOV2    2
455#define TOV0    1
456#define OCF0    0
457
458
459
460/* SPMCR bit definitions */ 
461
462#define SPMIE   7
463#define RWWSB   6
464#define RWWSRE  4
465#define BLBSET  3
466#define PGWRT   2
467#define PGERS   1
468#define SPMEN   0
469
470
471
472/* EMCUCR bit definitions */
473
474#define SM0     7
475#define SRL2    6
476#define SRL1    5
477#define SRL0    4
478#define SRW01   3
479#define SRW00   2
480#define SRW11   1
481#define ISC2    0
482
483
484
485/* MCUCR bit definitions */
486
487#define SRE     7
488#define SRW10   6
489#define SE      5
490#define SM1     4
491#define ISC11   3
492#define ISC10   2
493#define ISC01   1
494#define ISC00   0
495
496
497
498/* MCUCSR bit definitions */
499
500#define JTD     7
501#define SM2     5
502#define JTRF    4
503#define WDRF    3
504#define BORF    2
505#define EXTRF   1
506#define PORF    0
507
508
509
510/* TCCR0 bit definitions */
511
512#define FOC0    7
513#define WGM00   6
514#define COM01   5
515#define COM00   4
516#define WGM01   3
517#define CS02    2
518#define CS01    1
519#define CS00    0
520
521
522
523/* SFIOR bit definitions */
524
525#define TSM     7
526#define XMBK    6
527#define XMM2    5
528#define XMM1    4
529#define XMM0    3
530#define PUD     2
531#define PSR2    1
532#define PSR310  0
533
534
535
536/* TCCR1A bit definitions */
537
538#define COM1A1  7
539#define COM1A0  6
540#define COM1B1  5
541#define COM1B0  4
542#define FOC1A   3
543#define FOC1B   2
544#define WGM11   1
545#define WGM10   0
546
547
548
549
550/* TCCR1B bit definitions */
551
552#define ICNC1   7               /* Input Capture Noise Canceler */
553#define ICES1   6               /* Input Capture Edge Select */
554#define WGM13   4               /* Waveform Generation Mode 3 */
555#define WGM12   3               /* Waveform Generation Mode 2 */
556#define CS12    2               /* Clock Select 2 */
557#define CS11    1               /* Clock Select 1 */
558#define CS10    0               /* Clock Select 0 */
559
560
561
562/* TCCR2 bit definitions */
563
564#define FOC2    7
565#define WGM20   6
566#define COM21   5
567#define COM20   4
568#define WGM21   3
569#define CS22    2
570#define CS21    1
571#define CS20    0
572
573
574
575/* ASSR bit definitions */
576
577#define AS2     3
578#define TCN2UB  2
579#define TCON2UB 2   /* Kept for backwards compatibility. */
580#define OCR2UB  1
581#define TCR2UB  0
582
583
584
585/* WDTCR bit definitions */
586
587#define WDCE    4
588#define WDE     3
589#define WDP2    2
590#define WDP1    1
591#define WDP0    0
592
593
594
595/* UBRR0H bif definitions */
596
597#define URSEL0  7
598#define UBRR011 3
599#define UBRR010 2
600#define UBRR09  1
601#define UBRR08  0
602
603
604
605/* UCSR0C bit definitions */
606
607#define URSEL0  7
608#define UMSEL0  6
609#define UPM01   5
610#define UPM00   4
611#define USBS0   3
612#define UCSZ01  2
613#define UCSZ00  1
614#define UCPOL0  0
615
616
617
618/* EEARH bit definitions */
619
620#define EEAR8   0
621
622
623
624/* EECR bit definitions */
625
626#define EERIE   3
627#define EEMWE   2
628#define EEWE    1
629#define EERE    0
630
631
632
633/* PORTA bit definitions */
634
635#define PA7     7
636#define PA6     6
637#define PA5     5
638#define PA4     4
639#define PA3     3
640#define PA2     2
641#define PA1     1
642#define PA0     0
643
644
645
646/* DDRA bit definitions */
647
648#define DDA7    7
649#define DDA6    6
650#define DDA5    5
651#define DDA4    4
652#define DDA3    3
653#define DDA2    2
654#define DDA1    1
655#define DDA0    0
656
657
658
659/* PINA bit definitions */
660
661#define PINA7   7
662#define PINA6   6
663#define PINA5   5
664#define PINA4   4
665#define PINA3   3
666#define PINA2   2
667#define PINA1   1
668#define PINA0   0
669
670
671/* PORTB bit definitions */
672
673#define PB7     7
674#define PB6     6
675#define PB5     5
676#define PB4     4
677#define PB3     3
678#define PB2     2
679#define PB1     1
680#define PB0     0
681
682
683
684/* DDRB bit definitions */
685
686#define DDB7    7
687#define DDB6    6
688#define DDB5    5
689#define DDB4    4
690#define DDB3    3
691#define DDB2    2
692#define DDB1    1
693#define DDB0    0
694
695
696
697/* PINB bit definitions */
698
699#define PINB7   7
700#define PINB6   6
701#define PINB5   5
702#define PINB4   4
703#define PINB3   3
704#define PINB2   2
705#define PINB1   1
706#define PINB0   0
707
708
709
710/* PORTC bit definitions */
711
712#define PC7      7
713#define PC6      6
714#define PC5      5
715#define PC4      4
716#define PC3      3
717#define PC2      2
718#define PC1      1
719#define PC0      0
720
721
722
723/* DDRC bit definitions */
724
725#define DDC7    7
726#define DDC6    6
727#define DDC5    5
728#define DDC4    4
729#define DDC3    3
730#define DDC2    2
731#define DDC1    1
732#define DDC0    0
733
734
735
736/* PINC bit definitions */
737
738#define PINC7   7
739#define PINC6   6
740#define PINC5   5
741#define PINC4   4
742#define PINC3   3
743#define PINC2   2
744#define PINC1   1
745#define PINC0   0
746
747
748
749/* PORTD bit definitions */
750
751#define PD7      7
752#define PD6      6
753#define PD5      5
754#define PD4      4
755#define PD3      3
756#define PD2      2
757#define PD1      1
758#define PD0      0
759
760
761
762/* DDRD bit definitions */
763
764#define DDD7    7
765#define DDD6    6
766#define DDD5    5
767#define DDD4    4
768#define DDD3    3
769#define DDD2    2
770#define DDD1    1
771#define DDD0    0
772
773
774
775/* PIND bit definitions */
776
777#define PIND7   7
778#define PIND6   6
779#define PIND5   5
780#define PIND4   4
781#define PIND3   3
782#define PIND2   2
783#define PIND1   1
784#define PIND0   0
785
786
787
788/* SPSR bit definitions */
789
790#define SPIF    7
791#define WCOL    6
792#define SPI2X   0
793
794
795
796/* SPCR bit definitions */
797
798#define SPIE    7
799#define SPE     6
800#define DORD    5
801#define MSTR    4
802#define CPOL    3
803#define CPHA    2
804#define SPR1    1
805#define SPR0    0
806
807
808
809/* UCSR0A bit definitions */
810
811#define RXC0    7
812#define TXC0    6
813#define UDRE0   5
814#define FE0     4
815#define DOR0    3
816#define UPE0    2
817#define U2X0    1
818#define MPCM0   0
819
820
821
822/* UCSR0B bit definitions */
823
824#define RXCIE0  7
825#define TXCIE0  6
826#define UDRIE0  5
827#define RXEN0   4
828#define TXEN0   3
829#define UCSZ02  2
830#define RXB80   1
831#define TXB80   0
832
833
834
835/* ACSR bit definitions */
836
837#define ACD     7
838#define ACBG    6
839#define ACO     5
840#define ACI     4
841#define ACIE    3
842#define ACIC    2
843#define ACIS1   1
844#define ACIS0   0
845
846
847
848/* PORTE bit definitions */
849
850#define PE2     2
851#define PE1     1
852#define PE0     0
853
854
855
856/* DDRE bit definitions */
857
858#define DDE2    2
859#define DDE1    1
860#define DDE0    0
861
862
863
864/* PINE bit definitions */
865
866#define PINE2   2
867#define PINE1   1
868#define PINE0   0
869
870
871
872/* UCSR1A bit definitions */
873
874#define RXC1    7
875#define TXC1    6
876#define UDRE1   5
877#define FE1     4
878#define DOR1    3
879#define UPE1    2
880#define U2X1    1
881#define MPCM1   0
882
883
884
885/* UCSR1B bit definitions */
886
887#define RXCIE1  7
888#define TXCIE1  6
889#define UDRIE1  5
890#define RXEN1   4
891#define TXEN1   3
892#define UCSZ12  2
893#define RXB81   1
894#define TXB81   0
895
896
897/* Constants */
898#define SPM_PAGESIZE 128
899#define RAMEND          0x4FF
900#define XRAMEND         0xFFFF
901#define E2END           0x1FF
902#define E2PAGESIZE  4
903#define FLASHEND        0x3FFF
904
905
906/* Fuses */
907
908#define FUSE_MEMORY_SIZE 3
909
910/* Low Fuse Byte */
911#define FUSE_CKSEL0      (unsigned char)~_BV(0)
912#define FUSE_CKSEL1      (unsigned char)~_BV(1)
913#define FUSE_CKSEL2      (unsigned char)~_BV(2)
914#define FUSE_CKSEL3      (unsigned char)~_BV(3)
915#define FUSE_SUT0        (unsigned char)~_BV(4)
916#define FUSE_SUT1        (unsigned char)~_BV(5)
917#define FUSE_CKOUT       (unsigned char)~_BV(6)
918#define FUSE_CKDIV8      (unsigned char)~_BV(7)
919#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
920
921/* High Fuse Byte */
922#define FUSE_BOOTRST     (unsigned char)~_BV(0)
923#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
924#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
925#define FUSE_EESAVE      (unsigned char)~_BV(3)
926#define FUSE_WDTON       (unsigned char)~_BV(4)
927#define FUSE_SPIEN       (unsigned char)~_BV(5)
928#define FUSE_JTAGEN      (unsigned char)~_BV(6)
929#define FUSE_OCDEN       (unsigned char)~_BV(7)
930#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
931
932/* Extended Fuse Byte */
933#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
934#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
935#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
936#define FUSE_M161C       (unsigned char)~_BV(4)
937#define EFUSE_DEFAULT (0xFF)
938
939
940/* Lock Bits */
941#define __LOCK_BITS_EXIST
942#define __BOOT_LOCK_BITS_0_EXIST
943#define __BOOT_LOCK_BITS_1_EXIST
944
945
946/* Signature */
947#define SIGNATURE_0 0x1E
948#define SIGNATURE_1 0x94
949#define SIGNATURE_2 0x04
950
951
952#endif  /* _AVR_IOM162_H_ */
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