| [04a62dce] | 1 | /* Copyright (c) 2002, Nils Kristian Strom <nilsst@omegav.ntnu.no> |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* iom162.h - definitions for ATmega162 */ |
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| 34 | |
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| 35 | #ifndef _AVR_IOM162_H_ |
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| 36 | #define _AVR_IOM162_H_ 1 |
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| 37 | |
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| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 39 | |
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| 40 | #ifndef _AVR_IO_H_ |
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| 41 | # error "Include <avr/io.h> instead of this file." |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifndef _AVR_IOXXX_H_ |
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| 45 | # define _AVR_IOXXX_H_ "iom162.h" |
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| 46 | #else |
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| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 48 | #endif |
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| 49 | |
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| 50 | /* Memory mapped I/O registers */ |
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| 51 | |
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| 52 | /* Timer/Counter3 Control Register A */ |
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| 53 | #define TCCR3A _SFR_MEM8(0x8B) |
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| 54 | |
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| 55 | /* Timer/Counter3 Control Register B */ |
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| 56 | #define TCCR3B _SFR_MEM8(0x8A) |
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| 57 | |
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| 58 | /* Timer/Counter3 - Counter Register */ |
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| 59 | #define TCNT3H _SFR_MEM8(0x89) |
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| 60 | #define TCNT3L _SFR_MEM8(0x88) |
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| 61 | #define TCNT3 _SFR_MEM16(0x88) |
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| 62 | |
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| 63 | /* Timer/Counter3 - Output Compare Register A */ |
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| 64 | #define OCR3AH _SFR_MEM8(0x87) |
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| 65 | #define OCR3AL _SFR_MEM8(0x86) |
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| 66 | #define OCR3A _SFR_MEM16(0x86) |
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| 67 | |
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| 68 | /* Timer/Counter3 - Output Compare Register B */ |
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| 69 | #define OCR3BH _SFR_MEM8(0x85) |
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| 70 | #define OCR3BL _SFR_MEM8(0x84) |
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| 71 | #define OCR3B _SFR_MEM16(0x84) |
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| 72 | |
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| 73 | /* Timer/Counter3 - Input Capture Register */ |
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| 74 | #define ICR3H _SFR_MEM8(0x81) |
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| 75 | #define ICR3L _SFR_MEM8(0x80) |
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| 76 | #define ICR3 _SFR_MEM16(0x80) |
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| 77 | |
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| 78 | /* Extended Timer/Counter Interrupt Mask */ |
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| 79 | #define ETIMSK _SFR_MEM8(0x7D) |
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| 80 | |
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| 81 | /* Extended Timer/Counter Interrupt Flag Register */ |
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| 82 | #define ETIFR _SFR_MEM8(0x7C) |
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| 83 | |
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| 84 | /* Pin Change Mask Register 1 */ |
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| 85 | #define PCMSK1 _SFR_MEM8(0x6C) |
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| 86 | |
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| 87 | /* Pin Change Mask Register 0 */ |
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| 88 | #define PCMSK0 _SFR_MEM8(0x6B) |
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| 89 | |
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| 90 | /* Clock PRescale */ |
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| 91 | #define CLKPR _SFR_MEM8(0x61) |
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| 92 | |
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| 93 | |
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| 94 | /* Standard I/O registers */ |
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| 95 | |
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| 96 | /* 0x3F SREG */ |
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| 97 | /* 0x3D..0x3E SP */ |
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| 98 | #define UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */ |
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| 99 | #define UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */ |
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| 100 | #define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */ |
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| 101 | #define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */ |
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| 102 | #define TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */ |
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| 103 | #define TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */ |
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| 104 | #define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */ |
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| 105 | #define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */ |
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| 106 | #define MCUCR _SFR_IO8(0x35) /* MCU Control Register */ |
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| 107 | #define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */ |
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| 108 | #define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */ |
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| 109 | #define TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */ |
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| 110 | #define OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */ |
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| 111 | #define SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */ |
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| 112 | #define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */ |
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| 113 | #define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */ |
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| 114 | #define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */ |
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| 115 | #define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */ |
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| 116 | #define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */ |
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| 117 | #define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */ |
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| 118 | #define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */ |
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| 119 | #define OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */ |
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| 120 | #define OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */ |
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| 121 | #define OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */ |
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| 122 | #define OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */ |
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| 123 | #define TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */ |
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| 124 | #define ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */ |
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| 125 | #define ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */ |
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| 126 | #define ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */ |
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| 127 | #define ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */ |
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| 128 | #define TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */ |
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| 129 | #define OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */ |
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| 130 | #define WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */ |
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| 131 | #define UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */ |
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| 132 | #define UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */ |
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| 133 | #define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */ |
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| 134 | #define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */ |
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| 135 | #define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */ |
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| 136 | #define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */ |
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| 137 | #define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */ |
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| 138 | #define PORTA _SFR_IO8(0x1B) /* Port A */ |
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| 139 | #define DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */ |
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| 140 | #define PINA _SFR_IO8(0x19) /* Port A Pin Register */ |
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| 141 | #define PORTB _SFR_IO8(0x18) /* Port B */ |
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| 142 | #define DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */ |
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| 143 | #define PINB _SFR_IO8(0x16) /* Port B Pin Register */ |
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| 144 | #define PORTC _SFR_IO8(0x15) /* Port C */ |
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| 145 | #define DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */ |
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| 146 | #define PINC _SFR_IO8(0x13) /* Port C Pin Register */ |
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| 147 | #define PORTD _SFR_IO8(0x12) /* Port D */ |
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| 148 | #define DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */ |
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| 149 | #define PIND _SFR_IO8(0x10) /* Port D Pin Register */ |
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| 150 | #define SPDR _SFR_IO8(0x0F) /* SPI Data Register */ |
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| 151 | #define SPSR _SFR_IO8(0x0E) /* SPI Status Register */ |
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| 152 | #define SPCR _SFR_IO8(0x0D) /* SPI Control Register */ |
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| 153 | #define UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */ |
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| 154 | #define UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */ |
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| 155 | #define UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */ |
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| 156 | #define UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */ |
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| 157 | #define ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */ |
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| 158 | #define PORTE _SFR_IO8(0x07) /* Port E */ |
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| 159 | #define DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */ |
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| 160 | #define PINE _SFR_IO8(0x05) /* Port E Pin Register */ |
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| 161 | #define OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */ |
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| 162 | #define OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */ |
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| 163 | #define UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */ |
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| 164 | #define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ |
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| 165 | #define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ |
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| 166 | #define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ |
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| 167 | |
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| 168 | |
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| 169 | /* Interrupt vectors (byte addresses) */ |
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| 170 | |
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| 171 | /* External Interrupt Request 0 */ |
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| 172 | #define INT0_vect _VECTOR(1) |
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| 173 | #define SIG_INTERRUPT0 _VECTOR(1) |
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| 174 | |
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| 175 | /* External Interrupt Request 1 */ |
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| 176 | #define INT1_vect _VECTOR(2) |
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| 177 | #define SIG_INTERRUPT1 _VECTOR(2) |
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| 178 | |
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| 179 | /* External Interrupt Request 2 */ |
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| 180 | #define INT2_vect _VECTOR(3) |
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| 181 | #define SIG_INTERRUPT2 _VECTOR(3) |
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| 182 | |
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| 183 | /* Pin Change Interrupt Request 0 */ |
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| 184 | #define PCINT0_vect _VECTOR(4) |
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| 185 | #define SIG_PIN_CHANGE0 _VECTOR(4) |
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| 186 | |
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| 187 | /* Pin Change Interrupt Request 1 */ |
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| 188 | #define PCINT1_vect _VECTOR(5) |
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| 189 | #define SIG_PIN_CHANGE1 _VECTOR(5) |
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| 190 | |
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| 191 | /* Timer/Counter3 Capture Event */ |
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| 192 | #define TIMER3_CAPT_vect _VECTOR(6) |
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| 193 | #define SIG_INPUT_CAPTURE3 _VECTOR(6) |
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| 194 | |
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| 195 | /* Timer/Counter3 Compare Match A */ |
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| 196 | #define TIMER3_COMPA_vect _VECTOR(7) |
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| 197 | #define SIG_OUTPUT_COMPARE3A _VECTOR(7) |
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| 198 | |
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| 199 | /* Timer/Counter3 Compare Match B */ |
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| 200 | #define TIMER3_COMPB_vect _VECTOR(8) |
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| 201 | #define SIG_OUTPUT_COMPARE3B _VECTOR(8) |
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| 202 | |
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| 203 | /* Timer/Counter3 Overflow */ |
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| 204 | #define TIMER3_OVF_vect _VECTOR(9) |
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| 205 | #define SIG_OVERFLOW3 _VECTOR(9) |
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| 206 | |
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| 207 | /* Timer/Counter2 Compare Match */ |
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| 208 | #define TIMER2_COMP_vect _VECTOR(10) |
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| 209 | #define SIG_OUTPUT_COMPARE2 _VECTOR(10) |
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| 210 | |
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| 211 | /* Timer/Counter2 Overflow */ |
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| 212 | #define TIMER2_OVF_vect _VECTOR(11) |
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| 213 | #define SIG_OVERFLOW2 _VECTOR(11) |
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| 214 | |
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| 215 | /* Timer/Counter1 Capture Event */ |
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| 216 | #define TIMER1_CAPT_vect _VECTOR(12) |
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| 217 | #define SIG_INPUT_CAPTURE1 _VECTOR(12) |
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| 218 | |
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| 219 | /* Timer/Counter1 Compare Match A */ |
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| 220 | #define TIMER1_COMPA_vect _VECTOR(13) |
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| 221 | #define SIG_OUTPUT_COMPARE1A _VECTOR(13) |
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| 222 | |
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| 223 | /* Timer/Counter Compare Match B */ |
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| 224 | #define TIMER1_COMPB_vect _VECTOR(14) |
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| 225 | #define SIG_OUTPUT_COMPARE1B _VECTOR(14) |
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| 226 | |
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| 227 | /* Timer/Counter1 Overflow */ |
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| 228 | #define TIMER1_OVF_vect _VECTOR(15) |
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| 229 | #define SIG_OVERFLOW1 _VECTOR(15) |
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| 230 | |
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| 231 | /* Timer/Counter0 Compare Match */ |
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| 232 | #define TIMER0_COMP_vect _VECTOR(16) |
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| 233 | #define SIG_OUTPUT_COMPARE0 _VECTOR(16) |
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| 234 | |
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| 235 | /* Timer/Counter0 Overflow */ |
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| 236 | #define TIMER0_OVF_vect _VECTOR(17) |
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| 237 | #define SIG_OVERFLOW0 _VECTOR(17) |
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| 238 | |
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| 239 | /* SPI Serial Transfer Complete */ |
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| 240 | #define SPI_STC_vect _VECTOR(18) |
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| 241 | #define SIG_SPI _VECTOR(18) |
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| 242 | |
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| 243 | /* USART0, Rx Complete */ |
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| 244 | #define USART0_RXC_vect _VECTOR(19) |
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| 245 | #define SIG_USART0_RECV _VECTOR(19) |
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| 246 | |
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| 247 | /* USART1, Rx Complete */ |
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| 248 | #define USART1_RXC_vect _VECTOR(20) |
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| 249 | #define SIG_USART1_RECV _VECTOR(20) |
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| 250 | |
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| 251 | /* USART0 Data register Empty */ |
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| 252 | #define USART0_UDRE_vect _VECTOR(21) |
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| 253 | #define SIG_USART0_DATA _VECTOR(21) |
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| 254 | |
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| 255 | /* USART1, Data register Empty */ |
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| 256 | #define USART1_UDRE_vect _VECTOR(22) |
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| 257 | #define SIG_USART1_DATA _VECTOR(22) |
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| 258 | |
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| 259 | /* USART0, Tx Complete */ |
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| 260 | #define USART0_TXC_vect _VECTOR(23) |
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| 261 | #define SIG_USART0_TRANS _VECTOR(23) |
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| 262 | |
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| 263 | /* USART1, Tx Complete */ |
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| 264 | #define USART1_TXC_vect _VECTOR(24) |
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| 265 | #define SIG_USART1_TRANS _VECTOR(24) |
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| 266 | |
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| 267 | /* EEPROM Ready */ |
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| 268 | #define EE_RDY_vect _VECTOR(25) |
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| 269 | #define SIG_EEPROM_READY _VECTOR(25) |
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| 270 | |
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| 271 | /* Analog Comparator */ |
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| 272 | #define ANA_COMP_vect _VECTOR(26) |
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| 273 | #define SIG_COMPARATOR _VECTOR(26) |
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| 274 | |
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| 275 | /* Store Program Memory Read */ |
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| 276 | #define SPM_RDY_vect _VECTOR(27) |
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| 277 | #define SIG_SPM_READY _VECTOR(27) |
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| 278 | |
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| 279 | #define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ |
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| 280 | |
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| 281 | |
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| 282 | |
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| 283 | |
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| 284 | |
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| 285 | /* TCCR3B bit definitions, memory mapped I/O */ |
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| 286 | |
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| 287 | #define ICNC3 7 |
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| 288 | #define ICES3 6 |
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| 289 | #define WGM33 4 |
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| 290 | #define WGM32 3 |
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| 291 | #define CS32 2 |
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| 292 | #define CS31 1 |
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| 293 | #define CS30 0 |
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| 294 | |
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| 295 | |
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| 296 | |
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| 297 | /* TCCR3A bit definitions, memory mapped I/O */ |
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| 298 | |
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| 299 | #define COM3A1 7 |
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| 300 | #define COM3A0 6 |
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| 301 | #define COM3B1 5 |
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| 302 | #define COM3B0 4 |
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| 303 | #define FOC3A 3 |
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| 304 | #define FOC3B 2 |
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| 305 | #define WGM31 1 |
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| 306 | #define WGM30 0 |
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| 307 | |
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| 308 | |
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| 309 | |
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| 310 | /* ETIMSK bit definitions, memory mapped I/O */ |
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| 311 | |
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| 312 | #define TICIE3 5 |
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| 313 | #define OCIE3A 4 |
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| 314 | #define OCIE3B 3 |
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| 315 | #define TOIE3 2 |
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| 316 | |
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| 317 | |
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| 318 | |
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| 319 | /* ETIFR bit definitions, memory mapped I/O */ |
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| 320 | |
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| 321 | #define ICF3 5 |
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| 322 | #define OCF3A 4 |
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| 323 | #define OCF3B 3 |
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| 324 | #define TOV3 2 |
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| 325 | |
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| 326 | |
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| 327 | |
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| 328 | /* PCMSK1 bit definitions, memory mapped I/O */ |
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| 329 | #define PCINT15 7 |
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| 330 | #define PCINT14 6 |
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| 331 | #define PCINT13 5 |
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| 332 | #define PCINT12 4 |
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| 333 | #define PCINT11 3 |
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| 334 | #define PCINT10 2 |
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| 335 | #define PCINT9 1 |
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| 336 | #define PCINT8 0 |
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| 337 | |
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| 338 | |
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| 339 | |
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| 340 | /* PCMSK0 bit definitions, memory mapped I/O */ |
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| 341 | |
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| 342 | #define PCINT7 7 |
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| 343 | #define PCINT6 6 |
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| 344 | #define PCINT5 5 |
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| 345 | #define PCINT4 4 |
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| 346 | #define PCINT3 3 |
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| 347 | #define PCINT2 2 |
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| 348 | #define PCINT1 1 |
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| 349 | #define PCINT0 0 |
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| 350 | |
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| 351 | |
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| 352 | |
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| 353 | /* CLKPR bit definitions, memory mapped I/O */ |
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| 354 | |
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| 355 | #define CLKPCE 7 |
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| 356 | #define CLKPS3 3 |
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| 357 | #define CLKPS2 2 |
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| 358 | #define CLKPS1 1 |
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| 359 | #define CLKPS0 0 |
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| 360 | |
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| 361 | |
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| 362 | |
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| 363 | /* SPH bit definitions */ |
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| 364 | |
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| 365 | #define SP15 15 |
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| 366 | #define SP14 14 |
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| 367 | #define SP13 13 |
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| 368 | #define SP12 12 |
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| 369 | #define SP11 11 |
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| 370 | #define SP10 10 |
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| 371 | #define SP9 9 |
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| 372 | #define SP8 8 |
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| 373 | |
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| 374 | |
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| 375 | |
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| 376 | /* SPL bit definitions */ |
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| 377 | |
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| 378 | #define SP7 7 |
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| 379 | #define SP6 6 |
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| 380 | #define SP5 5 |
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| 381 | #define SP4 4 |
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| 382 | #define SP3 3 |
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| 383 | #define SP2 2 |
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| 384 | #define SP1 1 |
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| 385 | #define SP0 0 |
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| 386 | |
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| 387 | |
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| 388 | |
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| 389 | /* UBRR1H bit definitions */ |
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| 390 | |
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| 391 | #define URSEL1 7 |
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| 392 | #define UBRR111 3 |
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| 393 | #define UBRR110 2 |
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| 394 | #define UBRR19 1 |
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| 395 | #define UBRR18 0 |
|---|
| 396 | |
|---|
| 397 | |
|---|
| 398 | |
|---|
| 399 | /* UCSR1C bit definitions */ |
|---|
| 400 | |
|---|
| 401 | #define URSEL1 7 |
|---|
| 402 | #define UMSEL1 6 |
|---|
| 403 | #define UPM11 5 |
|---|
| 404 | #define UPM10 4 |
|---|
| 405 | #define USBS1 3 |
|---|
| 406 | #define UCSZ11 2 |
|---|
| 407 | #define UCSZ10 1 |
|---|
| 408 | #define UCPOL1 0 |
|---|
| 409 | |
|---|
| 410 | |
|---|
| 411 | |
|---|
| 412 | /* GICR bit definitions */ |
|---|
| 413 | |
|---|
| 414 | #define INT1 7 |
|---|
| 415 | #define INT0 6 |
|---|
| 416 | #define INT2 5 |
|---|
| 417 | #define PCIE1 4 |
|---|
| 418 | #define PCIE0 3 |
|---|
| 419 | #define IVSEL 1 |
|---|
| 420 | #define IVCE 0 |
|---|
| 421 | |
|---|
| 422 | |
|---|
| 423 | |
|---|
| 424 | /* GIFR bit definitions */ |
|---|
| 425 | |
|---|
| 426 | #define INTF1 7 |
|---|
| 427 | #define INTF0 6 |
|---|
| 428 | #define INTF2 5 |
|---|
| 429 | #define PCIF1 4 |
|---|
| 430 | #define PCIF0 3 |
|---|
| 431 | |
|---|
| 432 | |
|---|
| 433 | |
|---|
| 434 | /* TIMSK bit definitions */ |
|---|
| 435 | |
|---|
| 436 | #define TOIE1 7 |
|---|
| 437 | #define OCIE1A 6 |
|---|
| 438 | #define OCIE1B 5 |
|---|
| 439 | #define OCIE2 4 |
|---|
| 440 | #define TICIE1 3 |
|---|
| 441 | #define TOIE2 2 |
|---|
| 442 | #define TOIE0 1 |
|---|
| 443 | #define OCIE0 0 |
|---|
| 444 | |
|---|
| 445 | |
|---|
| 446 | |
|---|
| 447 | /* TIFR bit definitions */ |
|---|
| 448 | |
|---|
| 449 | #define TOV1 7 |
|---|
| 450 | #define OCF1A 6 |
|---|
| 451 | #define OCF1B 5 |
|---|
| 452 | #define OCF2 4 |
|---|
| 453 | #define ICF1 3 |
|---|
| 454 | #define TOV2 2 |
|---|
| 455 | #define TOV0 1 |
|---|
| 456 | #define OCF0 0 |
|---|
| 457 | |
|---|
| 458 | |
|---|
| 459 | |
|---|
| 460 | /* SPMCR bit definitions */ |
|---|
| 461 | |
|---|
| 462 | #define SPMIE 7 |
|---|
| 463 | #define RWWSB 6 |
|---|
| 464 | #define RWWSRE 4 |
|---|
| 465 | #define BLBSET 3 |
|---|
| 466 | #define PGWRT 2 |
|---|
| 467 | #define PGERS 1 |
|---|
| 468 | #define SPMEN 0 |
|---|
| 469 | |
|---|
| 470 | |
|---|
| 471 | |
|---|
| 472 | /* EMCUCR bit definitions */ |
|---|
| 473 | |
|---|
| 474 | #define SM0 7 |
|---|
| 475 | #define SRL2 6 |
|---|
| 476 | #define SRL1 5 |
|---|
| 477 | #define SRL0 4 |
|---|
| 478 | #define SRW01 3 |
|---|
| 479 | #define SRW00 2 |
|---|
| 480 | #define SRW11 1 |
|---|
| 481 | #define ISC2 0 |
|---|
| 482 | |
|---|
| 483 | |
|---|
| 484 | |
|---|
| 485 | /* MCUCR bit definitions */ |
|---|
| 486 | |
|---|
| 487 | #define SRE 7 |
|---|
| 488 | #define SRW10 6 |
|---|
| 489 | #define SE 5 |
|---|
| 490 | #define SM1 4 |
|---|
| 491 | #define ISC11 3 |
|---|
| 492 | #define ISC10 2 |
|---|
| 493 | #define ISC01 1 |
|---|
| 494 | #define ISC00 0 |
|---|
| 495 | |
|---|
| 496 | |
|---|
| 497 | |
|---|
| 498 | /* MCUCSR bit definitions */ |
|---|
| 499 | |
|---|
| 500 | #define JTD 7 |
|---|
| 501 | #define SM2 5 |
|---|
| 502 | #define JTRF 4 |
|---|
| 503 | #define WDRF 3 |
|---|
| 504 | #define BORF 2 |
|---|
| 505 | #define EXTRF 1 |
|---|
| 506 | #define PORF 0 |
|---|
| 507 | |
|---|
| 508 | |
|---|
| 509 | |
|---|
| 510 | /* TCCR0 bit definitions */ |
|---|
| 511 | |
|---|
| 512 | #define FOC0 7 |
|---|
| 513 | #define WGM00 6 |
|---|
| 514 | #define COM01 5 |
|---|
| 515 | #define COM00 4 |
|---|
| 516 | #define WGM01 3 |
|---|
| 517 | #define CS02 2 |
|---|
| 518 | #define CS01 1 |
|---|
| 519 | #define CS00 0 |
|---|
| 520 | |
|---|
| 521 | |
|---|
| 522 | |
|---|
| 523 | /* SFIOR bit definitions */ |
|---|
| 524 | |
|---|
| 525 | #define TSM 7 |
|---|
| 526 | #define XMBK 6 |
|---|
| 527 | #define XMM2 5 |
|---|
| 528 | #define XMM1 4 |
|---|
| 529 | #define XMM0 3 |
|---|
| 530 | #define PUD 2 |
|---|
| 531 | #define PSR2 1 |
|---|
| 532 | #define PSR310 0 |
|---|
| 533 | |
|---|
| 534 | |
|---|
| 535 | |
|---|
| 536 | /* TCCR1A bit definitions */ |
|---|
| 537 | |
|---|
| 538 | #define COM1A1 7 |
|---|
| 539 | #define COM1A0 6 |
|---|
| 540 | #define COM1B1 5 |
|---|
| 541 | #define COM1B0 4 |
|---|
| 542 | #define FOC1A 3 |
|---|
| 543 | #define FOC1B 2 |
|---|
| 544 | #define WGM11 1 |
|---|
| 545 | #define WGM10 0 |
|---|
| 546 | |
|---|
| 547 | |
|---|
| 548 | |
|---|
| 549 | |
|---|
| 550 | /* TCCR1B bit definitions */ |
|---|
| 551 | |
|---|
| 552 | #define ICNC1 7 /* Input Capture Noise Canceler */ |
|---|
| 553 | #define ICES1 6 /* Input Capture Edge Select */ |
|---|
| 554 | #define WGM13 4 /* Waveform Generation Mode 3 */ |
|---|
| 555 | #define WGM12 3 /* Waveform Generation Mode 2 */ |
|---|
| 556 | #define CS12 2 /* Clock Select 2 */ |
|---|
| 557 | #define CS11 1 /* Clock Select 1 */ |
|---|
| 558 | #define CS10 0 /* Clock Select 0 */ |
|---|
| 559 | |
|---|
| 560 | |
|---|
| 561 | |
|---|
| 562 | /* TCCR2 bit definitions */ |
|---|
| 563 | |
|---|
| 564 | #define FOC2 7 |
|---|
| 565 | #define WGM20 6 |
|---|
| 566 | #define COM21 5 |
|---|
| 567 | #define COM20 4 |
|---|
| 568 | #define WGM21 3 |
|---|
| 569 | #define CS22 2 |
|---|
| 570 | #define CS21 1 |
|---|
| 571 | #define CS20 0 |
|---|
| 572 | |
|---|
| 573 | |
|---|
| 574 | |
|---|
| 575 | /* ASSR bit definitions */ |
|---|
| 576 | |
|---|
| 577 | #define AS2 3 |
|---|
| 578 | #define TCN2UB 2 |
|---|
| 579 | #define TCON2UB 2 /* Kept for backwards compatibility. */ |
|---|
| 580 | #define OCR2UB 1 |
|---|
| 581 | #define TCR2UB 0 |
|---|
| 582 | |
|---|
| 583 | |
|---|
| 584 | |
|---|
| 585 | /* WDTCR bit definitions */ |
|---|
| 586 | |
|---|
| 587 | #define WDCE 4 |
|---|
| 588 | #define WDE 3 |
|---|
| 589 | #define WDP2 2 |
|---|
| 590 | #define WDP1 1 |
|---|
| 591 | #define WDP0 0 |
|---|
| 592 | |
|---|
| 593 | |
|---|
| 594 | |
|---|
| 595 | /* UBRR0H bif definitions */ |
|---|
| 596 | |
|---|
| 597 | #define URSEL0 7 |
|---|
| 598 | #define UBRR011 3 |
|---|
| 599 | #define UBRR010 2 |
|---|
| 600 | #define UBRR09 1 |
|---|
| 601 | #define UBRR08 0 |
|---|
| 602 | |
|---|
| 603 | |
|---|
| 604 | |
|---|
| 605 | /* UCSR0C bit definitions */ |
|---|
| 606 | |
|---|
| 607 | #define URSEL0 7 |
|---|
| 608 | #define UMSEL0 6 |
|---|
| 609 | #define UPM01 5 |
|---|
| 610 | #define UPM00 4 |
|---|
| 611 | #define USBS0 3 |
|---|
| 612 | #define UCSZ01 2 |
|---|
| 613 | #define UCSZ00 1 |
|---|
| 614 | #define UCPOL0 0 |
|---|
| 615 | |
|---|
| 616 | |
|---|
| 617 | |
|---|
| 618 | /* EEARH bit definitions */ |
|---|
| 619 | |
|---|
| 620 | #define EEAR8 0 |
|---|
| 621 | |
|---|
| 622 | |
|---|
| 623 | |
|---|
| 624 | /* EECR bit definitions */ |
|---|
| 625 | |
|---|
| 626 | #define EERIE 3 |
|---|
| 627 | #define EEMWE 2 |
|---|
| 628 | #define EEWE 1 |
|---|
| 629 | #define EERE 0 |
|---|
| 630 | |
|---|
| 631 | |
|---|
| 632 | |
|---|
| 633 | /* PORTA bit definitions */ |
|---|
| 634 | |
|---|
| 635 | #define PA7 7 |
|---|
| 636 | #define PA6 6 |
|---|
| 637 | #define PA5 5 |
|---|
| 638 | #define PA4 4 |
|---|
| 639 | #define PA3 3 |
|---|
| 640 | #define PA2 2 |
|---|
| 641 | #define PA1 1 |
|---|
| 642 | #define PA0 0 |
|---|
| 643 | |
|---|
| 644 | |
|---|
| 645 | |
|---|
| 646 | /* DDRA bit definitions */ |
|---|
| 647 | |
|---|
| 648 | #define DDA7 7 |
|---|
| 649 | #define DDA6 6 |
|---|
| 650 | #define DDA5 5 |
|---|
| 651 | #define DDA4 4 |
|---|
| 652 | #define DDA3 3 |
|---|
| 653 | #define DDA2 2 |
|---|
| 654 | #define DDA1 1 |
|---|
| 655 | #define DDA0 0 |
|---|
| 656 | |
|---|
| 657 | |
|---|
| 658 | |
|---|
| 659 | /* PINA bit definitions */ |
|---|
| 660 | |
|---|
| 661 | #define PINA7 7 |
|---|
| 662 | #define PINA6 6 |
|---|
| 663 | #define PINA5 5 |
|---|
| 664 | #define PINA4 4 |
|---|
| 665 | #define PINA3 3 |
|---|
| 666 | #define PINA2 2 |
|---|
| 667 | #define PINA1 1 |
|---|
| 668 | #define PINA0 0 |
|---|
| 669 | |
|---|
| 670 | |
|---|
| 671 | /* PORTB bit definitions */ |
|---|
| 672 | |
|---|
| 673 | #define PB7 7 |
|---|
| 674 | #define PB6 6 |
|---|
| 675 | #define PB5 5 |
|---|
| 676 | #define PB4 4 |
|---|
| 677 | #define PB3 3 |
|---|
| 678 | #define PB2 2 |
|---|
| 679 | #define PB1 1 |
|---|
| 680 | #define PB0 0 |
|---|
| 681 | |
|---|
| 682 | |
|---|
| 683 | |
|---|
| 684 | /* DDRB bit definitions */ |
|---|
| 685 | |
|---|
| 686 | #define DDB7 7 |
|---|
| 687 | #define DDB6 6 |
|---|
| 688 | #define DDB5 5 |
|---|
| 689 | #define DDB4 4 |
|---|
| 690 | #define DDB3 3 |
|---|
| 691 | #define DDB2 2 |
|---|
| 692 | #define DDB1 1 |
|---|
| 693 | #define DDB0 0 |
|---|
| 694 | |
|---|
| 695 | |
|---|
| 696 | |
|---|
| 697 | /* PINB bit definitions */ |
|---|
| 698 | |
|---|
| 699 | #define PINB7 7 |
|---|
| 700 | #define PINB6 6 |
|---|
| 701 | #define PINB5 5 |
|---|
| 702 | #define PINB4 4 |
|---|
| 703 | #define PINB3 3 |
|---|
| 704 | #define PINB2 2 |
|---|
| 705 | #define PINB1 1 |
|---|
| 706 | #define PINB0 0 |
|---|
| 707 | |
|---|
| 708 | |
|---|
| 709 | |
|---|
| 710 | /* PORTC bit definitions */ |
|---|
| 711 | |
|---|
| 712 | #define PC7 7 |
|---|
| 713 | #define PC6 6 |
|---|
| 714 | #define PC5 5 |
|---|
| 715 | #define PC4 4 |
|---|
| 716 | #define PC3 3 |
|---|
| 717 | #define PC2 2 |
|---|
| 718 | #define PC1 1 |
|---|
| 719 | #define PC0 0 |
|---|
| 720 | |
|---|
| 721 | |
|---|
| 722 | |
|---|
| 723 | /* DDRC bit definitions */ |
|---|
| 724 | |
|---|
| 725 | #define DDC7 7 |
|---|
| 726 | #define DDC6 6 |
|---|
| 727 | #define DDC5 5 |
|---|
| 728 | #define DDC4 4 |
|---|
| 729 | #define DDC3 3 |
|---|
| 730 | #define DDC2 2 |
|---|
| 731 | #define DDC1 1 |
|---|
| 732 | #define DDC0 0 |
|---|
| 733 | |
|---|
| 734 | |
|---|
| 735 | |
|---|
| 736 | /* PINC bit definitions */ |
|---|
| 737 | |
|---|
| 738 | #define PINC7 7 |
|---|
| 739 | #define PINC6 6 |
|---|
| 740 | #define PINC5 5 |
|---|
| 741 | #define PINC4 4 |
|---|
| 742 | #define PINC3 3 |
|---|
| 743 | #define PINC2 2 |
|---|
| 744 | #define PINC1 1 |
|---|
| 745 | #define PINC0 0 |
|---|
| 746 | |
|---|
| 747 | |
|---|
| 748 | |
|---|
| 749 | /* PORTD bit definitions */ |
|---|
| 750 | |
|---|
| 751 | #define PD7 7 |
|---|
| 752 | #define PD6 6 |
|---|
| 753 | #define PD5 5 |
|---|
| 754 | #define PD4 4 |
|---|
| 755 | #define PD3 3 |
|---|
| 756 | #define PD2 2 |
|---|
| 757 | #define PD1 1 |
|---|
| 758 | #define PD0 0 |
|---|
| 759 | |
|---|
| 760 | |
|---|
| 761 | |
|---|
| 762 | /* DDRD bit definitions */ |
|---|
| 763 | |
|---|
| 764 | #define DDD7 7 |
|---|
| 765 | #define DDD6 6 |
|---|
| 766 | #define DDD5 5 |
|---|
| 767 | #define DDD4 4 |
|---|
| 768 | #define DDD3 3 |
|---|
| 769 | #define DDD2 2 |
|---|
| 770 | #define DDD1 1 |
|---|
| 771 | #define DDD0 0 |
|---|
| 772 | |
|---|
| 773 | |
|---|
| 774 | |
|---|
| 775 | /* PIND bit definitions */ |
|---|
| 776 | |
|---|
| 777 | #define PIND7 7 |
|---|
| 778 | #define PIND6 6 |
|---|
| 779 | #define PIND5 5 |
|---|
| 780 | #define PIND4 4 |
|---|
| 781 | #define PIND3 3 |
|---|
| 782 | #define PIND2 2 |
|---|
| 783 | #define PIND1 1 |
|---|
| 784 | #define PIND0 0 |
|---|
| 785 | |
|---|
| 786 | |
|---|
| 787 | |
|---|
| 788 | /* SPSR bit definitions */ |
|---|
| 789 | |
|---|
| 790 | #define SPIF 7 |
|---|
| 791 | #define WCOL 6 |
|---|
| 792 | #define SPI2X 0 |
|---|
| 793 | |
|---|
| 794 | |
|---|
| 795 | |
|---|
| 796 | /* SPCR bit definitions */ |
|---|
| 797 | |
|---|
| 798 | #define SPIE 7 |
|---|
| 799 | #define SPE 6 |
|---|
| 800 | #define DORD 5 |
|---|
| 801 | #define MSTR 4 |
|---|
| 802 | #define CPOL 3 |
|---|
| 803 | #define CPHA 2 |
|---|
| 804 | #define SPR1 1 |
|---|
| 805 | #define SPR0 0 |
|---|
| 806 | |
|---|
| 807 | |
|---|
| 808 | |
|---|
| 809 | /* UCSR0A bit definitions */ |
|---|
| 810 | |
|---|
| 811 | #define RXC0 7 |
|---|
| 812 | #define TXC0 6 |
|---|
| 813 | #define UDRE0 5 |
|---|
| 814 | #define FE0 4 |
|---|
| 815 | #define DOR0 3 |
|---|
| 816 | #define UPE0 2 |
|---|
| 817 | #define U2X0 1 |
|---|
| 818 | #define MPCM0 0 |
|---|
| 819 | |
|---|
| 820 | |
|---|
| 821 | |
|---|
| 822 | /* UCSR0B bit definitions */ |
|---|
| 823 | |
|---|
| 824 | #define RXCIE0 7 |
|---|
| 825 | #define TXCIE0 6 |
|---|
| 826 | #define UDRIE0 5 |
|---|
| 827 | #define RXEN0 4 |
|---|
| 828 | #define TXEN0 3 |
|---|
| 829 | #define UCSZ02 2 |
|---|
| 830 | #define RXB80 1 |
|---|
| 831 | #define TXB80 0 |
|---|
| 832 | |
|---|
| 833 | |
|---|
| 834 | |
|---|
| 835 | /* ACSR bit definitions */ |
|---|
| 836 | |
|---|
| 837 | #define ACD 7 |
|---|
| 838 | #define ACBG 6 |
|---|
| 839 | #define ACO 5 |
|---|
| 840 | #define ACI 4 |
|---|
| 841 | #define ACIE 3 |
|---|
| 842 | #define ACIC 2 |
|---|
| 843 | #define ACIS1 1 |
|---|
| 844 | #define ACIS0 0 |
|---|
| 845 | |
|---|
| 846 | |
|---|
| 847 | |
|---|
| 848 | /* PORTE bit definitions */ |
|---|
| 849 | |
|---|
| 850 | #define PE2 2 |
|---|
| 851 | #define PE1 1 |
|---|
| 852 | #define PE0 0 |
|---|
| 853 | |
|---|
| 854 | |
|---|
| 855 | |
|---|
| 856 | /* DDRE bit definitions */ |
|---|
| 857 | |
|---|
| 858 | #define DDE2 2 |
|---|
| 859 | #define DDE1 1 |
|---|
| 860 | #define DDE0 0 |
|---|
| 861 | |
|---|
| 862 | |
|---|
| 863 | |
|---|
| 864 | /* PINE bit definitions */ |
|---|
| 865 | |
|---|
| 866 | #define PINE2 2 |
|---|
| 867 | #define PINE1 1 |
|---|
| 868 | #define PINE0 0 |
|---|
| 869 | |
|---|
| 870 | |
|---|
| 871 | |
|---|
| 872 | /* UCSR1A bit definitions */ |
|---|
| 873 | |
|---|
| 874 | #define RXC1 7 |
|---|
| 875 | #define TXC1 6 |
|---|
| 876 | #define UDRE1 5 |
|---|
| 877 | #define FE1 4 |
|---|
| 878 | #define DOR1 3 |
|---|
| 879 | #define UPE1 2 |
|---|
| 880 | #define U2X1 1 |
|---|
| 881 | #define MPCM1 0 |
|---|
| 882 | |
|---|
| 883 | |
|---|
| 884 | |
|---|
| 885 | /* UCSR1B bit definitions */ |
|---|
| 886 | |
|---|
| 887 | #define RXCIE1 7 |
|---|
| 888 | #define TXCIE1 6 |
|---|
| 889 | #define UDRIE1 5 |
|---|
| 890 | #define RXEN1 4 |
|---|
| 891 | #define TXEN1 3 |
|---|
| 892 | #define UCSZ12 2 |
|---|
| 893 | #define RXB81 1 |
|---|
| 894 | #define TXB81 0 |
|---|
| 895 | |
|---|
| 896 | |
|---|
| 897 | /* Constants */ |
|---|
| 898 | #define SPM_PAGESIZE 128 |
|---|
| 899 | #define RAMEND 0x4FF |
|---|
| 900 | #define XRAMEND 0xFFFF |
|---|
| 901 | #define E2END 0x1FF |
|---|
| 902 | #define E2PAGESIZE 4 |
|---|
| 903 | #define FLASHEND 0x3FFF |
|---|
| 904 | |
|---|
| 905 | |
|---|
| 906 | /* Fuses */ |
|---|
| 907 | |
|---|
| 908 | #define FUSE_MEMORY_SIZE 3 |
|---|
| 909 | |
|---|
| 910 | /* Low Fuse Byte */ |
|---|
| 911 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
|---|
| 912 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
|---|
| 913 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
|---|
| 914 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
|---|
| 915 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
|---|
| 916 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
|---|
| 917 | #define FUSE_CKOUT (unsigned char)~_BV(6) |
|---|
| 918 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) |
|---|
| 919 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
|---|
| 920 | |
|---|
| 921 | /* High Fuse Byte */ |
|---|
| 922 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
|---|
| 923 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
|---|
| 924 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
|---|
| 925 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
|---|
| 926 | #define FUSE_WDTON (unsigned char)~_BV(4) |
|---|
| 927 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
|---|
| 928 | #define FUSE_JTAGEN (unsigned char)~_BV(6) |
|---|
| 929 | #define FUSE_OCDEN (unsigned char)~_BV(7) |
|---|
| 930 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
|---|
| 931 | |
|---|
| 932 | /* Extended Fuse Byte */ |
|---|
| 933 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) |
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| 934 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) |
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| 935 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) |
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| 936 | #define FUSE_M161C (unsigned char)~_BV(4) |
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| 937 | #define EFUSE_DEFAULT (0xFF) |
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| 938 | |
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| 939 | |
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| 940 | /* Lock Bits */ |
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| 941 | #define __LOCK_BITS_EXIST |
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| 942 | #define __BOOT_LOCK_BITS_0_EXIST |
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| 943 | #define __BOOT_LOCK_BITS_1_EXIST |
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| 944 | |
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| 945 | |
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| 946 | /* Signature */ |
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| 947 | #define SIGNATURE_0 0x1E |
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| 948 | #define SIGNATURE_1 0x94 |
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| 949 | #define SIGNATURE_2 0x04 |
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| 950 | |
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| 951 | |
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| 952 | #endif /* _AVR_IOM162_H_ */ |
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