source: rtems/cpukit/score/cpu/avr/avr/iom161.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 12.7 KB
Line 
1/* Copyright (c) 2002, Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iom161.h - definitions for ATmega161 */
34
35#ifndef _AVR_IOM161_H_
36#define _AVR_IOM161_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom161.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* UART1 Baud Rate Register */
53#define UBRR1   _SFR_IO8(0x00)
54
55/* UART1 Control and Status Registers */
56#define UCSR1B  _SFR_IO8(0x01)
57#define UCSR1A  _SFR_IO8(0x02)
58
59/* UART1 I/O Data Register */
60#define UDR1    _SFR_IO8(0x03)
61
62/* 0x04 reserved */
63
64/* Input Pins, Port E */
65#define PINE    _SFR_IO8(0x05)
66
67/* Data Direction Register, Port E */
68#define DDRE    _SFR_IO8(0x06)
69
70/* Data Register, Port E */
71#define PORTE   _SFR_IO8(0x07)
72
73/* Analog Comparator Control and Status Register */
74#define ACSR    _SFR_IO8(0x08)
75
76/* UART0 Baud Rate Register */
77#define UBRR0   _SFR_IO8(0x09)
78
79/* UART0 Control and Status Registers */
80#define UCSR0B  _SFR_IO8(0x0A)
81#define UCSR0A  _SFR_IO8(0x0B)
82
83/* UART0 I/O Data Register */
84#define UDR0    _SFR_IO8(0x0C)
85
86/* SPI Control Register */
87#define SPCR    _SFR_IO8(0x0D)
88
89/* SPI Status Register */
90#define SPSR    _SFR_IO8(0x0E)
91
92/* SPI I/O Data Register */
93#define SPDR    _SFR_IO8(0x0F)
94
95/* Input Pins, Port D */
96#define PIND    _SFR_IO8(0x10)
97
98/* Data Direction Register, Port D */
99#define DDRD    _SFR_IO8(0x11)
100
101/* Data Register, Port D */
102#define PORTD   _SFR_IO8(0x12)
103
104/* Input Pins, Port C */
105#define PINC    _SFR_IO8(0x13)
106
107/* Data Direction Register, Port C */
108#define DDRC    _SFR_IO8(0x14)
109
110/* Data Register, Port C */
111#define PORTC   _SFR_IO8(0x15)
112
113/* Input Pins, Port B */
114#define PINB    _SFR_IO8(0x16)
115
116/* Data Direction Register, Port B */
117#define DDRB    _SFR_IO8(0x17)
118
119/* Data Register, Port B */
120#define PORTB   _SFR_IO8(0x18)
121
122/* Input Pins, Port A */
123#define PINA    _SFR_IO8(0x19)
124
125/* Data Direction Register, Port A */
126#define DDRA    _SFR_IO8(0x1A)
127
128/* Data Register, Port A */
129#define PORTA   _SFR_IO8(0x1B)
130
131/* EEPROM Control Register */
132#define EECR    _SFR_IO8(0x1C)
133
134/* EEPROM Data Register */
135#define EEDR    _SFR_IO8(0x1D)
136
137/* EEPROM Address Register */
138#define EEAR    _SFR_IO16(0x1E)
139#define EEARL   _SFR_IO8(0x1E)
140#define EEARH   _SFR_IO8(0x1F)
141
142/* UART Baud Register HIgh */
143#define UBRRH   _SFR_IO8(0x20)
144
145/* Watchdog Timer Control Register */
146#define WDTCR   _SFR_IO8(0x21)
147
148/* Timer/Counter2 Output Compare Register */
149#define OCR2    _SFR_IO8(0x22)
150
151/* Timer/Counter2 (8-bit) */
152#define TCNT2   _SFR_IO8(0x23)
153
154/* Timer/Counter1 Input Capture Register */
155#define ICR1    _SFR_IO16(0x24)
156#define ICR1L   _SFR_IO8(0x24)
157#define ICR1H   _SFR_IO8(0x25)
158
159/* ASynchronous mode Status Register */
160#define ASSR    _SFR_IO8(0x26)
161
162/* Timer/Counter2 Control Register */
163#define TCCR2   _SFR_IO8(0x27)
164
165/* Timer/Counter1 Output Compare RegisterB */
166#define OCR1B   _SFR_IO16(0x28)
167#define OCR1BL  _SFR_IO8(0x28)
168#define OCR1BH  _SFR_IO8(0x29)
169
170/* Timer/Counter1 Output Compare RegisterA */
171#define OCR1A   _SFR_IO16(0x2A)
172#define OCR1AL  _SFR_IO8(0x2A)
173#define OCR1AH  _SFR_IO8(0x2B)
174
175/* Timer/Counter1 */
176#define TCNT1   _SFR_IO16(0x2C)
177#define TCNT1L  _SFR_IO8(0x2C)
178#define TCNT1H  _SFR_IO8(0x2D)
179
180/* Timer/Counter1 Control Register B */
181#define TCCR1B  _SFR_IO8(0x2E)
182
183/* Timer/Counter1 Control Register A */
184#define TCCR1A  _SFR_IO8(0x2F)
185
186/* Special Function IO Register */
187#define SFIOR   _SFR_IO8(0x30)
188
189/* Timer/Counter0 Output Compare Register */
190#define OCR0    _SFR_IO8(0x31)
191
192/* Timer/Counter0 (8-bit) */
193#define TCNT0   _SFR_IO8(0x32)
194
195/* Timer/Counter0 Control Register */
196#define TCCR0   _SFR_IO8(0x33)
197
198/* MCU general Status Register */
199#define MCUSR   _SFR_IO8(0x34)
200
201/* MCU general Control Register */
202#define MCUCR   _SFR_IO8(0x35)
203
204/* Extended MCU general Control Register */
205#define EMCUCR  _SFR_IO8(0x36)
206
207/* Store Program Memory Control Register */
208#define SPMCR   _SFR_IO8(0x37)
209
210/* Timer/Counter Interrupt Flag Register */
211#define TIFR    _SFR_IO8(0x38)
212
213/* Timer/Counter Interrupt MaSK Register */
214#define TIMSK   _SFR_IO8(0x39)
215
216/* General Interrupt Flag Register */
217#define GIFR    _SFR_IO8(0x3A)
218
219/* General Interrupt MaSK register */
220#define GIMSK   _SFR_IO8(0x3B)
221
222/* 0x3C reserved */
223
224/* 0x3D..0x3E SP */
225
226/* 0x3F SREG */
227
228/* Interrupt vectors */
229
230/* External Interrupt 0 */
231#define INT0_vect                       _VECTOR(1)
232#define SIG_INTERRUPT0                  _VECTOR(1)
233
234/* External Interrupt 1 */
235#define INT1_vect                       _VECTOR(2)
236#define SIG_INTERRUPT1                  _VECTOR(2)
237
238/* External Interrupt 2 */
239#define INT2_vect                       _VECTOR(3)
240#define SIG_INTERRUPT2                  _VECTOR(3)
241
242/* Timer/Counter2 Compare Match */
243#define TIMER2_COMP_vect                _VECTOR(4)
244#define SIG_OUTPUT_COMPARE2             _VECTOR(4)
245
246/* Timer/Counter2 Overflow */
247#define TIMER2_OVF_vect                 _VECTOR(5)
248#define SIG_OVERFLOW2                   _VECTOR(5)
249
250/* Timer/Counter1 Capture Event */
251#define TIMER1_CAPT_vect                _VECTOR(6)
252#define SIG_INPUT_CAPTURE1              _VECTOR(6)
253
254/* Timer/Counter1 Compare Match A */
255#define TIMER1_COMPA_vect               _VECTOR(7)
256#define SIG_OUTPUT_COMPARE1A            _VECTOR(7)
257
258/* Timer/Counter1 Compare Match B */
259#define TIMER1_COMPB_vect               _VECTOR(8)
260#define SIG_OUTPUT_COMPARE1B            _VECTOR(8)
261
262/* Timer/Counter1 Overflow */
263#define TIMER1_OVF_vect                 _VECTOR(9)
264#define SIG_OVERFLOW1                   _VECTOR(9)
265
266/* Timer/Counter0 Compare Match */
267#define TIMER0_COMP_vect                _VECTOR(10)
268#define SIG_OUTPUT_COMPARE0             _VECTOR(10)
269
270/* Timer/Counter0 Overflow */
271#define TIMER0_OVF_vect                 _VECTOR(11)
272#define SIG_OVERFLOW0                   _VECTOR(11)
273
274/* Serial Transfer Complete */
275#define SPI_STC_vect                    _VECTOR(12)
276#define SIG_SPI                         _VECTOR(12)
277
278/* UART0, Rx Complete */
279#define UART0_RX_vect                   _VECTOR(13)
280#define SIG_UART0_RECV                  _VECTOR(13)
281
282/* UART1, Rx Complete */
283#define UART1_RX_vect                   _VECTOR(14)
284#define SIG_UART1_RECV                  _VECTOR(14)
285
286/* UART0 Data Register Empty */
287#define UART0_UDRE_vect                 _VECTOR(15)
288#define SIG_UART0_DATA                  _VECTOR(15)
289
290/* UART1 Data Register Empty */
291#define UART1_UDRE_vect                 _VECTOR(16)
292#define SIG_UART1_DATA                  _VECTOR(16)
293
294/* UART0, Tx Complete */
295#define UART0_TX_vect                   _VECTOR(17)
296#define SIG_UART0_TRANS                 _VECTOR(17)
297
298/* UART1, Tx Complete */
299#define UART1_TX_vect                   _VECTOR(18)
300#define SIG_UART1_TRANS                 _VECTOR(18)
301
302/* EEPROM Ready */
303#define EE_RDY_vect                     _VECTOR(19)
304#define SIG_EEPROM_READY                _VECTOR(19)
305
306/* Analog Comparator */
307#define ANA_COMP_vect                   _VECTOR(20)
308#define SIG_COMPARATOR                  _VECTOR(20)
309
310#define _VECTORS_SIZE 84
311
312/* Bit numbers */
313
314/* GIMSK */
315#define INT1    7
316#define INT0    6
317#define INT2    5
318
319/* GIFR */
320#define INTF1   7
321#define INTF0   6
322#define INTF2   5
323
324/* TIMSK */
325#define TOIE1   7
326#define OCIE1A  6
327#define OCIE1B  5
328#define TOIE2   4
329#define TICIE1  3
330#define OCIE2   2
331#define TOIE0   1
332#define OCIE0   0
333
334/* TIFR */
335#define TOV1    7
336#define OCF1A   6
337#define OCF1B   5
338#define TOV2    4
339#define ICF1    3
340#define OCF2    2
341#define TOV0    1
342#define OCF0    0
343
344/* MCUCR */
345#define SRE     7
346#define SRW10   6
347#define SE      5
348#define SM1     4
349#define ISC11   3
350#define ISC10   2
351#define ISC01   1
352#define ISC00   0
353
354/* EMCUCR */
355#define SM0     7
356#define SRL2    6
357#define SRL1    5
358#define SRL0    4
359#define SRW01   3
360#define SRW00   2
361#define SRW11   1
362#define ISC2    0
363
364/* SPMCR */
365#define BLBSET  3
366#define PGWRT   2
367#define PGERS   1
368#define SPMEN   0
369
370/* SFIOR */
371#define PSR2    1
372#define PSR10   0
373
374/* TCCR0 */
375#define FOC0    7
376#define PWM0    6
377#define COM01   5
378#define COM00   4
379#define CTC0    3
380#define CS02    2
381#define CS01    1
382#define CS00    0
383
384/* TCCR2 */
385#define FOC2    7
386#define PWM2    6
387#define COM21   5
388#define COM20   4
389#define CTC2    3
390#define CS22    2
391#define CS21    1
392#define CS20    0
393
394/* ASSR */
395#define AS2     3
396#define TCN2UB  2
397#define OCR2UB  1
398#define TCR2UB  0
399
400/* TCCR1A */
401#define COM1A1  7
402#define COM1A0  6
403#define COM1B1  5
404#define COM1B0  4
405#define FOC1A   3
406#define FOC1B   2
407#define PWM11   1
408#define PWM10   0
409
410/* TCCR1B */
411#define ICNC1   7
412#define ICES1   6
413#define CTC1    3
414#define CS12    2
415#define CS11    1
416#define CS10    0
417
418/* WDTCR */
419#define WDTOE   4
420#define WDE     3
421#define WDP2    2
422#define WDP1    1
423#define WDP0    0
424
425/* PORTA */
426#define PA7     7
427#define PA6     6
428#define PA5     5
429#define PA4     4
430#define PA3     3
431#define PA2     2
432#define PA1     1
433#define PA0     0
434
435/* DDRA */
436#define DDA7    7
437#define DDA6    6
438#define DDA5    5
439#define DDA4    4
440#define DDA3    3
441#define DDA2    2
442#define DDA1    1
443#define DDA0    0
444
445/* PINA */
446#define PINA7   7
447#define PINA6   6
448#define PINA5   5
449#define PINA4   4
450#define PINA3   3
451#define PINA2   2
452#define PINA1   1
453#define PINA0   0
454
455/*
456   PB7 = SCK
457   PB6 = MISO
458   PB5 = MOSI
459   PB4 = SS#
460   PB3 = TXD1 / AIN1
461   PB2 = RXD1 / AIN0
462   PB1 = OC2 / T1
463   PB0 = OC0 / T0
464 */
465
466/* PORTB */
467#define PB7     7
468#define PB6     6
469#define PB5     5
470#define PB4     4
471#define PB3     3
472#define PB2     2
473#define PB1     1
474#define PB0     0
475
476/* DDRB */
477#define DDB7    7
478#define DDB6    6
479#define DDB5    5
480#define DDB4    4
481#define DDB3    3
482#define DDB2    2
483#define DDB1    1
484#define DDB0    0
485
486/* PINB */
487#define PINB7   7
488#define PINB6   6
489#define PINB5   5
490#define PINB4   4
491#define PINB3   3
492#define PINB2   2
493#define PINB1   1
494#define PINB0   0
495
496/* PORTC */
497#define PC7      7
498#define PC6      6
499#define PC5      5
500#define PC4      4
501#define PC3      3
502#define PC2      2
503#define PC1      1
504#define PC0      0
505
506/* DDRC */
507#define DDC7    7
508#define DDC6    6
509#define DDC5    5
510#define DDC4    4
511#define DDC3    3
512#define DDC2    2
513#define DDC1    1
514#define DDC0    0
515
516/* PINC */
517#define PINC7   7
518#define PINC6   6
519#define PINC5   5
520#define PINC4   4
521#define PINC3   3
522#define PINC2   2
523#define PINC1   1
524#define PINC0   0
525
526/*
527   PD7 = RD#
528   PD6 = WR#
529   PD5 = TOSC2 / OC1A
530   PD4 = TOSC1
531   PD3 = INT1
532   PD2 = INT0
533   PD1 = TXD0
534   PD0 = RXD0
535 */
536
537/* PORTD */
538#define PD7      7
539#define PD6      6
540#define PD5      5
541#define PD4      4
542#define PD3      3
543#define PD2      2
544#define PD1      1
545#define PD0      0
546
547/* DDRD */
548#define DDD7    7
549#define DDD6    6
550#define DDD5    5
551#define DDD4    4
552#define DDD3    3
553#define DDD2    2
554#define DDD1    1
555#define DDD0    0
556
557/* PIND */
558#define PIND7   7
559#define PIND6   6
560#define PIND5   5
561#define PIND4   4
562#define PIND3   3
563#define PIND2   2
564#define PIND1   1
565#define PIND0   0
566
567/*
568   PE2 = ALE
569   PE1 = OC1B
570   PE0 = ICP / INT2
571 */
572
573/* PORTE */
574#define PE2     2
575#define PE1     1
576#define PE0     0
577
578/* DDRE */
579#define DDE2    2
580#define DDE1    1
581#define DDE0    0
582
583/* PINE */
584#define PINE2   2
585#define PINE1   1
586#define PINE0   0
587
588/* SPSR */
589#define SPIF    7
590#define WCOL    6
591#define SPI2X   0
592
593/* SPCR */
594#define SPIE    7
595#define SPE     6
596#define DORD    5
597#define MSTR    4
598#define CPOL    3
599#define CPHA    2
600#define SPR1    1
601#define SPR0    0
602
603/* UCSR0A, UCSR1A */
604#define RXC     7
605#define TXC     6
606#define UDRE    5
607#define FE      4
608#define DOR     3
609#define U2X     1
610#define MPCM    0
611
612/* UCSR0B, UCSR1B */
613#define RXCIE   7
614#define TXCIE   6
615#define UDRIE   5
616#define RXEN    4
617#define TXEN    3
618#define CHR9    2
619#define RXB8    1
620#define TXB8    0
621
622/* ACSR */
623#define ACD     7
624#define AINBG   6
625#define ACO     5
626#define ACI     4
627#define ACIE    3
628#define ACIC    2
629#define ACIS1   1
630#define ACIS0   0
631
632/* EEPROM Control Register */
633#define    EERIE        3
634#define    EEMWE        2
635#define    EEWE         1
636#define    EERE         0
637
638/* Constants */
639#define SPM_PAGESIZE 128
640#define RAMEND          0x45F
641#define XRAMEND         0xFFFF
642#define E2END           0x1FF
643#define E2PAGESIZE  0
644#define FLASHEND        0x3FFF
645
646
647/* Fuses */
648
649#define FUSE_MEMORY_SIZE 1
650
651/* Fuse Byte */
652#define FUSE_CKSEL0      (unsigned char)~_BV(0)
653#define FUSE_CKSEL1      (unsigned char)~_BV(1)
654#define FUSE_CKSEL2      (unsigned char)~_BV(2)
655#define FUSE_SUT         (unsigned char)~_BV(4)
656#define FUSE_SPIEN       (unsigned char)~_BV(5)
657#define FUSE_BOOTRST     (unsigned char)~_BV(6)
658#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN)
659
660
661/* Lock Bits */
662#define __LOCK_BITS_EXIST
663#define __BOOT_LOCK_BITS_0_EXIST
664#define __BOOT_LOCK_BITS_1_EXIST
665
666
667/* Signature */
668#define SIGNATURE_0 0x1E
669#define SIGNATURE_1 0x94
670#define SIGNATURE_2 0x01
671
672
673#endif /* _AVR_IOM161_H_ */
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