1 | /* Copyright (c) 2007 Atmel Corporation
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2 | All rights reserved.
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3 |
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4 | Redistribution and use in source and binary forms, with or without
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5 | modification, are permitted provided that the following conditions are met:
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6 |
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7 | * Redistributions of source code must retain the above copyright
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8 | notice, this list of conditions and the following disclaimer.
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9 |
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10 | * Redistributions in binary form must reproduce the above copyright
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11 | notice, this list of conditions and the following disclaimer in
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12 | the documentation and/or other materials provided with the
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13 | distribution.
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14 |
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15 | * Neither the name of the copyright holders nor the names of
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16 | contributors may be used to endorse or promote products derived
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17 | from this software without specific prior written permission.
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18 |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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29 | POSSIBILITY OF SUCH DAMAGE.
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30 | */
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31 |
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32 | /* $Id$ */
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33 |
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34 | /* avr/iom1284p.h - definitions for ATmega1284P. */
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35 |
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36 | /* This file should only be included from <avr/io.h>, never directly. */
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37 |
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38 | #ifndef _AVR_IO_H_
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39 | # error "Include <avr/io.h> instead of this file."
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40 | #endif
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41 |
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42 | #ifndef _AVR_IOXXX_H_
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43 | # define _AVR_IOXXX_H_ "iom1284p.h"
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44 | #else
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45 | # error "Attempt to include more than one <avr/ioXXX.h> file."
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46 | #endif
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47 |
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48 |
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49 | #ifndef _AVR_IOM1284P_H_
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50 | #define _AVR_IOM1284P_H_ 1
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51 |
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52 |
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53 | /* Registers and associated bit numbers */
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54 |
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55 | #define PINA _SFR_IO8(0x00)
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56 | #define PINA0 0
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57 | #define PINA1 1
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58 | #define PINA2 2
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59 | #define PINA3 3
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60 | #define PINA4 4
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61 | #define PINA5 5
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62 | #define PINA6 6
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63 | #define PINA7 7
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64 |
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65 | #define DDRA _SFR_IO8(0x01)
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66 | #define DDA0 0
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67 | #define DDA1 1
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68 | #define DDA2 2
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69 | #define DDA3 3
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70 | #define DDA4 4
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71 | #define DDA5 5
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72 | #define DDA6 6
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73 | #define DDA7 7
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74 |
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75 | #define PORTA _SFR_IO8(0x02)
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76 | #define PORTA0 0
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77 | #define PORTA1 1
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78 | #define PORTA2 2
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79 | #define PORTA3 3
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80 | #define PORTA4 4
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81 | #define PORTA5 5
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82 | #define PORTA6 6
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83 | #define PORTA7 7
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84 |
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85 | #define PINB _SFR_IO8(0x03)
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86 | #define PINB0 0
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87 | #define PINB1 1
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88 | #define PINB2 2
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89 | #define PINB3 3
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90 | #define PINB4 4
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91 | #define PINB5 5
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92 | #define PINB6 6
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93 | #define PINB7 7
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94 |
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95 | #define DDRB _SFR_IO8(0x04)
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96 | #define DDB0 0
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97 | #define DDB1 1
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98 | #define DDB2 2
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99 | #define DDB3 3
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100 | #define DDB4 4
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101 | #define DDB5 5
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102 | #define DDB6 6
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103 | #define DDB7 7
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104 |
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105 | #define PORTB _SFR_IO8(0x05)
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106 | #define PORTB0 0
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107 | #define PORTB1 1
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108 | #define PORTB2 2
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109 | #define PORTB3 3
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110 | #define PORTB4 4
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111 | #define PORTB5 5
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112 | #define PORTB6 6
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113 | #define PORTB7 7
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114 |
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115 | #define PINC _SFR_IO8(0x06)
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116 | #define PINC0 0
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117 | #define PINC1 1
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118 | #define PINC2 2
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119 | #define PINC3 3
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120 | #define PINC4 4
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121 | #define PINC5 5
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122 | #define PINC6 6
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123 | #define PINC7 7
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124 |
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125 | #define DDRC _SFR_IO8(0x07)
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126 | #define DDC0 0
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127 | #define DDC1 1
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128 | #define DDC2 2
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129 | #define DDC3 3
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130 | #define DDC4 4
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131 | #define DDC5 5
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132 | #define DDC6 6
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133 | #define DDC7 7
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134 |
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135 | #define PORTC _SFR_IO8(0x08)
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136 | #define PORTC0 0
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137 | #define PORTC1 1
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138 | #define PORTC2 2
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139 | #define PORTC3 3
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140 | #define PORTC4 4
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141 | #define PORTC5 5
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142 | #define PORTC6 6
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143 | #define PORTC7 7
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144 |
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145 | #define PIND _SFR_IO8(0x09)
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146 | #define PIND0 0
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147 | #define PIND1 1
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148 | #define PIND2 2
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149 | #define PIND3 3
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150 | #define PIND4 4
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151 | #define PIND5 5
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152 | #define PIND6 6
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153 | #define PIND7 7
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154 |
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155 | #define DDRD _SFR_IO8(0x0A)
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156 | #define DDD0 0
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157 | #define DDD1 1
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158 | #define DDD2 2
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159 | #define DDD3 3
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160 | #define DDD4 4
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161 | #define DDD5 5
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162 | #define DDD6 6
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163 | #define DDD7 7
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164 |
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165 | #define PORTD _SFR_IO8(0x0B)
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166 | #define PORTD0 0
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167 | #define PORTD1 1
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168 | #define PORTD2 2
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169 | #define PORTD3 3
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170 | #define PORTD4 4
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171 | #define PORTD5 5
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172 | #define PORTD6 6
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173 | #define PORTD7 7
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174 |
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175 | #define TIFR0 _SFR_IO8(0x15)
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176 | #define TOV0 0
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177 | #define OCF0A 1
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178 | #define OCF0B 2
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179 |
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180 | #define TIFR1 _SFR_IO8(0x16)
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181 | #define TOV1 0
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182 | #define OCF1A 1
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183 | #define OCF1B 2
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184 | #define ICF1 5
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185 |
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186 | #define TIFR2 _SFR_IO8(0x17)
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187 | #define TOV2 0
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188 | #define OCF2A 1
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189 | #define OCF2B 2
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190 |
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191 | #define TIFR3 _SFR_IO8(0x18)
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192 | #define TOV3 0
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193 | #define OCF3A 1
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194 | #define OCF3B 2
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195 | #define ICF3 5
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196 |
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197 | #define PCIFR _SFR_IO8(0x1B)
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198 | #define PCIF0 0
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199 | #define PCIF1 1
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200 | #define PCIF2 2
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201 | #define PCIF3 3
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202 |
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203 | #define EIFR _SFR_IO8(0x1C)
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204 | #define INTF0 0
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205 | #define INTF1 1
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206 | #define INTF2 2
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207 |
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208 | #define EIMSK _SFR_IO8(0x1D)
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209 | #define INT0 0
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210 | #define INT1 1
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211 | #define INT2 2
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212 |
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213 | #define GPIOR0 _SFR_IO8(0x1E)
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214 | #define GPIOR00 0
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215 | #define GPIOR01 1
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216 | #define GPIOR02 2
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217 | #define GPIOR03 3
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218 | #define GPIOR04 4
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219 | #define GPIOR05 5
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220 | #define GPIOR06 6
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221 | #define GPIOR07 7
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222 |
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223 | #define EECR _SFR_IO8(0x1F)
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224 | #define EERE 0
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225 | #define EEPE 1
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226 | #define EEMPE 2
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227 | #define EERIE 3
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228 | #define EEPM0 4
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229 | #define EEPM1 5
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230 |
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231 | #define EEDR _SFR_IO8(0x20)
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232 | #define EEDR0 0
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233 | #define EEDR1 1
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234 | #define EEDR2 2
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235 | #define EEDR3 3
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236 | #define EEDR4 4
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237 | #define EEDR5 5
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238 | #define EEDR6 6
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239 | #define EEDR7 7
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240 |
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241 | #define EEAR _SFR_IO16(0x21)
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242 |
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243 | #define EEARL _SFR_IO8(0x21)
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244 | #define EEAR0 0
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245 | #define EEAR1 1
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246 | #define EEAR2 2
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247 | #define EEAR3 3
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248 | #define EEAR4 4
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249 | #define EEAR5 5
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250 | #define EEAR6 6
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251 | #define EEAR7 7
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252 |
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253 | #define EEARH _SFR_IO8(0x22)
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254 | #define EEAR8 0
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255 | #define EEAR9 1
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256 | #define EEAR10 2
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257 | #define EEAR11 3
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258 |
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259 | #define GTCCR _SFR_IO8(0x23)
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260 | #define PSRSYNC 0
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261 | #define PSRASY 1
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262 | #define TSM 7
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263 |
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264 | #define TCCR0A _SFR_IO8(0x24)
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265 | #define WGM00 0
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266 | #define WGM01 1
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267 | #define COM0B0 4
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268 | #define COM0B1 5
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269 | #define COM0A0 6
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270 | #define COM0A1 7
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271 |
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272 | #define TCCR0B _SFR_IO8(0x25)
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273 | #define CS00 0
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274 | #define CS01 1
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275 | #define CS02 2
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276 | #define WGM02 3
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277 | #define FOC0B 6
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278 | #define FOC0A 7
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279 |
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280 | #define TCNT0 _SFR_IO8(0x26)
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281 | #define TCNT0_0 0
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282 | #define TCNT0_1 1
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283 | #define TCNT0_2 2
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284 | #define TCNT0_3 3
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285 | #define TCNT0_4 4
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286 | #define TCNT0_5 5
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287 | #define TCNT0_6 6
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288 | #define TCNT0_7 7
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289 |
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290 | #define OCR0A _SFR_IO8(0x27)
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291 | #define OCR0A_0 0
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292 | #define OCR0A_1 1
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293 | #define OCR0A_2 2
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294 | #define OCR0A_3 3
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295 | #define OCR0A_4 4
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296 | #define OCR0A_5 5
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297 | #define OCR0A_6 6
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298 | #define OCR0A_7 7
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299 |
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300 | #define OCR0B _SFR_IO8(0x28)
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301 | #define OCR0B_0 0
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302 | #define OCR0B_1 1
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303 | #define OCR0B_2 2
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304 | #define OCR0B_3 3
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305 | #define OCR0B_4 4
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306 | #define OCR0B_5 5
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307 | #define OCR0B_6 6
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308 | #define OCR0B_7 7
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309 |
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310 | #define GPIOR1 _SFR_IO8(0x2A)
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311 | #define GPIOR10 0
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312 | #define GPIOR11 1
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313 | #define GPIOR12 2
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314 | #define GPIOR13 3
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315 | #define GPIOR14 4
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316 | #define GPIOR15 5
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317 | #define GPIOR16 6
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318 | #define GPIOR17 7
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319 |
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320 | #define GPIOR2 _SFR_IO8(0x2B)
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321 | #define GPIOR20 0
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322 | #define GPIOR21 1
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323 | #define GPIOR22 2
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324 | #define GPIOR23 3
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325 | #define GPIOR24 4
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326 | #define GPIOR25 5
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327 | #define GPIOR26 6
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328 | #define GPIOR27 7
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329 |
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330 | #define SPCR _SFR_IO8(0x2C)
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331 | #define SPR0 0
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332 | #define SPR1 1
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333 | #define CPHA 2
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334 | #define CPOL 3
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335 | #define MSTR 4
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336 | #define DORD 5
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337 | #define SPE 6
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338 | #define SPIE 7
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339 |
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340 | #define SPSR _SFR_IO8(0x2D)
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341 | #define SPI2X 0
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342 | #define WCOL 6
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343 | #define SPIF 7
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344 |
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345 | #define SPDR _SFR_IO8(0x2E)
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346 | #define SPDR0 0
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347 | #define SPDR1 1
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348 | #define SPDR2 2
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349 | #define SPDR3 3
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350 | #define SPDR4 4
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351 | #define SPDR5 5
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352 | #define SPDR6 6
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353 | #define SPDR7 7
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354 |
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355 | #define ACSR _SFR_IO8(0x30)
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356 | #define ACIS0 0
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357 | #define ACIS1 1
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358 | #define ACIC 2
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359 | #define ACIE 3
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360 | #define ACI 4
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361 | #define ACO 5
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362 | #define ACBG 6
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363 | #define ACD 7
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364 |
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365 | #define OCDR _SFR_IO8(0x31)
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366 | #define OCDR0 0
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367 | #define OCDR1 1
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368 | #define OCDR2 2
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369 | #define OCDR3 3
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370 | #define OCDR4 4
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371 | #define OCDR5 5
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372 | #define OCDR6 6
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373 | #define OCDR7 7
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374 |
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375 | #define SMCR _SFR_IO8(0x33)
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376 | #define SE 0
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377 | #define SM0 1
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378 | #define SM1 2
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379 | #define SM2 3
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380 |
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381 | #define MCUSR _SFR_IO8(0x34)
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382 | #define PORF 0
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383 | #define EXTRF 1
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384 | #define BORF 2
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385 | #define WDRF 3
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386 | #define JTRF 4
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387 |
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388 | #define MCUCR _SFR_IO8(0x35)
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389 | #define IVCE 0
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390 | #define IVSEL 1
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391 | #define PUD 4
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392 | #define BODSE 5
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393 | #define BODS 6
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394 | #define JTD 7
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395 |
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396 | #define SPMCSR _SFR_IO8(0x37)
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397 | #define SPMEN 0
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398 | #define PGERS 1
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399 | #define PGWRT 2
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400 | #define BLBSET 3
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401 | #define RWWSRE 4
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402 | #define SIGRD 5
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403 | #define RWWSB 6
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404 | #define SPMIE 7
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405 |
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406 | #define RAMPZ _SFR_IO8(0x3B)
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407 | #define RAMPZ0 0
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408 |
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409 | #define WDTCSR _SFR_MEM8(0x60)
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410 | #define WDP0 0
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411 | #define WDP1 1
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412 | #define WDP2 2
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413 | #define WDE 3
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414 | #define WDCE 4
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415 | #define WDP3 5
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416 | #define WDIE 6
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417 | #define WDIF 7
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418 |
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419 | #define CLKPR _SFR_MEM8(0x61)
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420 | #define CLKPS0 0
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421 | #define CLKPS1 1
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422 | #define CLKPS2 2
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423 | #define CLKPS3 3
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424 | #define CLKPCE 7
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425 |
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426 | #define PRR0 _SFR_MEM8(0x64)
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427 | #define PRADC 0
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428 | #define PRUSART0 1
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429 | #define PRSPI 2
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430 | #define PRTIM1 3
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431 | #define PRUSART1 4
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432 | #define PRTIM0 5
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433 | #define PRTIM2 6
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434 | #define PRTWI 7
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435 |
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436 | #define PRR1 _SFR_MEM8(0x65)
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437 | #define PRTIM3 0
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438 |
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439 | #define OSCCAL _SFR_MEM8(0x66)
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440 | #define CAL0 0
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441 | #define CAL1 1
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442 | #define CAL2 2
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443 | #define CAL3 3
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444 | #define CAL4 4
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445 | #define CAL5 5
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446 | #define CAL6 6
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447 | #define CAL7 7
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448 |
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449 | #define PCICR _SFR_MEM8(0x68)
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450 | #define PCIE0 0
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451 | #define PCIE1 1
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452 | #define PCIE2 2
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453 | #define PCIE3 3
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454 |
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455 | #define EICRA _SFR_MEM8(0x69)
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456 | #define ISC00 0
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457 | #define ISC01 1
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458 | #define ISC10 2
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459 | #define ISC11 3
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460 | #define ISC20 4
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461 | #define ISC21 5
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462 |
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463 | #define PCMSK0 _SFR_MEM8(0x6B)
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464 | #define PCINT0 0
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465 | #define PCINT1 1
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466 | #define PCINT2 2
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467 | #define PCINT3 3
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468 | #define PCINT4 4
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469 | #define PCINT5 5
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470 | #define PCINT6 6
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471 | #define PCINT7 7
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472 |
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473 | #define PCMSK1 _SFR_MEM8(0x6C)
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474 | #define PCINT8 0
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475 | #define PCINT9 1
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476 | #define PCINT10 2
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477 | #define PCINT11 3
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478 | #define PCINT12 4
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479 | #define PCINT13 5
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480 | #define PCINT14 6
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481 | #define PCINT15 7
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482 |
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483 | #define PCMSK2 _SFR_MEM8(0x6D)
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484 | #define PCINT16 0
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485 | #define PCINT17 1
|
---|
486 | #define PCINT18 2
|
---|
487 | #define PCINT19 3
|
---|
488 | #define PCINT20 4
|
---|
489 | #define PCINT21 5
|
---|
490 | #define PCINT22 6
|
---|
491 | #define PCINT23 7
|
---|
492 |
|
---|
493 | #define TIMSK0 _SFR_MEM8(0x6E)
|
---|
494 | #define TOIE0 0
|
---|
495 | #define OCIE0A 1
|
---|
496 | #define OCIE0B 2
|
---|
497 |
|
---|
498 | #define TIMSK1 _SFR_MEM8(0x6F)
|
---|
499 | #define TOIE1 0
|
---|
500 | #define OCIE1A 1
|
---|
501 | #define OCIE1B 2
|
---|
502 | #define ICIE1 5
|
---|
503 |
|
---|
504 | #define TIMSK2 _SFR_MEM8(0x70)
|
---|
505 | #define TOIE2 0
|
---|
506 | #define OCIE2A 1
|
---|
507 | #define OCIE2B 2
|
---|
508 |
|
---|
509 | #define TIMSK3 _SFR_MEM8(0x71)
|
---|
510 | #define TOIE3 0
|
---|
511 | #define OCIE3A 1
|
---|
512 | #define OCIE3B 2
|
---|
513 | #define ICIE3 5
|
---|
514 |
|
---|
515 | #define PCMSK3 _SFR_MEM8(0x73)
|
---|
516 | #define PCINT24 0
|
---|
517 | #define PCINT25 1
|
---|
518 | #define PCINT26 2
|
---|
519 | #define PCINT27 3
|
---|
520 | #define PCINT28 4
|
---|
521 | #define PCINT29 5
|
---|
522 | #define PCINT30 6
|
---|
523 | #define PCINT31 7
|
---|
524 |
|
---|
525 | #ifndef __ASSEMBLER__
|
---|
526 | #define ADC _SFR_MEM16(0x78)
|
---|
527 | #endif
|
---|
528 | #define ADCW _SFR_MEM16(0x78)
|
---|
529 |
|
---|
530 | #define ADCL _SFR_MEM8(0x78)
|
---|
531 | #define ADCL0 0
|
---|
532 | #define ADCL1 1
|
---|
533 | #define ADCL2 2
|
---|
534 | #define ADCL3 3
|
---|
535 | #define ADCL4 4
|
---|
536 | #define ADCL5 5
|
---|
537 | #define ADCL6 6
|
---|
538 | #define ADCL7 7
|
---|
539 |
|
---|
540 | #define ADCH _SFR_MEM8(0x79)
|
---|
541 | #define ADCH0 0
|
---|
542 | #define ADCH1 1
|
---|
543 | #define ADCH2 2
|
---|
544 | #define ADCH3 3
|
---|
545 | #define ADCH4 4
|
---|
546 | #define ADCH5 5
|
---|
547 | #define ADCH6 6
|
---|
548 | #define ADCH7 7
|
---|
549 |
|
---|
550 | #define ADCSRA _SFR_MEM8(0x7A)
|
---|
551 | #define ADPS0 0
|
---|
552 | #define ADPS1 1
|
---|
553 | #define ADPS2 2
|
---|
554 | #define ADIE 3
|
---|
555 | #define ADIF 4
|
---|
556 | #define ADATE 5
|
---|
557 | #define ADSC 6
|
---|
558 | #define ADEN 7
|
---|
559 |
|
---|
560 | #define ADCSRB _SFR_MEM8(0x7B)
|
---|
561 | #define ADTS0 0
|
---|
562 | #define ADTS1 1
|
---|
563 | #define ADTS2 2
|
---|
564 | #define ACME 6
|
---|
565 |
|
---|
566 | #define ADMUX _SFR_MEM8(0x7C)
|
---|
567 | #define MUX0 0
|
---|
568 | #define MUX1 1
|
---|
569 | #define MUX2 2
|
---|
570 | #define MUX3 3
|
---|
571 | #define MUX4 4
|
---|
572 | #define ADLAR 5
|
---|
573 | #define REFS0 6
|
---|
574 | #define REFS1 7
|
---|
575 |
|
---|
576 | #define DIDR0 _SFR_MEM8(0x7E)
|
---|
577 | #define ADC0D 0
|
---|
578 | #define ADC1D 1
|
---|
579 | #define ADC2D 2
|
---|
580 | #define ADC3D 3
|
---|
581 | #define ADC4D 4
|
---|
582 | #define ADC5D 5
|
---|
583 | #define ADC6D 6
|
---|
584 | #define ADC7D 7
|
---|
585 |
|
---|
586 | #define DIDR1 _SFR_MEM8(0x7F)
|
---|
587 | #define AIN0D 0
|
---|
588 | #define AIN1D 1
|
---|
589 |
|
---|
590 | #define TCCR1A _SFR_MEM8(0x80)
|
---|
591 | #define WGM10 0
|
---|
592 | #define WGM11 1
|
---|
593 | #define COM1B0 4
|
---|
594 | #define COM1B1 5
|
---|
595 | #define COM1A0 6
|
---|
596 | #define COM1A1 7
|
---|
597 |
|
---|
598 | #define TCCR1B _SFR_MEM8(0x81)
|
---|
599 | #define CS10 0
|
---|
600 | #define CS11 1
|
---|
601 | #define CS12 2
|
---|
602 | #define WGM12 3
|
---|
603 | #define WGM13 4
|
---|
604 | #define ICES1 6
|
---|
605 | #define ICNC1 7
|
---|
606 |
|
---|
607 | #define TCCR1C _SFR_MEM8(0x82)
|
---|
608 | #define FOC1B 6
|
---|
609 | #define FOC1A 7
|
---|
610 |
|
---|
611 | #define TCNT1 _SFR_MEM16(0x84)
|
---|
612 |
|
---|
613 | #define TCNT1L _SFR_MEM8(0x84)
|
---|
614 | #define TCNT1L0 0
|
---|
615 | #define TCNT1L1 1
|
---|
616 | #define TCNT1L2 2
|
---|
617 | #define TCNT1L3 3
|
---|
618 | #define TCNT1L4 4
|
---|
619 | #define TCNT1L5 5
|
---|
620 | #define TCNT1L6 6
|
---|
621 | #define TCNT1L7 7
|
---|
622 |
|
---|
623 | #define TCNT1H _SFR_MEM8(0x85)
|
---|
624 | #define TCNT1H0 0
|
---|
625 | #define TCNT1H1 1
|
---|
626 | #define TCNT1H2 2
|
---|
627 | #define TCNT1H3 3
|
---|
628 | #define TCNT1H4 4
|
---|
629 | #define TCNT1H5 5
|
---|
630 | #define TCNT1H6 6
|
---|
631 | #define TCNT1H7 7
|
---|
632 |
|
---|
633 | #define ICR1 _SFR_MEM16(0x86)
|
---|
634 |
|
---|
635 | #define ICR1L _SFR_MEM8(0x86)
|
---|
636 | #define ICR1L0 0
|
---|
637 | #define ICR1L1 1
|
---|
638 | #define ICR1L2 2
|
---|
639 | #define ICR1L3 3
|
---|
640 | #define ICR1L4 4
|
---|
641 | #define ICR1L5 5
|
---|
642 | #define ICR1L6 6
|
---|
643 | #define ICR1L7 7
|
---|
644 |
|
---|
645 | #define ICR1H _SFR_MEM8(0x87)
|
---|
646 | #define ICR1H0 0
|
---|
647 | #define ICR1H1 1
|
---|
648 | #define ICR1H2 2
|
---|
649 | #define ICR1H3 3
|
---|
650 | #define ICR1H4 4
|
---|
651 | #define ICR1H5 5
|
---|
652 | #define ICR1H6 6
|
---|
653 | #define ICR1H7 7
|
---|
654 |
|
---|
655 | #define OCR1A _SFR_MEM16(0x88)
|
---|
656 |
|
---|
657 | #define OCR1AL _SFR_MEM8(0x88)
|
---|
658 | #define OCR1AL0 0
|
---|
659 | #define OCR1AL1 1
|
---|
660 | #define OCR1AL2 2
|
---|
661 | #define OCR1AL3 3
|
---|
662 | #define OCR1AL4 4
|
---|
663 | #define OCR1AL5 5
|
---|
664 | #define OCR1AL6 6
|
---|
665 | #define OCR1AL7 7
|
---|
666 |
|
---|
667 | #define OCR1AH _SFR_MEM8(0x89)
|
---|
668 | #define OCR1AH0 0
|
---|
669 | #define OCR1AH1 1
|
---|
670 | #define OCR1AH2 2
|
---|
671 | #define OCR1AH3 3
|
---|
672 | #define OCR1AH4 4
|
---|
673 | #define OCR1AH5 5
|
---|
674 | #define OCR1AH6 6
|
---|
675 | #define OCR1AH7 7
|
---|
676 |
|
---|
677 | #define OCR1B _SFR_MEM16(0x8A)
|
---|
678 |
|
---|
679 | #define OCR1BL _SFR_MEM8(0x8A)
|
---|
680 | #define OCR1AL0 0
|
---|
681 | #define OCR1AL1 1
|
---|
682 | #define OCR1AL2 2
|
---|
683 | #define OCR1AL3 3
|
---|
684 | #define OCR1AL4 4
|
---|
685 | #define OCR1AL5 5
|
---|
686 | #define OCR1AL6 6
|
---|
687 | #define OCR1AL7 7
|
---|
688 |
|
---|
689 | #define OCR1BH _SFR_MEM8(0x8B)
|
---|
690 | #define OCR1AH0 0
|
---|
691 | #define OCR1AH1 1
|
---|
692 | #define OCR1AH2 2
|
---|
693 | #define OCR1AH3 3
|
---|
694 | #define OCR1AH4 4
|
---|
695 | #define OCR1AH5 5
|
---|
696 | #define OCR1AH6 6
|
---|
697 | #define OCR1AH7 7
|
---|
698 |
|
---|
699 | #define TCCR3A _SFR_MEM8(0x90)
|
---|
700 | #define WGM30 0
|
---|
701 | #define WGM31 1
|
---|
702 | #define COM3B0 4
|
---|
703 | #define COM3B1 5
|
---|
704 | #define COM3A0 6
|
---|
705 | #define COM3A1 7
|
---|
706 |
|
---|
707 | #define TCCR3B _SFR_MEM8(0x91)
|
---|
708 | #define CS30 0
|
---|
709 | #define CS31 1
|
---|
710 | #define CS32 2
|
---|
711 | #define WGM32 3
|
---|
712 | #define WGM33 4
|
---|
713 | #define ICES3 6
|
---|
714 | #define ICNC3 7
|
---|
715 |
|
---|
716 | #define TCCR3C _SFR_MEM8(0x92)
|
---|
717 | #define FOC3B 6
|
---|
718 | #define FOC3A 7
|
---|
719 |
|
---|
720 | #define TCNT3 _SFR_MEM16(0x94)
|
---|
721 |
|
---|
722 | #define TCNT3L _SFR_MEM8(0x94)
|
---|
723 | #define TCNT3L0 0
|
---|
724 | #define TCNT3L1 1
|
---|
725 | #define TCNT3L2 2
|
---|
726 | #define TCNT3L3 3
|
---|
727 | #define TCNT3L4 4
|
---|
728 | #define TCNT3L5 5
|
---|
729 | #define TCNT3L6 6
|
---|
730 | #define TCNT3L7 7
|
---|
731 |
|
---|
732 | #define TCNT3H _SFR_MEM8(0x95)
|
---|
733 | #define TCNT3H0 0
|
---|
734 | #define TCNT3H1 1
|
---|
735 | #define TCNT3H2 2
|
---|
736 | #define TCNT3H3 3
|
---|
737 | #define TCNT3H4 4
|
---|
738 | #define TCNT3H5 5
|
---|
739 | #define TCNT3H6 6
|
---|
740 | #define TCNT3H7 7
|
---|
741 |
|
---|
742 | #define ICR3 _SFR_MEM16(0x96)
|
---|
743 |
|
---|
744 | #define ICR3L _SFR_MEM8(0x96)
|
---|
745 | #define ICR3L0 0
|
---|
746 | #define ICR3L1 1
|
---|
747 | #define ICR3L2 2
|
---|
748 | #define ICR3L3 3
|
---|
749 | #define ICR3L4 4
|
---|
750 | #define ICR3L5 5
|
---|
751 | #define ICR3L6 6
|
---|
752 | #define ICR3L7 7
|
---|
753 |
|
---|
754 | #define ICR3H _SFR_MEM8(0x97)
|
---|
755 | #define ICR3H0 0
|
---|
756 | #define ICR3H1 1
|
---|
757 | #define ICR3H2 2
|
---|
758 | #define ICR3H3 3
|
---|
759 | #define ICR3H4 4
|
---|
760 | #define ICR3H5 5
|
---|
761 | #define ICR3H6 6
|
---|
762 | #define ICR3H7 7
|
---|
763 |
|
---|
764 | #define OCR3A _SFR_MEM16(0x98)
|
---|
765 |
|
---|
766 | #define OCR3AL _SFR_MEM8(0x98)
|
---|
767 | #define OCR3AL0 0
|
---|
768 | #define OCR3AL1 1
|
---|
769 | #define OCR3AL2 2
|
---|
770 | #define OCR3AL3 3
|
---|
771 | #define OCR3AL4 4
|
---|
772 | #define OCR3AL5 5
|
---|
773 | #define OCR3AL6 6
|
---|
774 | #define OCR3AL7 7
|
---|
775 |
|
---|
776 | #define OCR3AH _SFR_MEM8(0x99)
|
---|
777 | #define OCR3AH0 0
|
---|
778 | #define OCR3AH1 1
|
---|
779 | #define OCR3AH2 2
|
---|
780 | #define OCR3AH3 3
|
---|
781 | #define OCR3AH4 4
|
---|
782 | #define OCR3AH5 5
|
---|
783 | #define OCR3AH6 6
|
---|
784 | #define OCR3AH7 7
|
---|
785 |
|
---|
786 | #define OCR3B _SFR_MEM16(0x9A)
|
---|
787 |
|
---|
788 | #define OCR3BL _SFR_MEM8(0x9A)
|
---|
789 | #define OCR3AL0 0
|
---|
790 | #define OCR3AL1 1
|
---|
791 | #define OCR3AL2 2
|
---|
792 | #define OCR3AL3 3
|
---|
793 | #define OCR3AL4 4
|
---|
794 | #define OCR3AL5 5
|
---|
795 | #define OCR3AL6 6
|
---|
796 | #define OCR3AL7 7
|
---|
797 |
|
---|
798 | #define OCR3BH _SFR_MEM8(0x9B)
|
---|
799 | #define OCR3AH0 0
|
---|
800 | #define OCR3AH1 1
|
---|
801 | #define OCR3AH2 2
|
---|
802 | #define OCR3AH3 3
|
---|
803 | #define OCR3AH4 4
|
---|
804 | #define OCR3AH5 5
|
---|
805 | #define OCR3AH6 6
|
---|
806 | #define OCR3AH7 7
|
---|
807 |
|
---|
808 | #define TCCR2A _SFR_MEM8(0xB0)
|
---|
809 | #define WGM20 0
|
---|
810 | #define WGM21 1
|
---|
811 | #define COM2B0 4
|
---|
812 | #define COM2B1 5
|
---|
813 | #define COM2A0 6
|
---|
814 | #define COM2A1 7
|
---|
815 |
|
---|
816 | #define TCCR2B _SFR_MEM8(0xB1)
|
---|
817 | #define CS20 0
|
---|
818 | #define CS21 1
|
---|
819 | #define CS22 2
|
---|
820 | #define WGM22 3
|
---|
821 | #define FOC2B 6
|
---|
822 | #define FOC2A 7
|
---|
823 |
|
---|
824 | #define TCNT2 _SFR_MEM8(0xB2)
|
---|
825 | #define TCNT2_0 0
|
---|
826 | #define TCNT2_1 1
|
---|
827 | #define TCNT2_2 2
|
---|
828 | #define TCNT2_3 3
|
---|
829 | #define TCNT2_4 4
|
---|
830 | #define TCNT2_5 5
|
---|
831 | #define TCNT2_6 6
|
---|
832 | #define TCNT2_7 7
|
---|
833 |
|
---|
834 | #define OCR2A _SFR_MEM8(0xB3)
|
---|
835 | #define OCR2_0 0
|
---|
836 | #define OCR2_1 1
|
---|
837 | #define OCR2_2 2
|
---|
838 | #define OCR2_3 3
|
---|
839 | #define OCR2_4 4
|
---|
840 | #define OCR2_5 5
|
---|
841 | #define OCR2_6 6
|
---|
842 | #define OCR2_7 7
|
---|
843 |
|
---|
844 | #define OCR2B _SFR_MEM8(0xB4)
|
---|
845 | #define OCR2_0 0
|
---|
846 | #define OCR2_1 1
|
---|
847 | #define OCR2_2 2
|
---|
848 | #define OCR2_3 3
|
---|
849 | #define OCR2_4 4
|
---|
850 | #define OCR2_5 5
|
---|
851 | #define OCR2_6 6
|
---|
852 | #define OCR2_7 7
|
---|
853 |
|
---|
854 | #define ASSR _SFR_MEM8(0xB6)
|
---|
855 | #define TCR2BUB 0
|
---|
856 | #define TCR2AUB 1
|
---|
857 | #define OCR2BUB 2
|
---|
858 | #define OCR2AUB 3
|
---|
859 | #define TCN2UB 4
|
---|
860 | #define AS2 5
|
---|
861 | #define EXCLK 6
|
---|
862 |
|
---|
863 | #define TWBR _SFR_MEM8(0xB8)
|
---|
864 | #define TWBR0 0
|
---|
865 | #define TWBR1 1
|
---|
866 | #define TWBR2 2
|
---|
867 | #define TWBR3 3
|
---|
868 | #define TWBR4 4
|
---|
869 | #define TWBR5 5
|
---|
870 | #define TWBR6 6
|
---|
871 | #define TWBR7 7
|
---|
872 |
|
---|
873 | #define TWSR _SFR_MEM8(0xB9)
|
---|
874 | #define TWPS0 0
|
---|
875 | #define TWPS1 1
|
---|
876 | #define TWS3 3
|
---|
877 | #define TWS4 4
|
---|
878 | #define TWS5 5
|
---|
879 | #define TWS6 6
|
---|
880 | #define TWS7 7
|
---|
881 |
|
---|
882 | #define TWAR _SFR_MEM8(0xBA)
|
---|
883 | #define TWGCE 0
|
---|
884 | #define TWA0 1
|
---|
885 | #define TWA1 2
|
---|
886 | #define TWA2 3
|
---|
887 | #define TWA3 4
|
---|
888 | #define TWA4 5
|
---|
889 | #define TWA5 6
|
---|
890 | #define TWA6 7
|
---|
891 |
|
---|
892 | #define TWDR _SFR_MEM8(0xBB)
|
---|
893 | #define TWD0 0
|
---|
894 | #define TWD1 1
|
---|
895 | #define TWD2 2
|
---|
896 | #define TWD3 3
|
---|
897 | #define TWD4 4
|
---|
898 | #define TWD5 5
|
---|
899 | #define TWD6 6
|
---|
900 | #define TWD7 7
|
---|
901 |
|
---|
902 | #define TWCR _SFR_MEM8(0xBC)
|
---|
903 | #define TWIE 0
|
---|
904 | #define TWEN 2
|
---|
905 | #define TWWC 3
|
---|
906 | #define TWSTO 4
|
---|
907 | #define TWSTA 5
|
---|
908 | #define TWEA 6
|
---|
909 | #define TWINT 7
|
---|
910 |
|
---|
911 | #define TWAMR _SFR_MEM8(0xBD)
|
---|
912 | #define TWAM0 1
|
---|
913 | #define TWAM1 2
|
---|
914 | #define TWAM2 3
|
---|
915 | #define TWAM3 4
|
---|
916 | #define TWAM4 5
|
---|
917 | #define TWAM5 6
|
---|
918 | #define TWAM6 7
|
---|
919 |
|
---|
920 | #define UCSR0A _SFR_MEM8(0xC0)
|
---|
921 | #define MPCM0 0
|
---|
922 | #define U2X0 1
|
---|
923 | #define UPE0 2
|
---|
924 | #define DOR0 3
|
---|
925 | #define FE0 4
|
---|
926 | #define UDRE0 5
|
---|
927 | #define TXC0 6
|
---|
928 | #define RXC0 7
|
---|
929 |
|
---|
930 | #define UCSR0B _SFR_MEM8(0xC1)
|
---|
931 | #define TXB80 0
|
---|
932 | #define RXB80 1
|
---|
933 | #define UCSZ02 2
|
---|
934 | #define TXEN0 3
|
---|
935 | #define RXEN0 4
|
---|
936 | #define UDRIE0 5
|
---|
937 | #define TXCIE0 6
|
---|
938 | #define RXCIE0 7
|
---|
939 |
|
---|
940 | #define UCSR0C _SFR_MEM8(0xC2)
|
---|
941 | #define UCPOL0 0
|
---|
942 | #define UCSZ00 1
|
---|
943 | #define UCSZ01 2
|
---|
944 | #define USBS0 3
|
---|
945 | #define UPM00 4
|
---|
946 | #define UPM01 5
|
---|
947 | #define UMSEL00 6
|
---|
948 | #define UMSEL01 7
|
---|
949 |
|
---|
950 | #define UBRR0 _SFR_MEM16(0xC4)
|
---|
951 |
|
---|
952 | #define UBRR0L _SFR_MEM8(0xC4)
|
---|
953 | #define UBRR0_0 0
|
---|
954 | #define UBRR0_1 1
|
---|
955 | #define UBRR0_2 2
|
---|
956 | #define UBRR0_3 3
|
---|
957 | #define UBRR0_4 4
|
---|
958 | #define UBRR0_5 5
|
---|
959 | #define UBRR0_6 6
|
---|
960 | #define UBRR0_7 7
|
---|
961 |
|
---|
962 | #define UBRR0H _SFR_MEM8(0xC5)
|
---|
963 | #define UBRR0_8 0
|
---|
964 | #define UBRR0_9 1
|
---|
965 | #define UBRR0_10 2
|
---|
966 | #define UBRR0_11 3
|
---|
967 |
|
---|
968 | #define UDR0 _SFR_MEM8(0xC6)
|
---|
969 | #define UDR0_0 0
|
---|
970 | #define UDR0_1 1
|
---|
971 | #define UDR0_2 2
|
---|
972 | #define UDR0_3 3
|
---|
973 | #define UDR0_4 4
|
---|
974 | #define UDR0_5 5
|
---|
975 | #define UDR0_6 6
|
---|
976 | #define UDR0_7 7
|
---|
977 |
|
---|
978 | #define UCSR1A _SFR_MEM8(0xC8)
|
---|
979 | #define MPCM1 0
|
---|
980 | #define U2X1 1
|
---|
981 | #define UPE1 2
|
---|
982 | #define DOR1 3
|
---|
983 | #define FE1 4
|
---|
984 | #define UDRE1 5
|
---|
985 | #define TXC1 6
|
---|
986 | #define RXC1 7
|
---|
987 |
|
---|
988 | #define UCSR1B _SFR_MEM8(0xC9)
|
---|
989 | #define TXB81 0
|
---|
990 | #define RXB81 1
|
---|
991 | #define UCSZ12 2
|
---|
992 | #define TXEN1 3
|
---|
993 | #define RXEN1 4
|
---|
994 | #define UDRIE1 5
|
---|
995 | #define TXCIE1 6
|
---|
996 | #define RXCIE1 7
|
---|
997 |
|
---|
998 | #define UCSR1C _SFR_MEM8(0xCA)
|
---|
999 | #define UCPOL1 0
|
---|
1000 | #define UCSZ10 1
|
---|
1001 | #define UCSZ11 2
|
---|
1002 | #define USBS1 3
|
---|
1003 | #define UPM10 4
|
---|
1004 | #define UPM11 5
|
---|
1005 | #define UMSEL10 6
|
---|
1006 | #define UMSEL11 7
|
---|
1007 |
|
---|
1008 | #define UBRR1 _SFR_MEM16(0xCC)
|
---|
1009 |
|
---|
1010 | #define UBRR1L _SFR_MEM8(0xCC)
|
---|
1011 | #define UBRR1_0 0
|
---|
1012 | #define UBRR1_1 1
|
---|
1013 | #define UBRR1_2 2
|
---|
1014 | #define UBRR1_3 3
|
---|
1015 | #define UBRR1_4 4
|
---|
1016 | #define UBRR1_5 5
|
---|
1017 | #define UBRR1_6 6
|
---|
1018 | #define UBRR1_7 7
|
---|
1019 |
|
---|
1020 | #define UBRR1H _SFR_MEM8(0xCD)
|
---|
1021 | #define UBRR1_8 0
|
---|
1022 | #define UBRR1_9 1
|
---|
1023 | #define UBRR1_10 2
|
---|
1024 | #define UBRR1_11 3
|
---|
1025 |
|
---|
1026 | #define UDR1 _SFR_MEM8(0xCE)
|
---|
1027 | #define UDR1_0 0
|
---|
1028 | #define UDR1_1 1
|
---|
1029 | #define UDR1_2 2
|
---|
1030 | #define UDR1_3 3
|
---|
1031 | #define UDR1_4 4
|
---|
1032 | #define UDR1_5 5
|
---|
1033 | #define UDR1_6 6
|
---|
1034 | #define UDR1_7 7
|
---|
1035 |
|
---|
1036 |
|
---|
1037 | /* Interrupt Vectors */
|
---|
1038 | /* Interrupt Vector 0 is the reset vector. */
|
---|
1039 |
|
---|
1040 | #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
|
---|
1041 | #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
|
---|
1042 | #define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
|
---|
1043 | #define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
|
---|
1044 | #define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
|
---|
1045 | #define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */
|
---|
1046 | #define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */
|
---|
1047 | #define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */
|
---|
1048 | #define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */
|
---|
1049 | #define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */
|
---|
1050 | #define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */
|
---|
1051 | #define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */
|
---|
1052 | #define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */
|
---|
1053 | #define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */
|
---|
1054 | #define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */
|
---|
1055 | #define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */
|
---|
1056 | #define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */
|
---|
1057 | #define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */
|
---|
1058 | #define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */
|
---|
1059 | #define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */
|
---|
1060 | #define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */
|
---|
1061 | #define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */
|
---|
1062 | #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
|
---|
1063 | #define ADC_vect _VECTOR(24) /* ADC Conversion Complete */
|
---|
1064 | #define EE_READY_vect _VECTOR(25) /* EEPROM Ready */
|
---|
1065 | #define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */
|
---|
1066 | #define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */
|
---|
1067 | #define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */
|
---|
1068 | #define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */
|
---|
1069 | #define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */
|
---|
1070 | #define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */
|
---|
1071 | #define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */
|
---|
1072 | #define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */
|
---|
1073 | #define TIMER3_OVF_vect _VECTOR(34) /* Timer/Counter3 Overflow */
|
---|
1074 |
|
---|
1075 | #define _VECTORS_SIZE (35 * 4)
|
---|
1076 |
|
---|
1077 |
|
---|
1078 | /* Constants */
|
---|
1079 | #define SPM_PAGESIZE 256
|
---|
1080 | #define RAMEND 0x40FF /* Last On-Chip SRAM Location */
|
---|
1081 | #define XRAMSIZE 0
|
---|
1082 | #define XRAMEND RAMEND
|
---|
1083 | #define E2END 0xFFF
|
---|
1084 | #define E2PAGESIZE 8
|
---|
1085 | #define FLASHEND 0x1FFFF
|
---|
1086 |
|
---|
1087 |
|
---|
1088 | /* Fuses */
|
---|
1089 | #define FUSE_MEMORY_SIZE 3
|
---|
1090 |
|
---|
1091 | /* Low Fuse Byte */
|
---|
1092 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
|
---|
1093 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
|
---|
1094 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
|
---|
1095 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
|
---|
1096 | #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
|
---|
1097 | #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
|
---|
1098 | #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
|
---|
1099 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
|
---|
1100 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
|
---|
1101 |
|
---|
1102 | /* High Fuse Byte */
|
---|
1103 | #define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
|
---|
1104 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
|
---|
1105 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
|
---|
1106 | #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
|
---|
1107 | #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
|
---|
1108 | #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
|
---|
1109 | #define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
|
---|
1110 | #define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
|
---|
1111 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN)
|
---|
1112 |
|
---|
1113 | /* Extended Fuse Byte */
|
---|
1114 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
|
---|
1115 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
|
---|
1116 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
|
---|
1117 | #define EFUSE_DEFAULT (0xFF)
|
---|
1118 |
|
---|
1119 |
|
---|
1120 | /* Lock Bits */
|
---|
1121 | #define __LOCK_BITS_EXIST
|
---|
1122 | #define __BOOT_LOCK_BITS_0_EXIST
|
---|
1123 | #define __BOOT_LOCK_BITS_1_EXIST
|
---|
1124 |
|
---|
1125 |
|
---|
1126 | /* Signature */
|
---|
1127 | #define SIGNATURE_0 0x1E
|
---|
1128 | #define SIGNATURE_1 0x97
|
---|
1129 | #define SIGNATURE_2 0x05
|
---|
1130 |
|
---|
1131 |
|
---|
1132 | #endif /* _AVR_IOM1284P_H_ */
|
---|