1 | /** |
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2 | * @file avr/iom128.h |
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3 | * |
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4 | * @brief Definitions for ATmega128 |
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5 | * |
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6 | * This file should only be included from <avr/io.h>, never directly. |
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7 | * |
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8 | * As of 2002-08-27: |
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9 | * - This should be up to date with data sheet 2467E-AVR-05/02 |
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10 | */ |
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11 | |
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12 | /* |
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13 | * Copyright (c) 2002, Peter Jansen |
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14 | * Copyright (c) 2007, Atmel Corporation |
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15 | * All rights reserved. |
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16 | * |
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17 | * Redistribution and use in source and binary forms, with or without |
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18 | * modification, are permitted provided that the following conditions are met: |
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19 | * |
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20 | * * Redistributions of source code must retain the above copyright |
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21 | * notice, this list of conditions and the following disclaimer. |
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22 | * |
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23 | * * Redistributions in binary form must reproduce the above copyright |
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24 | * notice, this list of conditions and the following disclaimer in |
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25 | * the documentation and/or other materials provided with the |
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26 | * distribution. |
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27 | * |
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28 | * * Neither the name of the copyright holders nor the names of |
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29 | * contributors may be used to endorse or promote products derived |
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30 | * from this software without specific prior written permission. |
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31 | * |
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32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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35 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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36 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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37 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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38 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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39 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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40 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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41 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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42 | * POSSIBILITY OF SUCH DAMAGE. |
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43 | */ |
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44 | |
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45 | #ifndef _AVR_IOM128_H_ |
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46 | #define _AVR_IOM128_H_ 1 |
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47 | |
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48 | /** |
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49 | * @defgroup Avr_iom128 ATmega128 Definitions |
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50 | * |
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51 | * @ingroup avr |
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52 | */ |
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53 | /**@{*/ |
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54 | |
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55 | #ifndef _AVR_IO_H_ |
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56 | # error "Include <avr/io.h> instead of this file." |
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57 | #endif |
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58 | |
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59 | #ifndef _AVR_IOXXX_H_ |
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60 | # define _AVR_IOXXX_H_ "iom128.h" |
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61 | #else |
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62 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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63 | #endif |
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64 | |
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65 | /* I/O registers */ |
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66 | |
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67 | /* Input Pins, Port F */ |
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68 | #define PINF _SFR_IO8(0x00) |
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69 | |
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70 | /* Input Pins, Port E */ |
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71 | #define PINE _SFR_IO8(0x01) |
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72 | |
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73 | /* Data Direction Register, Port E */ |
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74 | #define DDRE _SFR_IO8(0x02) |
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75 | |
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76 | /* Data Register, Port E */ |
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77 | #define PORTE _SFR_IO8(0x03) |
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78 | |
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79 | /* ADC Data Register */ |
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80 | #define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ |
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81 | #ifndef __ASSEMBLER__ |
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82 | #define ADC _SFR_IO16(0x04) |
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83 | #endif |
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84 | #define ADCL _SFR_IO8(0x04) |
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85 | #define ADCH _SFR_IO8(0x05) |
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86 | |
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87 | /* ADC Control and status register */ |
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88 | #define ADCSR _SFR_IO8(0x06) |
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89 | #define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ |
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90 | |
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91 | /* ADC Multiplexer select */ |
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92 | #define ADMUX _SFR_IO8(0x07) |
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93 | |
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94 | /* Analog Comparator Control and Status Register */ |
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95 | #define ACSR _SFR_IO8(0x08) |
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96 | |
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97 | /* USART0 Baud Rate Register Low */ |
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98 | #define UBRR0L _SFR_IO8(0x09) |
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99 | |
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100 | /* USART0 Control and Status Register B */ |
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101 | #define UCSR0B _SFR_IO8(0x0A) |
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102 | |
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103 | /* USART0 Control and Status Register A */ |
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104 | #define UCSR0A _SFR_IO8(0x0B) |
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105 | |
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106 | /* USART0 I/O Data Register */ |
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107 | #define UDR0 _SFR_IO8(0x0C) |
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108 | |
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109 | /* SPI Control Register */ |
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110 | #define SPCR _SFR_IO8(0x0D) |
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111 | |
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112 | /* SPI Status Register */ |
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113 | #define SPSR _SFR_IO8(0x0E) |
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114 | |
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115 | /* SPI I/O Data Register */ |
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116 | #define SPDR _SFR_IO8(0x0F) |
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117 | |
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118 | /* Input Pins, Port D */ |
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119 | #define PIND _SFR_IO8(0x10) |
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120 | |
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121 | /* Data Direction Register, Port D */ |
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122 | #define DDRD _SFR_IO8(0x11) |
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123 | |
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124 | /* Data Register, Port D */ |
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125 | #define PORTD _SFR_IO8(0x12) |
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126 | |
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127 | /* Input Pins, Port C */ |
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128 | #define PINC _SFR_IO8(0x13) |
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129 | |
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130 | /* Data Direction Register, Port C */ |
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131 | #define DDRC _SFR_IO8(0x14) |
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132 | |
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133 | /* Data Register, Port C */ |
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134 | #define PORTC _SFR_IO8(0x15) |
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135 | |
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136 | /* Input Pins, Port B */ |
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137 | #define PINB _SFR_IO8(0x16) |
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138 | |
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139 | /* Data Direction Register, Port B */ |
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140 | #define DDRB _SFR_IO8(0x17) |
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141 | |
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142 | /* Data Register, Port B */ |
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143 | #define PORTB _SFR_IO8(0x18) |
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144 | |
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145 | /* Input Pins, Port A */ |
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146 | #define PINA _SFR_IO8(0x19) |
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147 | |
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148 | /* Data Direction Register, Port A */ |
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149 | #define DDRA _SFR_IO8(0x1A) |
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150 | |
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151 | /* Data Register, Port A */ |
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152 | #define PORTA _SFR_IO8(0x1B) |
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153 | |
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154 | /* EEPROM Control Register */ |
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155 | #define EECR _SFR_IO8(0x1C) |
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156 | |
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157 | /* EEPROM Data Register */ |
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158 | #define EEDR _SFR_IO8(0x1D) |
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159 | |
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160 | /* EEPROM Address Register */ |
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161 | #define EEAR _SFR_IO16(0x1E) |
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162 | #define EEARL _SFR_IO8(0x1E) |
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163 | #define EEARH _SFR_IO8(0x1F) |
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164 | |
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165 | /* Special Function I/O Register */ |
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166 | #define SFIOR _SFR_IO8(0x20) |
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167 | |
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168 | /* Watchdog Timer Control Register */ |
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169 | #define WDTCR _SFR_IO8(0x21) |
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170 | |
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171 | /* On-chip Debug Register */ |
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172 | #define OCDR _SFR_IO8(0x22) |
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173 | |
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174 | /* Timer2 Output Compare Register */ |
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175 | #define OCR2 _SFR_IO8(0x23) |
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176 | |
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177 | /* Timer/Counter 2 */ |
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178 | #define TCNT2 _SFR_IO8(0x24) |
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179 | |
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180 | /* Timer/Counter 2 Control register */ |
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181 | #define TCCR2 _SFR_IO8(0x25) |
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182 | |
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183 | /* T/C 1 Input Capture Register */ |
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184 | #define ICR1 _SFR_IO16(0x26) |
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185 | #define ICR1L _SFR_IO8(0x26) |
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186 | #define ICR1H _SFR_IO8(0x27) |
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187 | |
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188 | /* Timer/Counter1 Output Compare Register B */ |
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189 | #define OCR1B _SFR_IO16(0x28) |
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190 | #define OCR1BL _SFR_IO8(0x28) |
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191 | #define OCR1BH _SFR_IO8(0x29) |
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192 | |
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193 | /* Timer/Counter1 Output Compare Register A */ |
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194 | #define OCR1A _SFR_IO16(0x2A) |
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195 | #define OCR1AL _SFR_IO8(0x2A) |
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196 | #define OCR1AH _SFR_IO8(0x2B) |
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197 | |
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198 | /* Timer/Counter 1 */ |
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199 | #define TCNT1 _SFR_IO16(0x2C) |
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200 | #define TCNT1L _SFR_IO8(0x2C) |
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201 | #define TCNT1H _SFR_IO8(0x2D) |
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202 | |
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203 | /* Timer/Counter 1 Control and Status Register */ |
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204 | #define TCCR1B _SFR_IO8(0x2E) |
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205 | |
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206 | /* Timer/Counter 1 Control Register */ |
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207 | #define TCCR1A _SFR_IO8(0x2F) |
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208 | |
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209 | /* Timer/Counter 0 Asynchronous Control & Status Register */ |
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210 | #define ASSR _SFR_IO8(0x30) |
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211 | |
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212 | /* Output Compare Register 0 */ |
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213 | #define OCR0 _SFR_IO8(0x31) |
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214 | |
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215 | /* Timer/Counter 0 */ |
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216 | #define TCNT0 _SFR_IO8(0x32) |
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217 | |
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218 | /* Timer/Counter 0 Control Register */ |
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219 | #define TCCR0 _SFR_IO8(0x33) |
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220 | |
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221 | /* MCU Status Register */ |
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222 | #define MCUSR _SFR_IO8(0x34) |
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223 | #define MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ |
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224 | |
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225 | /* MCU general Control Register */ |
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226 | #define MCUCR _SFR_IO8(0x35) |
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227 | |
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228 | /* Timer/Counter Interrupt Flag Register */ |
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229 | #define TIFR _SFR_IO8(0x36) |
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230 | |
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231 | /* Timer/Counter Interrupt MaSK register */ |
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232 | #define TIMSK _SFR_IO8(0x37) |
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233 | |
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234 | /* External Interrupt Flag Register */ |
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235 | #define EIFR _SFR_IO8(0x38) |
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236 | |
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237 | /* External Interrupt MaSK register */ |
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238 | #define EIMSK _SFR_IO8(0x39) |
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239 | |
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240 | /* External Interrupt Control Register B */ |
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241 | #define EICRB _SFR_IO8(0x3A) |
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242 | |
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243 | /* RAM Page Z select register */ |
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244 | #define RAMPZ _SFR_IO8(0x3B) |
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245 | |
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246 | /* XDIV Divide control register */ |
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247 | #define XDIV _SFR_IO8(0x3C) |
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248 | |
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249 | /* 0x3D..0x3E SP */ |
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250 | |
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251 | /* 0x3F SREG */ |
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252 | |
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253 | /* Extended I/O registers */ |
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254 | |
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255 | /* Data Direction Register, Port F */ |
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256 | #define DDRF _SFR_MEM8(0x61) |
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257 | |
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258 | /* Data Register, Port F */ |
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259 | #define PORTF _SFR_MEM8(0x62) |
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260 | |
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261 | /* Input Pins, Port G */ |
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262 | #define PING _SFR_MEM8(0x63) |
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263 | |
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264 | /* Data Direction Register, Port G */ |
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265 | #define DDRG _SFR_MEM8(0x64) |
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266 | |
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267 | /* Data Register, Port G */ |
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268 | #define PORTG _SFR_MEM8(0x65) |
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269 | |
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270 | /* Store Program Memory Control and Status Register */ |
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271 | #define SPMCR _SFR_MEM8(0x68) |
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272 | #define SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ |
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273 | |
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274 | /* External Interrupt Control Register A */ |
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275 | #define EICRA _SFR_MEM8(0x6A) |
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276 | |
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277 | /* External Memory Control Register B */ |
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278 | #define XMCRB _SFR_MEM8(0x6C) |
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279 | |
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280 | /* External Memory Control Register A */ |
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281 | #define XMCRA _SFR_MEM8(0x6D) |
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282 | |
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283 | /* Oscillator Calibration Register */ |
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284 | #define OSCCAL _SFR_MEM8(0x6F) |
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285 | |
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286 | /* 2-wire Serial Interface Bit Rate Register */ |
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287 | #define TWBR _SFR_MEM8(0x70) |
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288 | |
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289 | /* 2-wire Serial Interface Status Register */ |
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290 | #define TWSR _SFR_MEM8(0x71) |
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291 | |
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292 | /* 2-wire Serial Interface Address Register */ |
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293 | #define TWAR _SFR_MEM8(0x72) |
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294 | |
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295 | /* 2-wire Serial Interface Data Register */ |
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296 | #define TWDR _SFR_MEM8(0x73) |
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297 | |
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298 | /* 2-wire Serial Interface Control Register */ |
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299 | #define TWCR _SFR_MEM8(0x74) |
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300 | |
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301 | /* Time Counter 1 Output Compare Register C */ |
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302 | #define OCR1C _SFR_MEM16(0x78) |
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303 | #define OCR1CL _SFR_MEM8(0x78) |
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304 | #define OCR1CH _SFR_MEM8(0x79) |
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305 | |
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306 | /* Timer/Counter 1 Control Register C */ |
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307 | #define TCCR1C _SFR_MEM8(0x7A) |
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308 | |
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309 | /* Extended Timer Interrupt Flag Register */ |
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310 | #define ETIFR _SFR_MEM8(0x7C) |
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311 | |
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312 | /* Extended Timer Interrupt Mask Register */ |
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313 | #define ETIMSK _SFR_MEM8(0x7D) |
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314 | |
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315 | /* Timer/Counter 3 Input Capture Register */ |
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316 | #define ICR3 _SFR_MEM16(0x80) |
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317 | #define ICR3L _SFR_MEM8(0x80) |
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318 | #define ICR3H _SFR_MEM8(0x81) |
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319 | |
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320 | /* Timer/Counter 3 Output Compare Register C */ |
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321 | #define OCR3C _SFR_MEM16(0x82) |
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322 | #define OCR3CL _SFR_MEM8(0x82) |
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323 | #define OCR3CH _SFR_MEM8(0x83) |
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324 | |
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325 | /* Timer/Counter 3 Output Compare Register B */ |
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326 | #define OCR3B _SFR_MEM16(0x84) |
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327 | #define OCR3BL _SFR_MEM8(0x84) |
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328 | #define OCR3BH _SFR_MEM8(0x85) |
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329 | |
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330 | /* Timer/Counter 3 Output Compare Register A */ |
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331 | #define OCR3A _SFR_MEM16(0x86) |
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332 | #define OCR3AL _SFR_MEM8(0x86) |
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333 | #define OCR3AH _SFR_MEM8(0x87) |
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334 | |
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335 | /* Timer/Counter 3 Counter Register */ |
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336 | #define TCNT3 _SFR_MEM16(0x88) |
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337 | #define TCNT3L _SFR_MEM8(0x88) |
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338 | #define TCNT3H _SFR_MEM8(0x89) |
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339 | |
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340 | /* Timer/Counter 3 Control Register B */ |
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341 | #define TCCR3B _SFR_MEM8(0x8A) |
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342 | |
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343 | /* Timer/Counter 3 Control Register A */ |
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344 | #define TCCR3A _SFR_MEM8(0x8B) |
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345 | |
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346 | /* Timer/Counter 3 Control Register C */ |
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347 | #define TCCR3C _SFR_MEM8(0x8C) |
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348 | |
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349 | /* USART0 Baud Rate Register High */ |
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350 | #define UBRR0H _SFR_MEM8(0x90) |
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351 | |
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352 | /* USART0 Control and Status Register C */ |
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353 | #define UCSR0C _SFR_MEM8(0x95) |
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354 | |
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355 | /* USART1 Baud Rate Register High */ |
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356 | #define UBRR1H _SFR_MEM8(0x98) |
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357 | |
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358 | /* USART1 Baud Rate Register Low*/ |
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359 | #define UBRR1L _SFR_MEM8(0x99) |
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360 | |
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361 | /* USART1 Control and Status Register B */ |
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362 | #define UCSR1B _SFR_MEM8(0x9A) |
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363 | |
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364 | /* USART1 Control and Status Register A */ |
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365 | #define UCSR1A _SFR_MEM8(0x9B) |
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366 | |
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367 | /* USART1 I/O Data Register */ |
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368 | #define UDR1 _SFR_MEM8(0x9C) |
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369 | |
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370 | /* USART1 Control and Status Register C */ |
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371 | #define UCSR1C _SFR_MEM8(0x9D) |
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372 | |
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373 | /* Interrupt vectors */ |
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374 | |
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375 | /* External Interrupt Request 0 */ |
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376 | #define INT0_vect _VECTOR(1) |
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377 | #define SIG_INTERRUPT0 _VECTOR(1) |
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378 | |
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379 | /* External Interrupt Request 1 */ |
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380 | #define INT1_vect _VECTOR(2) |
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381 | #define SIG_INTERRUPT1 _VECTOR(2) |
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382 | |
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383 | /* External Interrupt Request 2 */ |
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384 | #define INT2_vect _VECTOR(3) |
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385 | #define SIG_INTERRUPT2 _VECTOR(3) |
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386 | |
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387 | /* External Interrupt Request 3 */ |
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388 | #define INT3_vect _VECTOR(4) |
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389 | #define SIG_INTERRUPT3 _VECTOR(4) |
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390 | |
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391 | /* External Interrupt Request 4 */ |
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392 | #define INT4_vect _VECTOR(5) |
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393 | #define SIG_INTERRUPT4 _VECTOR(5) |
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394 | |
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395 | /* External Interrupt Request 5 */ |
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396 | #define INT5_vect _VECTOR(6) |
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397 | #define SIG_INTERRUPT5 _VECTOR(6) |
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398 | |
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399 | /* External Interrupt Request 6 */ |
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400 | #define INT6_vect _VECTOR(7) |
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401 | #define SIG_INTERRUPT6 _VECTOR(7) |
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402 | |
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403 | /* External Interrupt Request 7 */ |
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404 | #define INT7_vect _VECTOR(8) |
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405 | #define SIG_INTERRUPT7 _VECTOR(8) |
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406 | |
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407 | /* Timer/Counter2 Compare Match */ |
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408 | #define TIMER2_COMP_vect _VECTOR(9) |
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409 | #define SIG_OUTPUT_COMPARE2 _VECTOR(9) |
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410 | |
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411 | /* Timer/Counter2 Overflow */ |
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412 | #define TIMER2_OVF_vect _VECTOR(10) |
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413 | #define SIG_OVERFLOW2 _VECTOR(10) |
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414 | |
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415 | /* Timer/Counter1 Capture Event */ |
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416 | #define TIMER1_CAPT_vect _VECTOR(11) |
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417 | #define SIG_INPUT_CAPTURE1 _VECTOR(11) |
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418 | |
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419 | /* Timer/Counter1 Compare Match A */ |
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420 | #define TIMER1_COMPA_vect _VECTOR(12) |
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421 | #define SIG_OUTPUT_COMPARE1A _VECTOR(12) |
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422 | |
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423 | /* Timer/Counter Compare Match B */ |
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424 | #define TIMER1_COMPB_vect _VECTOR(13) |
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425 | #define SIG_OUTPUT_COMPARE1B _VECTOR(13) |
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426 | |
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427 | /* Timer/Counter1 Overflow */ |
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428 | #define TIMER1_OVF_vect _VECTOR(14) |
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429 | #define SIG_OVERFLOW1 _VECTOR(14) |
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430 | |
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431 | /* Timer/Counter0 Compare Match */ |
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432 | #define TIMER0_COMP_vect _VECTOR(15) |
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433 | #define SIG_OUTPUT_COMPARE0 _VECTOR(15) |
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434 | |
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435 | /* Timer/Counter0 Overflow */ |
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436 | #define TIMER0_OVF_vect _VECTOR(16) |
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437 | #define SIG_OVERFLOW0 _VECTOR(16) |
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438 | |
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439 | /* SPI Serial Transfer Complete */ |
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440 | #define SPI_STC_vect _VECTOR(17) |
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441 | #define SIG_SPI _VECTOR(17) |
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442 | |
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443 | /* USART0, Rx Complete */ |
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444 | #define USART0_RX_vect _VECTOR(18) |
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445 | #define SIG_USART0_RECV _VECTOR(18) |
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446 | #define SIG_UART0_RECV _VECTOR(18) |
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447 | |
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448 | /* USART0 Data Register Empty */ |
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449 | #define USART0_UDRE_vect _VECTOR(19) |
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450 | #define SIG_USART0_DATA _VECTOR(19) |
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451 | #define SIG_UART0_DATA _VECTOR(19) |
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452 | |
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453 | /* USART0, Tx Complete */ |
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454 | #define USART0_TX_vect _VECTOR(20) |
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455 | #define SIG_USART0_TRANS _VECTOR(20) |
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456 | #define SIG_UART0_TRANS _VECTOR(20) |
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457 | |
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458 | /* ADC Conversion Complete */ |
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459 | #define ADC_vect _VECTOR(21) |
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460 | #define SIG_ADC _VECTOR(21) |
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461 | |
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462 | /* EEPROM Ready */ |
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463 | #define EE_READY_vect _VECTOR(22) |
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464 | #define SIG_EEPROM_READY _VECTOR(22) |
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465 | |
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466 | /* Analog Comparator */ |
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467 | #define ANALOG_COMP_vect _VECTOR(23) |
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468 | #define SIG_COMPARATOR _VECTOR(23) |
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469 | |
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470 | /* Timer/Counter1 Compare Match C */ |
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471 | #define TIMER1_COMPC_vect _VECTOR(24) |
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472 | #define SIG_OUTPUT_COMPARE1C _VECTOR(24) |
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473 | |
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474 | /* Timer/Counter3 Capture Event */ |
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475 | #define TIMER3_CAPT_vect _VECTOR(25) |
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476 | #define SIG_INPUT_CAPTURE3 _VECTOR(25) |
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477 | |
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478 | /* Timer/Counter3 Compare Match A */ |
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479 | #define TIMER3_COMPA_vect _VECTOR(26) |
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480 | #define SIG_OUTPUT_COMPARE3A _VECTOR(26) |
---|
481 | |
---|
482 | /* Timer/Counter3 Compare Match B */ |
---|
483 | #define TIMER3_COMPB_vect _VECTOR(27) |
---|
484 | #define SIG_OUTPUT_COMPARE3B _VECTOR(27) |
---|
485 | |
---|
486 | /* Timer/Counter3 Compare Match C */ |
---|
487 | #define TIMER3_COMPC_vect _VECTOR(28) |
---|
488 | #define SIG_OUTPUT_COMPARE3C _VECTOR(28) |
---|
489 | |
---|
490 | /* Timer/Counter3 Overflow */ |
---|
491 | #define TIMER3_OVF_vect _VECTOR(29) |
---|
492 | #define SIG_OVERFLOW3 _VECTOR(29) |
---|
493 | |
---|
494 | /* USART1, Rx Complete */ |
---|
495 | #define USART1_RX_vect _VECTOR(30) |
---|
496 | #define SIG_USART1_RECV _VECTOR(30) |
---|
497 | #define SIG_UART1_RECV _VECTOR(30) |
---|
498 | |
---|
499 | /* USART1, Data Register Empty */ |
---|
500 | #define USART1_UDRE_vect _VECTOR(31) |
---|
501 | #define SIG_USART1_DATA _VECTOR(31) |
---|
502 | #define SIG_UART1_DATA _VECTOR(31) |
---|
503 | |
---|
504 | /* USART1, Tx Complete */ |
---|
505 | #define USART1_TX_vect _VECTOR(32) |
---|
506 | #define SIG_USART1_TRANS _VECTOR(32) |
---|
507 | #define SIG_UART1_TRANS _VECTOR(32) |
---|
508 | |
---|
509 | /* 2-wire Serial Interface */ |
---|
510 | #define TWI_vect _VECTOR(33) |
---|
511 | #define SIG_2WIRE_SERIAL _VECTOR(33) |
---|
512 | |
---|
513 | /* Store Program Memory Read */ |
---|
514 | #define SPM_READY_vect _VECTOR(34) |
---|
515 | #define SIG_SPM_READY _VECTOR(34) |
---|
516 | |
---|
517 | #define _VECTORS_SIZE 140 |
---|
518 | |
---|
519 | /* |
---|
520 | The Register Bit names are represented by their bit number (0-7). |
---|
521 | */ |
---|
522 | |
---|
523 | /* 2-wire Control Register - TWCR */ |
---|
524 | #define TWINT 7 |
---|
525 | #define TWEA 6 |
---|
526 | #define TWSTA 5 |
---|
527 | #define TWSTO 4 |
---|
528 | #define TWWC 3 |
---|
529 | #define TWEN 2 |
---|
530 | #define TWIE 0 |
---|
531 | |
---|
532 | /* 2-wire Address Register - TWAR */ |
---|
533 | #define TWA6 7 |
---|
534 | #define TWA5 6 |
---|
535 | #define TWA4 5 |
---|
536 | #define TWA3 4 |
---|
537 | #define TWA2 3 |
---|
538 | #define TWA1 2 |
---|
539 | #define TWA0 1 |
---|
540 | #define TWGCE 0 |
---|
541 | |
---|
542 | /* 2-wire Status Register - TWSR */ |
---|
543 | #define TWS7 7 |
---|
544 | #define TWS6 6 |
---|
545 | #define TWS5 5 |
---|
546 | #define TWS4 4 |
---|
547 | #define TWS3 3 |
---|
548 | #define TWPS1 1 |
---|
549 | #define TWPS0 0 |
---|
550 | |
---|
551 | /* External Memory Control Register A - XMCRA */ |
---|
552 | #define SRL2 6 |
---|
553 | #define SRL1 5 |
---|
554 | #define SRL0 4 |
---|
555 | #define SRW01 3 |
---|
556 | #define SRW00 2 |
---|
557 | #define SRW11 1 |
---|
558 | |
---|
559 | /* External Memory Control Register B - XMCRA */ |
---|
560 | #define XMBK 7 |
---|
561 | #define XMM2 2 |
---|
562 | #define XMM1 1 |
---|
563 | #define XMM0 0 |
---|
564 | |
---|
565 | /* XDIV Divide control register - XDIV */ |
---|
566 | #define XDIVEN 7 |
---|
567 | #define XDIV6 6 |
---|
568 | #define XDIV5 5 |
---|
569 | #define XDIV4 4 |
---|
570 | #define XDIV3 3 |
---|
571 | #define XDIV2 2 |
---|
572 | #define XDIV1 1 |
---|
573 | #define XDIV0 0 |
---|
574 | |
---|
575 | /* RAM Page Z select register - RAMPZ */ |
---|
576 | #define RAMPZ0 0 |
---|
577 | |
---|
578 | /* External Interrupt Control Register A - EICRA */ |
---|
579 | #define ISC31 7 |
---|
580 | #define ISC30 6 |
---|
581 | #define ISC21 5 |
---|
582 | #define ISC20 4 |
---|
583 | #define ISC11 3 |
---|
584 | #define ISC10 2 |
---|
585 | #define ISC01 1 |
---|
586 | #define ISC00 0 |
---|
587 | |
---|
588 | /* External Interrupt Control Register B - EICRB */ |
---|
589 | #define ISC71 7 |
---|
590 | #define ISC70 6 |
---|
591 | #define ISC61 5 |
---|
592 | #define ISC60 4 |
---|
593 | #define ISC51 3 |
---|
594 | #define ISC50 2 |
---|
595 | #define ISC41 1 |
---|
596 | #define ISC40 0 |
---|
597 | |
---|
598 | /* Store Program Memory Control Register - SPMCSR, SPMCR */ |
---|
599 | #define SPMIE 7 |
---|
600 | #define RWWSB 6 |
---|
601 | #define RWWSRE 4 |
---|
602 | #define BLBSET 3 |
---|
603 | #define PGWRT 2 |
---|
604 | #define PGERS 1 |
---|
605 | #define SPMEN 0 |
---|
606 | |
---|
607 | /* External Interrupt MaSK register - EIMSK */ |
---|
608 | #define INT7 7 |
---|
609 | #define INT6 6 |
---|
610 | #define INT5 5 |
---|
611 | #define INT4 4 |
---|
612 | #define INT3 3 |
---|
613 | #define INT2 2 |
---|
614 | #define INT1 1 |
---|
615 | #define INT0 0 |
---|
616 | |
---|
617 | /* External Interrupt Flag Register - EIFR */ |
---|
618 | #define INTF7 7 |
---|
619 | #define INTF6 6 |
---|
620 | #define INTF5 5 |
---|
621 | #define INTF4 4 |
---|
622 | #define INTF3 3 |
---|
623 | #define INTF2 2 |
---|
624 | #define INTF1 1 |
---|
625 | #define INTF0 0 |
---|
626 | |
---|
627 | /* Timer/Counter Interrupt MaSK register - TIMSK */ |
---|
628 | #define OCIE2 7 |
---|
629 | #define TOIE2 6 |
---|
630 | #define TICIE1 5 |
---|
631 | #define OCIE1A 4 |
---|
632 | #define OCIE1B 3 |
---|
633 | #define TOIE1 2 |
---|
634 | #define OCIE0 1 |
---|
635 | #define TOIE0 0 |
---|
636 | |
---|
637 | /* Timer/Counter Interrupt Flag Register - TIFR */ |
---|
638 | #define OCF2 7 |
---|
639 | #define TOV2 6 |
---|
640 | #define ICF1 5 |
---|
641 | #define OCF1A 4 |
---|
642 | #define OCF1B 3 |
---|
643 | #define TOV1 2 |
---|
644 | #define OCF0 1 |
---|
645 | #define TOV0 0 |
---|
646 | |
---|
647 | /* Extended Timer Interrupt MaSK register - ETIMSK */ |
---|
648 | #define TICIE3 5 |
---|
649 | #define OCIE3A 4 |
---|
650 | #define OCIE3B 3 |
---|
651 | #define TOIE3 2 |
---|
652 | #define OCIE3C 1 |
---|
653 | #define OCIE1C 0 |
---|
654 | |
---|
655 | /* Extended Timer Interrupt Flag Register - ETIFR */ |
---|
656 | #define ICF3 5 |
---|
657 | #define OCF3A 4 |
---|
658 | #define OCF3B 3 |
---|
659 | #define TOV3 2 |
---|
660 | #define OCF3C 1 |
---|
661 | #define OCF1C 0 |
---|
662 | |
---|
663 | /* MCU general Control Register - MCUCR */ |
---|
664 | #define SRE 7 |
---|
665 | #define SRW 6 |
---|
666 | #define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ |
---|
667 | #define SE 5 |
---|
668 | #define SM1 4 |
---|
669 | #define SM0 3 |
---|
670 | #define SM2 2 |
---|
671 | #define IVSEL 1 |
---|
672 | #define IVCE 0 |
---|
673 | |
---|
674 | /* MCU Status Register - MCUSR, MCUCSR */ |
---|
675 | #define JTD 7 |
---|
676 | #define JTRF 4 |
---|
677 | #define WDRF 3 |
---|
678 | #define BORF 2 |
---|
679 | #define EXTRF 1 |
---|
680 | #define PORF 0 |
---|
681 | |
---|
682 | /* Timer/Counter Control Register (generic) */ |
---|
683 | #define FOC 7 |
---|
684 | #define WGM0 6 |
---|
685 | #define COM1 5 |
---|
686 | #define COM0 4 |
---|
687 | #define WGM1 3 |
---|
688 | #define CS2 2 |
---|
689 | #define CS1 1 |
---|
690 | #define CS0 0 |
---|
691 | |
---|
692 | /* Timer/Counter 0 Control Register - TCCR0 */ |
---|
693 | #define FOC0 7 |
---|
694 | #define WGM00 6 |
---|
695 | #define COM01 5 |
---|
696 | #define COM00 4 |
---|
697 | #define WGM01 3 |
---|
698 | #define CS02 2 |
---|
699 | #define CS01 1 |
---|
700 | #define CS00 0 |
---|
701 | |
---|
702 | /* Timer/Counter 2 Control Register - TCCR2 */ |
---|
703 | #define FOC2 7 |
---|
704 | #define WGM20 6 |
---|
705 | #define COM21 5 |
---|
706 | #define COM20 4 |
---|
707 | #define WGM21 3 |
---|
708 | #define CS22 2 |
---|
709 | #define CS21 1 |
---|
710 | #define CS20 0 |
---|
711 | |
---|
712 | /* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ |
---|
713 | #define AS0 3 |
---|
714 | #define TCN0UB 2 |
---|
715 | #define OCR0UB 1 |
---|
716 | #define TCR0UB 0 |
---|
717 | |
---|
718 | /* Timer/Counter Control Register A (generic) */ |
---|
719 | #define COMA1 7 |
---|
720 | #define COMA0 6 |
---|
721 | #define COMB1 5 |
---|
722 | #define COMB0 4 |
---|
723 | #define COMC1 3 |
---|
724 | #define COMC0 2 |
---|
725 | #define WGMA1 1 |
---|
726 | #define WGMA0 0 |
---|
727 | |
---|
728 | /* Timer/Counter 1 Control and Status Register A - TCCR1A */ |
---|
729 | #define COM1A1 7 |
---|
730 | #define COM1A0 6 |
---|
731 | #define COM1B1 5 |
---|
732 | #define COM1B0 4 |
---|
733 | #define COM1C1 3 |
---|
734 | #define COM1C0 2 |
---|
735 | #define WGM11 1 |
---|
736 | #define WGM10 0 |
---|
737 | |
---|
738 | /* Timer/Counter 3 Control and Status Register A - TCCR3A */ |
---|
739 | #define COM3A1 7 |
---|
740 | #define COM3A0 6 |
---|
741 | #define COM3B1 5 |
---|
742 | #define COM3B0 4 |
---|
743 | #define COM3C1 3 |
---|
744 | #define COM3C0 2 |
---|
745 | #define WGM31 1 |
---|
746 | #define WGM30 0 |
---|
747 | |
---|
748 | /* Timer/Counter Control and Status Register B (generic) */ |
---|
749 | #define ICNC 7 |
---|
750 | #define ICES 6 |
---|
751 | #define WGMB3 4 |
---|
752 | #define WGMB2 3 |
---|
753 | #define CSB2 2 |
---|
754 | #define CSB1 1 |
---|
755 | #define CSB0 0 |
---|
756 | |
---|
757 | /* Timer/Counter 1 Control and Status Register B - TCCR1B */ |
---|
758 | #define ICNC1 7 |
---|
759 | #define ICES1 6 |
---|
760 | #define WGM13 4 |
---|
761 | #define WGM12 3 |
---|
762 | #define CS12 2 |
---|
763 | #define CS11 1 |
---|
764 | #define CS10 0 |
---|
765 | |
---|
766 | /* Timer/Counter 3 Control and Status Register B - TCCR3B */ |
---|
767 | #define ICNC3 7 |
---|
768 | #define ICES3 6 |
---|
769 | #define WGM33 4 |
---|
770 | #define WGM32 3 |
---|
771 | #define CS32 2 |
---|
772 | #define CS31 1 |
---|
773 | #define CS30 0 |
---|
774 | |
---|
775 | /* Timer/Counter Control Register C (generic) */ |
---|
776 | #define FOCA 7 |
---|
777 | #define FOCB 6 |
---|
778 | #define FOCC 5 |
---|
779 | |
---|
780 | /* Timer/Counter 3 Control Register C - TCCR3C */ |
---|
781 | #define FOC3A 7 |
---|
782 | #define FOC3B 6 |
---|
783 | #define FOC3C 5 |
---|
784 | |
---|
785 | /* Timer/Counter 1 Control Register C - TCCR1C */ |
---|
786 | #define FOC1A 7 |
---|
787 | #define FOC1B 6 |
---|
788 | #define FOC1C 5 |
---|
789 | |
---|
790 | /* On-chip Debug Register - OCDR */ |
---|
791 | #define IDRD 7 |
---|
792 | #define OCDR7 7 |
---|
793 | #define OCDR6 6 |
---|
794 | #define OCDR5 5 |
---|
795 | #define OCDR4 4 |
---|
796 | #define OCDR3 3 |
---|
797 | #define OCDR2 2 |
---|
798 | #define OCDR1 1 |
---|
799 | #define OCDR0 0 |
---|
800 | |
---|
801 | /* Watchdog Timer Control Register - WDTCR */ |
---|
802 | #define WDCE 4 |
---|
803 | #define WDE 3 |
---|
804 | #define WDP2 2 |
---|
805 | #define WDP1 1 |
---|
806 | #define WDP0 0 |
---|
807 | |
---|
808 | /* |
---|
809 | The ADHSM bit has been removed from all documentation, |
---|
810 | as being not needed at all since the comparator has proven |
---|
811 | to be fast enough even without feeding it more power. |
---|
812 | */ |
---|
813 | |
---|
814 | /* Special Function I/O Register - SFIOR */ |
---|
815 | #define TSM 7 |
---|
816 | #define ACME 3 |
---|
817 | #define PUD 2 |
---|
818 | #define PSR0 1 |
---|
819 | #define PSR321 0 |
---|
820 | |
---|
821 | /* SPI Status Register - SPSR */ |
---|
822 | #define SPIF 7 |
---|
823 | #define WCOL 6 |
---|
824 | #define SPI2X 0 |
---|
825 | |
---|
826 | /* SPI Control Register - SPCR */ |
---|
827 | #define SPIE 7 |
---|
828 | #define SPE 6 |
---|
829 | #define DORD 5 |
---|
830 | #define MSTR 4 |
---|
831 | #define CPOL 3 |
---|
832 | #define CPHA 2 |
---|
833 | #define SPR1 1 |
---|
834 | #define SPR0 0 |
---|
835 | |
---|
836 | /* USART Register C (generic) */ |
---|
837 | #define UMSEL 6 |
---|
838 | #define UPM1 5 |
---|
839 | #define UPM0 4 |
---|
840 | #define USBS 3 |
---|
841 | #define UCSZ1 2 |
---|
842 | #define UCSZ0 1 |
---|
843 | #define UCPOL 0 |
---|
844 | |
---|
845 | /* USART1 Register C - UCSR1C */ |
---|
846 | #define UMSEL1 6 |
---|
847 | #define UPM11 5 |
---|
848 | #define UPM10 4 |
---|
849 | #define USBS1 3 |
---|
850 | #define UCSZ11 2 |
---|
851 | #define UCSZ10 1 |
---|
852 | #define UCPOL1 0 |
---|
853 | |
---|
854 | /* USART0 Register C - UCSR0C */ |
---|
855 | #define UMSEL0 6 |
---|
856 | #define UPM01 5 |
---|
857 | #define UPM00 4 |
---|
858 | #define USBS0 3 |
---|
859 | #define UCSZ01 2 |
---|
860 | #define UCSZ00 1 |
---|
861 | #define UCPOL0 0 |
---|
862 | |
---|
863 | /* USART Status Register A (generic) */ |
---|
864 | #define RXC 7 |
---|
865 | #define TXC 6 |
---|
866 | #define UDRE 5 |
---|
867 | #define FE 4 |
---|
868 | #define DOR 3 |
---|
869 | #define UPE 2 |
---|
870 | #define U2X 1 |
---|
871 | #define MPCM 0 |
---|
872 | |
---|
873 | /* USART1 Status Register A - UCSR1A */ |
---|
874 | #define RXC1 7 |
---|
875 | #define TXC1 6 |
---|
876 | #define UDRE1 5 |
---|
877 | #define FE1 4 |
---|
878 | #define DOR1 3 |
---|
879 | #define UPE1 2 |
---|
880 | #define U2X1 1 |
---|
881 | #define MPCM1 0 |
---|
882 | |
---|
883 | /* USART0 Status Register A - UCSR0A */ |
---|
884 | #define RXC0 7 |
---|
885 | #define TXC0 6 |
---|
886 | #define UDRE0 5 |
---|
887 | #define FE0 4 |
---|
888 | #define DOR0 3 |
---|
889 | #define UPE0 2 |
---|
890 | #define U2X0 1 |
---|
891 | #define MPCM0 0 |
---|
892 | |
---|
893 | /* USART Control Register B (generic) */ |
---|
894 | #define RXCIE 7 |
---|
895 | #define TXCIE 6 |
---|
896 | #define UDRIE 5 |
---|
897 | #define RXEN 4 |
---|
898 | #define TXEN 3 |
---|
899 | #define UCSZ 2 |
---|
900 | #define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ |
---|
901 | #define RXB8 1 |
---|
902 | #define TXB8 0 |
---|
903 | |
---|
904 | /* USART1 Control Register B - UCSR1B */ |
---|
905 | #define RXCIE1 7 |
---|
906 | #define TXCIE1 6 |
---|
907 | #define UDRIE1 5 |
---|
908 | #define RXEN1 4 |
---|
909 | #define TXEN1 3 |
---|
910 | #define UCSZ12 2 |
---|
911 | #define RXB81 1 |
---|
912 | #define TXB81 0 |
---|
913 | |
---|
914 | /* USART0 Control Register B - UCSR0B */ |
---|
915 | #define RXCIE0 7 |
---|
916 | #define TXCIE0 6 |
---|
917 | #define UDRIE0 5 |
---|
918 | #define RXEN0 4 |
---|
919 | #define TXEN0 3 |
---|
920 | #define UCSZ02 2 |
---|
921 | #define RXB80 1 |
---|
922 | #define TXB80 0 |
---|
923 | |
---|
924 | /* Analog Comparator Control and Status Register - ACSR */ |
---|
925 | #define ACD 7 |
---|
926 | #define ACBG 6 |
---|
927 | #define ACO 5 |
---|
928 | #define ACI 4 |
---|
929 | #define ACIE 3 |
---|
930 | #define ACIC 2 |
---|
931 | #define ACIS1 1 |
---|
932 | #define ACIS0 0 |
---|
933 | |
---|
934 | /* ADC Control and status register - ADCSRA */ |
---|
935 | #define ADEN 7 |
---|
936 | #define ADSC 6 |
---|
937 | #define ADFR 5 |
---|
938 | #define ADIF 4 |
---|
939 | #define ADIE 3 |
---|
940 | #define ADPS2 2 |
---|
941 | #define ADPS1 1 |
---|
942 | #define ADPS0 0 |
---|
943 | |
---|
944 | /* ADC Multiplexer select - ADMUX */ |
---|
945 | #define REFS1 7 |
---|
946 | #define REFS0 6 |
---|
947 | #define ADLAR 5 |
---|
948 | #define MUX4 4 |
---|
949 | #define MUX3 3 |
---|
950 | #define MUX2 2 |
---|
951 | #define MUX1 1 |
---|
952 | #define MUX0 0 |
---|
953 | |
---|
954 | /* Port A Data Register - PORTA */ |
---|
955 | #define PA7 7 |
---|
956 | #define PA6 6 |
---|
957 | #define PA5 5 |
---|
958 | #define PA4 4 |
---|
959 | #define PA3 3 |
---|
960 | #define PA2 2 |
---|
961 | #define PA1 1 |
---|
962 | #define PA0 0 |
---|
963 | |
---|
964 | /* Port A Data Direction Register - DDRA */ |
---|
965 | #define DDA7 7 |
---|
966 | #define DDA6 6 |
---|
967 | #define DDA5 5 |
---|
968 | #define DDA4 4 |
---|
969 | #define DDA3 3 |
---|
970 | #define DDA2 2 |
---|
971 | #define DDA1 1 |
---|
972 | #define DDA0 0 |
---|
973 | |
---|
974 | /* Port A Input Pins - PINA */ |
---|
975 | #define PINA7 7 |
---|
976 | #define PINA6 6 |
---|
977 | #define PINA5 5 |
---|
978 | #define PINA4 4 |
---|
979 | #define PINA3 3 |
---|
980 | #define PINA2 2 |
---|
981 | #define PINA1 1 |
---|
982 | #define PINA0 0 |
---|
983 | |
---|
984 | /* Port B Data Register - PORTB */ |
---|
985 | #define PB7 7 |
---|
986 | #define PB6 6 |
---|
987 | #define PB5 5 |
---|
988 | #define PB4 4 |
---|
989 | #define PB3 3 |
---|
990 | #define PB2 2 |
---|
991 | #define PB1 1 |
---|
992 | #define PB0 0 |
---|
993 | |
---|
994 | /* Port B Data Direction Register - DDRB */ |
---|
995 | #define DDB7 7 |
---|
996 | #define DDB6 6 |
---|
997 | #define DDB5 5 |
---|
998 | #define DDB4 4 |
---|
999 | #define DDB3 3 |
---|
1000 | #define DDB2 2 |
---|
1001 | #define DDB1 1 |
---|
1002 | #define DDB0 0 |
---|
1003 | |
---|
1004 | /* Port B Input Pins - PINB */ |
---|
1005 | #define PINB7 7 |
---|
1006 | #define PINB6 6 |
---|
1007 | #define PINB5 5 |
---|
1008 | #define PINB4 4 |
---|
1009 | #define PINB3 3 |
---|
1010 | #define PINB2 2 |
---|
1011 | #define PINB1 1 |
---|
1012 | #define PINB0 0 |
---|
1013 | |
---|
1014 | /* Port C Data Register - PORTC */ |
---|
1015 | #define PC7 7 |
---|
1016 | #define PC6 6 |
---|
1017 | #define PC5 5 |
---|
1018 | #define PC4 4 |
---|
1019 | #define PC3 3 |
---|
1020 | #define PC2 2 |
---|
1021 | #define PC1 1 |
---|
1022 | #define PC0 0 |
---|
1023 | |
---|
1024 | /* Port C Data Direction Register - DDRC */ |
---|
1025 | #define DDC7 7 |
---|
1026 | #define DDC6 6 |
---|
1027 | #define DDC5 5 |
---|
1028 | #define DDC4 4 |
---|
1029 | #define DDC3 3 |
---|
1030 | #define DDC2 2 |
---|
1031 | #define DDC1 1 |
---|
1032 | #define DDC0 0 |
---|
1033 | |
---|
1034 | /* Port C Input Pins - PINC */ |
---|
1035 | #define PINC7 7 |
---|
1036 | #define PINC6 6 |
---|
1037 | #define PINC5 5 |
---|
1038 | #define PINC4 4 |
---|
1039 | #define PINC3 3 |
---|
1040 | #define PINC2 2 |
---|
1041 | #define PINC1 1 |
---|
1042 | #define PINC0 0 |
---|
1043 | |
---|
1044 | /* Port D Data Register - PORTD */ |
---|
1045 | #define PD7 7 |
---|
1046 | #define PD6 6 |
---|
1047 | #define PD5 5 |
---|
1048 | #define PD4 4 |
---|
1049 | #define PD3 3 |
---|
1050 | #define PD2 2 |
---|
1051 | #define PD1 1 |
---|
1052 | #define PD0 0 |
---|
1053 | |
---|
1054 | /* Port D Data Direction Register - DDRD */ |
---|
1055 | #define DDD7 7 |
---|
1056 | #define DDD6 6 |
---|
1057 | #define DDD5 5 |
---|
1058 | #define DDD4 4 |
---|
1059 | #define DDD3 3 |
---|
1060 | #define DDD2 2 |
---|
1061 | #define DDD1 1 |
---|
1062 | #define DDD0 0 |
---|
1063 | |
---|
1064 | /* Port D Input Pins - PIND */ |
---|
1065 | #define PIND7 7 |
---|
1066 | #define PIND6 6 |
---|
1067 | #define PIND5 5 |
---|
1068 | #define PIND4 4 |
---|
1069 | #define PIND3 3 |
---|
1070 | #define PIND2 2 |
---|
1071 | #define PIND1 1 |
---|
1072 | #define PIND0 0 |
---|
1073 | |
---|
1074 | /* Port E Data Register - PORTE */ |
---|
1075 | #define PE7 7 |
---|
1076 | #define PE6 6 |
---|
1077 | #define PE5 5 |
---|
1078 | #define PE4 4 |
---|
1079 | #define PE3 3 |
---|
1080 | #define PE2 2 |
---|
1081 | #define PE1 1 |
---|
1082 | #define PE0 0 |
---|
1083 | |
---|
1084 | /* Port E Data Direction Register - DDRE */ |
---|
1085 | #define DDE7 7 |
---|
1086 | #define DDE6 6 |
---|
1087 | #define DDE5 5 |
---|
1088 | #define DDE4 4 |
---|
1089 | #define DDE3 3 |
---|
1090 | #define DDE2 2 |
---|
1091 | #define DDE1 1 |
---|
1092 | #define DDE0 0 |
---|
1093 | |
---|
1094 | /* Port E Input Pins - PINE */ |
---|
1095 | #define PINE7 7 |
---|
1096 | #define PINE6 6 |
---|
1097 | #define PINE5 5 |
---|
1098 | #define PINE4 4 |
---|
1099 | #define PINE3 3 |
---|
1100 | #define PINE2 2 |
---|
1101 | #define PINE1 1 |
---|
1102 | #define PINE0 0 |
---|
1103 | |
---|
1104 | /* Port F Data Register - PORTF */ |
---|
1105 | #define PF7 7 |
---|
1106 | #define PF6 6 |
---|
1107 | #define PF5 5 |
---|
1108 | #define PF4 4 |
---|
1109 | #define PF3 3 |
---|
1110 | #define PF2 2 |
---|
1111 | #define PF1 1 |
---|
1112 | #define PF0 0 |
---|
1113 | |
---|
1114 | /* Port F Data Direction Register - DDRF */ |
---|
1115 | #define DDF7 7 |
---|
1116 | #define DDF6 6 |
---|
1117 | #define DDF5 5 |
---|
1118 | #define DDF4 4 |
---|
1119 | #define DDF3 3 |
---|
1120 | #define DDF2 2 |
---|
1121 | #define DDF1 1 |
---|
1122 | #define DDF0 0 |
---|
1123 | |
---|
1124 | /* Port F Input Pins - PINF */ |
---|
1125 | #define PINF7 7 |
---|
1126 | #define PINF6 6 |
---|
1127 | #define PINF5 5 |
---|
1128 | #define PINF4 4 |
---|
1129 | #define PINF3 3 |
---|
1130 | #define PINF2 2 |
---|
1131 | #define PINF1 1 |
---|
1132 | #define PINF0 0 |
---|
1133 | |
---|
1134 | /* Port G Data Register - PORTG */ |
---|
1135 | #define PG4 4 |
---|
1136 | #define PG3 3 |
---|
1137 | #define PG2 2 |
---|
1138 | #define PG1 1 |
---|
1139 | #define PG0 0 |
---|
1140 | |
---|
1141 | /* Port G Data Direction Register - DDRG */ |
---|
1142 | #define DDG4 4 |
---|
1143 | #define DDG3 3 |
---|
1144 | #define DDG2 2 |
---|
1145 | #define DDG1 1 |
---|
1146 | #define DDG0 0 |
---|
1147 | |
---|
1148 | /* Port G Input Pins - PING */ |
---|
1149 | #define PING4 4 |
---|
1150 | #define PING3 3 |
---|
1151 | #define PING2 2 |
---|
1152 | #define PING1 1 |
---|
1153 | #define PING0 0 |
---|
1154 | |
---|
1155 | /* EEPROM Control Register */ |
---|
1156 | #define EERIE 3 |
---|
1157 | #define EEMWE 2 |
---|
1158 | #define EEWE 1 |
---|
1159 | #define EERE 0 |
---|
1160 | |
---|
1161 | /* Constants */ |
---|
1162 | #define SPM_PAGESIZE 256 |
---|
1163 | #define RAMEND 0x10FF /* Last On-Chip SRAM Location */ |
---|
1164 | #define XRAMEND 0xFFFF |
---|
1165 | #define E2END 0x0FFF |
---|
1166 | #define E2PAGESIZE 8 |
---|
1167 | #define FLASHEND 0x1FFFF |
---|
1168 | |
---|
1169 | |
---|
1170 | /* Fuses */ |
---|
1171 | |
---|
1172 | #define FUSE_MEMORY_SIZE 3 |
---|
1173 | |
---|
1174 | /* Low Fuse Byte */ |
---|
1175 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
---|
1176 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
---|
1177 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
---|
1178 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
---|
1179 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
---|
1180 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
---|
1181 | #define FUSE_BODEN (unsigned char)~_BV(6) |
---|
1182 | #define FUSE_BODLEVEL (unsigned char)~_BV(7) |
---|
1183 | #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) |
---|
1184 | |
---|
1185 | /* High Fuse Byte */ |
---|
1186 | #define FUSE_BOOTRST (unsigned char)~_BV(0) |
---|
1187 | #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
---|
1188 | #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
---|
1189 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
---|
1190 | #define FUSE_CKOPT (unsigned char)~_BV(4) |
---|
1191 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
---|
1192 | #define FUSE_JTAGEN (unsigned char)~_BV(6) |
---|
1193 | #define FUSE_OCDEN (unsigned char)~_BV(7) |
---|
1194 | #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
---|
1195 | |
---|
1196 | /* Extended Fuse Byte */ |
---|
1197 | #define FUSE_WDTON (unsigned char)~_BV(0) |
---|
1198 | #define FUSE_M103C (unsigned char)~_BV(1) |
---|
1199 | #define EFUSE_DEFAULT (FUSE_M103C) |
---|
1200 | |
---|
1201 | |
---|
1202 | /* Lock Bits */ |
---|
1203 | #define __LOCK_BITS_EXIST |
---|
1204 | #define __BOOT_LOCK_BITS_0_EXIST |
---|
1205 | #define __BOOT_LOCK_BITS_1_EXIST |
---|
1206 | |
---|
1207 | |
---|
1208 | /* Signature */ |
---|
1209 | #define SIGNATURE_0 0x1E |
---|
1210 | #define SIGNATURE_1 0x97 |
---|
1211 | #define SIGNATURE_2 0x02 |
---|
1212 | |
---|
1213 | |
---|
1214 | /**@}*/ |
---|
1215 | #endif /* _AVR_IOM128_H_ */ |
---|