| 1 | /* Copyright (c) 2002, Marek Michalkiewicz |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | |
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| 32 | /* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */ |
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| 33 | |
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| 34 | #ifndef _AVR_IOAT94K_H_ |
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| 35 | #define _AVR_IOAT94K_H_ 1 |
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| 36 | |
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| 37 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 38 | |
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| 39 | #ifndef _AVR_IO_H_ |
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| 40 | # error "Include <avr/io.h> instead of this file." |
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| 41 | #endif |
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| 42 | |
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| 43 | #ifndef _AVR_IOXXX_H_ |
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| 44 | # define _AVR_IOXXX_H_ "ioat94k.h" |
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| 45 | #else |
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| 46 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 47 | #endif |
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| 48 | |
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| 49 | /* I/O registers */ |
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| 50 | |
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| 51 | /* UART1 Baud Rate Register */ |
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| 52 | #define UBRR1 _SFR_IO8(0x00) |
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| 53 | |
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| 54 | /* UART1 Control and Status Registers */ |
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| 55 | #define UCSR1B _SFR_IO8(0x01) |
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| 56 | #define UCSR1A _SFR_IO8(0x02) |
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| 57 | |
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| 58 | /* UART1 I/O Data Register */ |
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| 59 | #define UDR1 _SFR_IO8(0x03) |
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| 60 | |
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| 61 | /* 0x04 reserved */ |
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| 62 | |
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| 63 | /* Input Pins, Port E */ |
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| 64 | #define PINE _SFR_IO8(0x05) |
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| 65 | |
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| 66 | /* Data Direction Register, Port E */ |
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| 67 | #define DDRE _SFR_IO8(0x06) |
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| 68 | |
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| 69 | /* Data Register, Port E */ |
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| 70 | #define PORTE _SFR_IO8(0x07) |
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| 71 | |
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| 72 | /* On Chip Debug Register (reserved) */ |
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| 73 | #define OCDR _SFR_IO8(0x08) |
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| 74 | |
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| 75 | /* UART0 Baud Rate Register */ |
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| 76 | #define UBRR0 _SFR_IO8(0x09) |
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| 77 | |
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| 78 | /* UART0 Control and Status Registers */ |
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| 79 | #define UCSR0B _SFR_IO8(0x0A) |
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| 80 | #define UCSR0A _SFR_IO8(0x0B) |
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| 81 | |
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| 82 | /* UART0 I/O Data Register */ |
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| 83 | #define UDR0 _SFR_IO8(0x0C) |
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| 84 | |
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| 85 | /* 0x0D..0x0F reserved */ |
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| 86 | |
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| 87 | /* Input Pins, Port D */ |
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| 88 | #define PIND _SFR_IO8(0x10) |
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| 89 | |
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| 90 | /* Data Direction Register, Port D */ |
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| 91 | #define DDRD _SFR_IO8(0x11) |
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| 92 | |
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| 93 | /* Data Register, Port D */ |
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| 94 | #define PORTD _SFR_IO8(0x12) |
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| 95 | |
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| 96 | /* FPGA I/O Select Control Register */ |
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| 97 | #define FISCR _SFR_IO8(0x13) |
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| 98 | |
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| 99 | /* FPGA I/O Select Registers A, B, C, D */ |
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| 100 | #define FISUA _SFR_IO8(0x14) |
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| 101 | #define FISUB _SFR_IO8(0x15) |
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| 102 | #define FISUC _SFR_IO8(0x16) |
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| 103 | #define FISUD _SFR_IO8(0x17) |
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| 104 | |
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| 105 | /* FPGA Cache Logic(R) registers (top secret, under NDA) */ |
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| 106 | #define FPGAX _SFR_IO8(0x18) |
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| 107 | #define FPGAY _SFR_IO8(0x19) |
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| 108 | #define FPGAZ _SFR_IO8(0x1A) |
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| 109 | #define FPGAD _SFR_IO8(0x1B) |
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| 110 | |
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| 111 | /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ |
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| 112 | |
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| 113 | /* 2-wire Serial Bit Rate Register */ |
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| 114 | #define TWBR _SFR_IO8(0x1C) |
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| 115 | |
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| 116 | /* 2-wire Serial Status Register */ |
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| 117 | #define TWSR _SFR_IO8(0x1D) |
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| 118 | |
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| 119 | /* 2-wire Serial (Slave) Address Register */ |
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| 120 | #define TWAR _SFR_IO8(0x1E) |
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| 121 | |
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| 122 | /* 2-wire Serial Data Register */ |
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| 123 | #define TWDR _SFR_IO8(0x1F) |
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| 124 | |
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| 125 | /* UART Baud Register High */ |
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| 126 | #define UBRRH _SFR_IO8(0x20) |
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| 127 | #define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */ |
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| 128 | |
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| 129 | /* Watchdog Timer Control Register */ |
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| 130 | #define WDTCR _SFR_IO8(0x21) |
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| 131 | |
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| 132 | /* Timer/Counter2 Output Compare Register */ |
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| 133 | #define OCR2 _SFR_IO8(0x22) |
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| 134 | |
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| 135 | /* Timer/Counter2 (8-bit) */ |
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| 136 | #define TCNT2 _SFR_IO8(0x23) |
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| 137 | |
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| 138 | /* Timer/Counter1 Input Capture Register */ |
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| 139 | #define ICR1 _SFR_IO16(0x24) |
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| 140 | #define ICR1L _SFR_IO8(0x24) |
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| 141 | #define ICR1H _SFR_IO8(0x25) |
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| 142 | |
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| 143 | /* Asynchronous mode StatuS Register */ |
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| 144 | #define ASSR _SFR_IO8(0x26) |
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| 145 | |
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| 146 | /* Timer/Counter2 Control Register */ |
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| 147 | #define TCCR2 _SFR_IO8(0x27) |
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| 148 | |
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| 149 | /* Timer/Counter1 Output Compare RegisterB */ |
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| 150 | #define OCR1B _SFR_IO16(0x28) |
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| 151 | #define OCR1BL _SFR_IO8(0x28) |
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| 152 | #define OCR1BH _SFR_IO8(0x29) |
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| 153 | |
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| 154 | /* Timer/Counter1 Output Compare RegisterA */ |
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| 155 | #define OCR1A _SFR_IO16(0x2A) |
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| 156 | #define OCR1AL _SFR_IO8(0x2A) |
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| 157 | #define OCR1AH _SFR_IO8(0x2B) |
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| 158 | |
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| 159 | /* Timer/Counter1 */ |
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| 160 | #define TCNT1 _SFR_IO16(0x2C) |
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| 161 | #define TCNT1L _SFR_IO8(0x2C) |
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| 162 | #define TCNT1H _SFR_IO8(0x2D) |
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| 163 | |
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| 164 | /* Timer/Counter1 Control Register B */ |
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| 165 | #define TCCR1B _SFR_IO8(0x2E) |
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| 166 | |
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| 167 | /* Timer/Counter1 Control Register A */ |
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| 168 | #define TCCR1A _SFR_IO8(0x2F) |
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| 169 | |
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| 170 | /* Special Function IO Register */ |
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| 171 | #define SFIOR _SFR_IO8(0x30) |
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| 172 | |
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| 173 | /* Timer/Counter0 Output Compare Register */ |
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| 174 | #define OCR0 _SFR_IO8(0x31) |
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| 175 | |
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| 176 | /* Timer/Counter0 (8-bit) */ |
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| 177 | #define TCNT0 _SFR_IO8(0x32) |
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| 178 | |
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| 179 | /* Timer/Counter0 Control Register */ |
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| 180 | #define TCCR0 _SFR_IO8(0x33) |
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| 181 | |
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| 182 | /* 0x34 reserved */ |
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| 183 | |
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| 184 | /* MCU Control/Status Register */ |
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| 185 | #define MCUR _SFR_IO8(0x35) |
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| 186 | |
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| 187 | /* 2-wire Serial Control Register */ |
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| 188 | #define TWCR _SFR_IO8(0x36) |
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| 189 | |
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| 190 | /* 0x37 reserved */ |
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| 191 | |
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| 192 | /* Timer/Counter Interrupt Flag Register */ |
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| 193 | #define TIFR _SFR_IO8(0x38) |
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| 194 | |
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| 195 | /* Timer/Counter Interrupt MaSK Register */ |
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| 196 | #define TIMSK _SFR_IO8(0x39) |
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| 197 | |
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| 198 | /* Software Control Register */ |
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| 199 | #define SFTCR _SFR_IO8(0x3A) |
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| 200 | |
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| 201 | /* External Interrupt Mask/Flag Register */ |
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| 202 | #define EIMF _SFR_IO8(0x3B) |
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| 203 | |
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| 204 | /* 0x3C reserved */ |
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| 205 | |
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| 206 | /* 0x3D..0x3E SP */ |
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| 207 | |
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| 208 | /* 0x3F SREG */ |
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| 209 | |
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| 210 | /* Interrupt vectors */ |
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| 211 | |
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| 212 | #define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ |
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| 213 | #define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ |
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| 214 | #define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ |
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| 215 | #define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ |
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| 216 | #define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ |
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| 217 | #define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ |
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| 218 | #define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ |
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| 219 | #define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ |
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| 220 | #define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ |
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| 221 | #define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ |
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| 222 | #define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ |
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| 223 | #define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ |
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| 224 | #define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ |
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| 225 | #define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ |
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| 226 | #define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ |
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| 227 | #define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ |
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| 228 | #define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ |
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| 229 | #define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ |
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| 230 | #define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ |
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| 231 | #define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ |
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| 232 | #define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ |
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| 233 | #define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ |
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| 234 | #define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ |
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| 235 | #define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ |
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| 236 | #define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ |
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| 237 | #define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ |
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| 238 | #define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ |
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| 239 | #define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ |
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| 240 | #define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ |
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| 241 | #define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ |
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| 242 | #define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */ |
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| 243 | #define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */ |
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| 244 | #define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */ |
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| 245 | #define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */ |
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| 246 | #define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */ |
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| 247 | |
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| 248 | #define _VECTORS_SIZE 144 |
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| 249 | |
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| 250 | /* Bit numbers (SFRs alphabetically sorted) */ |
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| 251 | |
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| 252 | /* ASSR */ |
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| 253 | #define AS2 3 |
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| 254 | #define TCN2UB 2 |
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| 255 | #define OCR2UB 1 |
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| 256 | #define TCR2UB 0 |
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| 257 | |
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| 258 | /* DDRD */ |
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| 259 | #define DDD7 7 |
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| 260 | #define DDD6 6 |
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| 261 | #define DDD5 5 |
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| 262 | #define DDD4 4 |
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| 263 | #define DDD3 3 |
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| 264 | #define DDD2 2 |
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| 265 | #define DDD1 1 |
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| 266 | #define DDD0 0 |
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| 267 | |
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| 268 | /* DDRE */ |
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| 269 | #define DDE7 7 |
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| 270 | #define DDE6 6 |
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| 271 | #define DDE5 5 |
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| 272 | #define DDE4 4 |
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| 273 | #define DDE3 3 |
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| 274 | #define DDE2 2 |
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| 275 | #define DDE1 1 |
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| 276 | #define DDE0 0 |
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| 277 | |
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| 278 | /* EIMF */ |
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| 279 | #define INTF3 7 |
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| 280 | #define INTF2 6 |
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| 281 | #define INTF1 5 |
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| 282 | #define INTF0 4 |
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| 283 | #define INT3 3 |
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| 284 | #define INT2 2 |
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| 285 | #define INT1 1 |
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| 286 | #define INT0 0 |
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| 287 | |
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| 288 | /* FISCR */ |
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| 289 | #define FIADR 7 |
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| 290 | #define XFIS1 1 |
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| 291 | #define XFIS0 0 |
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| 292 | |
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| 293 | /* FISUA */ |
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| 294 | #define FIF3 7 |
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| 295 | #define FIF2 6 |
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| 296 | #define FIF1 5 |
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| 297 | #define FIF0 4 |
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| 298 | #define FINT3 3 |
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| 299 | #define FINT2 2 |
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| 300 | #define FINT1 1 |
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| 301 | #define FINT0 0 |
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| 302 | |
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| 303 | /* FISUB */ |
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| 304 | #define FIF7 7 |
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| 305 | #define FIF6 6 |
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| 306 | #define FIF5 5 |
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| 307 | #define FIF4 4 |
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| 308 | #define FINT7 3 |
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| 309 | #define FINT6 2 |
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| 310 | #define FINT5 1 |
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| 311 | #define FINT4 0 |
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| 312 | |
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| 313 | /* FISUC */ |
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| 314 | #define FIF11 7 |
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| 315 | #define FIF10 6 |
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| 316 | #define FIF9 5 |
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| 317 | #define FIF8 4 |
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| 318 | #define FINT11 3 |
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| 319 | #define FINT10 2 |
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| 320 | #define FINT9 1 |
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| 321 | #define FINT8 0 |
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| 322 | |
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| 323 | /* FISUD */ |
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| 324 | #define FIF15 7 |
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| 325 | #define FIF14 6 |
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| 326 | #define FIF13 5 |
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| 327 | #define FIF12 4 |
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| 328 | #define FINT15 3 |
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| 329 | #define FINT14 2 |
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| 330 | #define FINT13 1 |
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| 331 | #define FINT12 0 |
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| 332 | |
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| 333 | /* MCUR */ |
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| 334 | #define JTRF 7 |
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| 335 | #define JTD 6 |
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| 336 | #define SE 5 |
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| 337 | #define SM1 4 |
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| 338 | #define SM0 3 |
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| 339 | #define PORF 2 |
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| 340 | #define WDRF 1 |
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| 341 | #define EXTRF 0 |
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| 342 | |
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| 343 | /* OCDR (reserved) */ |
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| 344 | #define IDRD 7 |
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| 345 | |
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| 346 | /* PIND */ |
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| 347 | #define PIND7 7 |
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| 348 | #define PIND6 6 |
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| 349 | #define PIND5 5 |
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| 350 | #define PIND4 4 |
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| 351 | #define PIND3 3 |
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| 352 | #define PIND2 2 |
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| 353 | #define PIND1 1 |
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| 354 | #define PIND0 0 |
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| 355 | |
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| 356 | /* PINE */ |
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| 357 | #define PINE7 7 |
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| 358 | #define PINE6 6 |
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| 359 | #define PINE5 5 |
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| 360 | #define PINE4 4 |
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| 361 | #define PINE3 3 |
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| 362 | #define PINE2 2 |
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| 363 | #define PINE1 1 |
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| 364 | #define PINE0 0 |
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| 365 | |
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| 366 | /* PORTD */ |
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| 367 | #define PD7 7 |
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| 368 | #define PD6 6 |
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| 369 | #define PD5 5 |
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| 370 | #define PD4 4 |
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| 371 | #define PD3 3 |
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| 372 | #define PD2 2 |
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| 373 | #define PD1 1 |
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| 374 | #define PD0 0 |
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| 375 | |
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| 376 | /* PORTE */ |
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| 377 | /* |
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| 378 | PE7 = IC1 / INT3 (alternate) |
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| 379 | PE6 = OC1A / INT2 (alternate) |
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| 380 | PE5 = OC1B / INT1 (alternate) |
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| 381 | PE4 = ET11 / INT0 (alternate) |
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| 382 | PE3 = OC2 / RX1 (alternate) |
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| 383 | PE2 = / TX1 (alternate) |
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| 384 | PE1 = OC0 / RX0 (alternate) |
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| 385 | PE0 = ET0 / TX0 (alternate) |
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| 386 | */ |
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| 387 | #define PE7 7 |
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| 388 | #define PE6 6 |
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| 389 | #define PE5 5 |
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| 390 | #define PE4 4 |
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| 391 | #define PE3 3 |
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| 392 | #define PE2 2 |
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| 393 | #define PE1 1 |
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| 394 | #define PE0 0 |
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| 395 | |
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| 396 | /* SFIOR */ |
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| 397 | #define PSR2 1 |
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| 398 | #define PSR10 0 |
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| 399 | |
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| 400 | /* SFTCR */ |
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| 401 | #define FMXOR 3 |
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| 402 | #define WDTS 2 |
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| 403 | #define DBG 1 |
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| 404 | #define SRST 0 |
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| 405 | |
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| 406 | /* TCCR0 */ |
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| 407 | #define FOC0 7 |
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| 408 | #define PWM0 6 |
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| 409 | #define COM01 5 |
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| 410 | #define COM00 4 |
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| 411 | #define CTC0 3 |
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| 412 | #define CS02 2 |
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| 413 | #define CS01 1 |
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| 414 | #define CS00 0 |
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| 415 | |
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| 416 | /* TCCR1A */ |
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| 417 | #define COM1A1 7 |
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| 418 | #define COM1A0 6 |
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| 419 | #define COM1B1 5 |
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| 420 | #define COM1B0 4 |
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| 421 | #define FOC1A 3 |
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| 422 | #define FOC1B 2 |
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| 423 | #define PWM11 1 |
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| 424 | #define PWM10 0 |
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| 425 | |
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| 426 | /* TCCR1B */ |
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| 427 | #define ICNC1 7 |
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| 428 | #define ICES1 6 |
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| 429 | #define ICPE 5 |
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| 430 | #define CTC1 3 |
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| 431 | #define CS12 2 |
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| 432 | #define CS11 1 |
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| 433 | #define CS10 0 |
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| 434 | |
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| 435 | /* TCCR2 */ |
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| 436 | #define FOC2 7 |
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| 437 | #define PWM2 6 |
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| 438 | #define COM21 5 |
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| 439 | #define COM20 4 |
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| 440 | #define CTC2 3 |
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| 441 | #define CS22 2 |
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| 442 | #define CS21 1 |
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| 443 | #define CS20 0 |
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| 444 | |
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| 445 | /* TIFR */ |
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| 446 | #define TOV1 7 |
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| 447 | #define OCF1A 6 |
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| 448 | #define OCF1B 5 |
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| 449 | #define TOV2 4 |
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| 450 | #define ICF1 3 |
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| 451 | #define OCF2 2 |
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| 452 | #define TOV0 1 |
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| 453 | #define OCF0 0 |
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| 454 | |
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| 455 | /* TIMSK */ |
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| 456 | #define TOIE1 7 |
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| 457 | #define OCIE1A 6 |
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| 458 | #define OCIE1B 5 |
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| 459 | #define TOIE2 4 |
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| 460 | #define TICIE1 3 |
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| 461 | #define OCIE2 2 |
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| 462 | #define TOIE0 1 |
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| 463 | #define OCIE0 0 |
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| 464 | |
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| 465 | /* TWAR */ |
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| 466 | /* #define TWA 1 */ /* TWA is bits 7:1 */ |
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| 467 | #define TWGCE 0 |
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| 468 | |
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| 469 | /* TWCR */ |
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| 470 | #define TWINT 7 |
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| 471 | #define TWEA 6 |
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| 472 | #define TWSTA 5 |
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| 473 | #define TWSTO 4 |
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| 474 | #define TWWC 3 |
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| 475 | #define TWEN 2 |
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| 476 | #define TWIE 0 |
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| 477 | |
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| 478 | /* TWSR */ |
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| 479 | #define TWS7 7 |
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| 480 | #define TWS6 6 |
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| 481 | #define TWS5 5 |
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| 482 | #define TWS4 4 |
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| 483 | #define TWS3 3 |
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| 484 | |
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| 485 | /* UBRRHI |
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| 486 | Bits 11..8 of UART1 are bits 7..4 of UBRRHI. |
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| 487 | Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */ |
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| 488 | /* #define UBRRHI1 4 */ |
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| 489 | /* #define UBRRHI0 0 */ |
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| 490 | |
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| 491 | /* UCSR0A */ |
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| 492 | #define RXC0 7 |
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| 493 | #define TXC0 6 |
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| 494 | #define UDRE0 5 |
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| 495 | #define FE0 4 |
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| 496 | #define OR0 3 |
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| 497 | #define U2X0 1 |
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| 498 | #define MPCM0 0 |
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| 499 | |
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| 500 | /* UCSR0B */ |
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| 501 | #define RXCIE0 7 |
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| 502 | #define TXCIE0 6 |
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| 503 | #define UDRIE0 5 |
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| 504 | #define RXEN0 4 |
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| 505 | #define TXEN0 3 |
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| 506 | #define CHR90 2 |
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| 507 | #define RXB80 1 |
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| 508 | #define TXB80 0 |
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| 509 | |
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| 510 | /* UCSR1A */ |
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| 511 | #define RXC1 7 |
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| 512 | #define TXC1 6 |
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| 513 | #define UDRE1 5 |
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| 514 | #define FE1 4 |
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| 515 | #define OR1 3 |
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| 516 | #define U2X1 1 |
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| 517 | #define MPCM1 0 |
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| 518 | |
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| 519 | /* UCSR1B */ |
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| 520 | #define RXCIE1 7 |
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| 521 | #define TXCIE1 6 |
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| 522 | #define UDRIE1 5 |
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| 523 | #define RXEN1 4 |
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| 524 | #define TXEN1 3 |
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| 525 | #define CHR91 2 |
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| 526 | #define RXB81 1 |
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| 527 | #define TXB81 0 |
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| 528 | |
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| 529 | /* WDTCR */ |
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| 530 | #define WDTOE 4 |
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| 531 | #define WDE 3 |
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| 532 | #define WDP2 2 |
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| 533 | #define WDP1 1 |
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| 534 | #define WDP0 0 |
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| 535 | |
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| 536 | /* |
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| 537 | Last memory addresses - depending on configuration, it is possible |
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| 538 | to have 20K-32K of program memory and 4K-16K of data memory |
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| 539 | (all in the same 36K total of SRAM, loaded from external EEPROM). |
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| 540 | */ |
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| 541 | |
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| 542 | #ifndef RAMEND |
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| 543 | #define RAMEND 0x0FFF |
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| 544 | #endif |
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| 545 | |
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| 546 | #ifndef XRAMEND |
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| 547 | #define XRAMEND RAMEND |
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| 548 | #endif |
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| 549 | |
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| 550 | #define E2END 0 |
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| 551 | |
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| 552 | #ifndef FLASHEND |
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| 553 | #define FLASHEND 0x7FFF |
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| 554 | #endif |
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| 555 | |
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| 556 | #endif /* _AVR_IOAT94K_H_ */ |
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