1 | /* Copyright (c) 2008 Atmel Corporation |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | |
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32 | /* avr/ioa6289.h - definitions for ATA6289 */ |
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33 | |
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34 | /* This file should only be included from <avr/io.h>, never directly. */ |
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35 | |
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36 | #ifndef _AVR_IO_H_ |
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37 | # error "Include <avr/io.h> instead of this file." |
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38 | #endif |
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39 | |
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40 | #ifndef _AVR_IOXXX_H_ |
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41 | # define _AVR_IOXXX_H_ "ioa6289.h" |
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42 | #else |
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43 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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44 | #endif |
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45 | |
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46 | |
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47 | #ifndef _AVR_ATA6289_H_ |
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48 | #define _AVR_ATA6289_H_ 1 |
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49 | |
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50 | |
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51 | /* Registers and associated bit numbers. */ |
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52 | |
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53 | #define PINB _SFR_IO8(0x03) |
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54 | #define PINB0 0 |
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55 | #define PINB1 1 |
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56 | #define PINB2 2 |
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57 | #define PINB3 3 |
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58 | #define PINB4 4 |
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59 | #define PINB5 5 |
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60 | #define PINB6 6 |
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61 | #define PINB7 7 |
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62 | |
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63 | #define DDRB _SFR_IO8(0x04) |
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64 | #define DDB0 0 |
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65 | #define DDB1 1 |
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66 | #define DDB2 2 |
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67 | #define DDB3 3 |
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68 | #define DDB4 4 |
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69 | #define DDB5 5 |
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70 | #define DDB6 6 |
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71 | #define DDB7 7 |
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72 | |
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73 | #define PORTB _SFR_IO8(0x05) |
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74 | #define PORTB0 0 |
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75 | #define PORTB1 1 |
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76 | #define PORTB2 2 |
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77 | #define PORTB3 3 |
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78 | #define PORTB4 4 |
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79 | #define PORTB5 5 |
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80 | #define PORTB6 6 |
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81 | #define PORTB7 7 |
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82 | |
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83 | #define PINC _SFR_IO8(0x06) |
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84 | #define PINC0 0 |
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85 | #define PINC1 1 |
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86 | |
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87 | #define DDRC _SFR_IO8(0x07) |
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88 | |
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89 | #define PORTC _SFR_IO8(0x08) |
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90 | #define PORTC0 0 |
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91 | #define PORTC1 1 |
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92 | |
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93 | #define PIND _SFR_IO8(0x09) |
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94 | #define PIND0 0 |
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95 | #define PIND1 1 |
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96 | #define PIND2 2 |
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97 | #define PIND3 3 |
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98 | #define PIND4 4 |
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99 | #define PIND5 5 |
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100 | #define PIND6 6 |
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101 | #define PIND7 7 |
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102 | |
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103 | #define DDRD _SFR_IO8(0x0A) |
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104 | #define DDD0 0 |
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105 | #define DDD1 1 |
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106 | #define DDD2 2 |
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107 | #define DDD3 3 |
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108 | #define DDD4 4 |
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109 | #define DDD5 5 |
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110 | #define DDD6 6 |
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111 | #define DDD7 7 |
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112 | |
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113 | #define PORTD _SFR_IO8(0x0B) |
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114 | #define PORTD0 0 |
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115 | #define PORTD1 1 |
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116 | #define PORTD2 2 |
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117 | #define PORTD3 3 |
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118 | #define PORTD4 4 |
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119 | #define PORTD5 5 |
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120 | #define PORTD6 6 |
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121 | #define PORTD7 7 |
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122 | |
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123 | #define CMCR _SFR_IO8(0x0F) |
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124 | #define CMM0 0 |
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125 | #define CMM1 1 |
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126 | #define SRCD 2 |
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127 | #define CMONEN 3 |
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128 | #define CCS 4 |
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129 | #define ECINS 5 |
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130 | #define CMCCE 7 |
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131 | |
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132 | #define CMSR _SFR_IO8(0x10) |
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133 | #define ECF 0 |
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134 | |
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135 | #define T2CRA _SFR_IO8(0x11) |
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136 | #define T2OTM 0 |
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137 | #define T2CTM 1 |
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138 | #define T2CR 2 |
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139 | #define T2CRM 3 |
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140 | #define T2CPRM 4 |
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141 | #define T2ICS 5 |
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142 | #define T2TS 6 |
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143 | #define T2E 7 |
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144 | |
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145 | #define T2CRB _SFR_IO8(0x12) |
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146 | #define T2SCE 0 |
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147 | |
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148 | #define T3CRA _SFR_IO8(0x14) |
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149 | #define T3AC 0 |
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150 | #define T3SCE 1 |
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151 | #define T3CR 2 |
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152 | #define T3TS 6 |
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153 | #define T3E 7 |
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154 | |
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155 | #define VMCSR _SFR_IO8(0x16) |
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156 | #define VMEN 0 |
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157 | #define VMLS0 1 |
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158 | #define VMLS1 2 |
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159 | #define VMLS2 3 |
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160 | #define VMIM 4 |
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161 | #define VMF 5 |
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162 | #define BODPD 6 |
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163 | #define BODLS 7 |
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164 | |
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165 | #define PCIFR _SFR_IO8(0x17) |
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166 | #define PCIF0 0 |
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167 | #define PCIF1 1 |
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168 | #define PCIF2 2 |
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169 | |
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170 | #define LFFR _SFR_IO8(0x18) |
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171 | #define LFWPF 0 |
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172 | #define LFBF 1 |
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173 | #define LFEDF 2 |
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174 | #define LFRF 3 |
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175 | |
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176 | #define SSFR _SFR_IO8(0x19) |
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177 | #define MSENF 0 |
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178 | #define MSENO 1 |
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179 | |
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180 | #define T10IFR _SFR_IO8(0x1A) |
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181 | #define T0F 0 |
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182 | #define T1F 1 |
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183 | |
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184 | #define T2IFR _SFR_IO8(0x1B) |
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185 | #define T2OFF 0 |
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186 | #define T2COF 1 |
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187 | #define T2ICF 2 |
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188 | #define T2RXF 3 |
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189 | #define T2TXF 4 |
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190 | #define T2TCF 5 |
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191 | |
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192 | #define T3IFR _SFR_IO8(0x1C) |
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193 | #define T3OFF 0 |
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194 | #define T3COAF 1 |
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195 | #define T3COBF 2 |
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196 | #define T3ICF 3 |
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197 | |
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198 | #define EIFR _SFR_IO8(0x1D) |
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199 | #define INTF0 0 |
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200 | #define INTF1 1 |
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201 | |
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202 | #define GPIOR0 _SFR_IO8(0x1E) |
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203 | #define GPIOR00 0 |
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204 | #define GPIOR01 1 |
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205 | #define GPIOR02 2 |
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206 | #define GPIOR03 3 |
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207 | #define GPIOR04 4 |
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208 | #define GPIOR05 5 |
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209 | #define GPIOR06 6 |
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210 | #define GPIOR07 7 |
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211 | |
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212 | #define EECR _SFR_IO8(0x1F) |
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213 | #define EERE 0 |
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214 | #define EEWE 1 |
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215 | #define EEMWE 2 |
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216 | #define EERIE 3 |
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217 | #define EEPM0 4 |
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218 | #define EEPM1 5 |
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219 | |
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220 | #define EEDR _SFR_IO8(0x20) |
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221 | #define EEDR0 0 |
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222 | #define EEDR1 1 |
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223 | #define EEDR2 2 |
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224 | #define EEDR3 3 |
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225 | #define EEDR4 4 |
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226 | #define EEDR5 5 |
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227 | #define EEDR6 6 |
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228 | #define EEDR7 7 |
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229 | |
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230 | #define EEAR _SFR_IO16(0x21) |
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231 | |
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232 | #define EEARL _SFR_IO8(0x21) |
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233 | #define EEAR0 0 |
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234 | #define EEAR1 1 |
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235 | #define EEAR2 2 |
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236 | #define EEAR3 3 |
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237 | #define EEAR4 4 |
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238 | #define EEAR5 5 |
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239 | #define EEAR6 6 |
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240 | #define EEAR7 7 |
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241 | |
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242 | #define EEARH _SFR_IO8(0x22) |
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243 | #define EEAR8 0 |
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244 | |
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245 | #define PCICR _SFR_IO8(0x23) |
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246 | #define PCIE0 0 |
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247 | #define PCIE1 1 |
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248 | #define PCIE2 2 |
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249 | |
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250 | #define EIMSK _SFR_IO8(0x24) |
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251 | #define INT0 0 |
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252 | #define INT1 1 |
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253 | |
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254 | #define SVCR _SFR_IO8(0x27) |
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255 | #define SVCS0 0 |
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256 | #define SVCS1 1 |
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257 | #define SVCS2 2 |
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258 | #define SVCS3 3 |
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259 | #define SVCS4 4 |
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260 | |
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261 | #define SCR _SFR_IO8(0x28) |
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262 | #define SMS 0 |
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263 | #define SEN0 1 |
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264 | #define SEN1 2 |
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265 | #define SMEN 3 |
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266 | |
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267 | #define SCCR _SFR_IO8(0x29) |
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268 | #define SRCC0 0 |
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269 | #define SRCC1 1 |
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270 | #define SCCS0 2 |
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271 | #define SCCS1 3 |
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272 | #define SCCS2 4 |
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273 | |
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274 | #define GPIOR1 _SFR_IO8(0x2A) |
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275 | #define GPIOR10 0 |
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276 | #define GPIOR11 1 |
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277 | #define GPIOR12 2 |
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278 | #define GPIOR13 3 |
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279 | #define GPIOR14 4 |
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280 | #define GPIOR15 5 |
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281 | #define GPIOR16 6 |
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282 | #define GPIOR17 7 |
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283 | |
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284 | #define GPIOR2 _SFR_IO8(0x2B) |
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285 | #define GPIOR20 0 |
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286 | #define GPIOR21 1 |
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287 | #define GPIOR22 2 |
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288 | #define GPIOR23 3 |
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289 | #define GPIOR24 4 |
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290 | #define GPIOR25 5 |
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291 | #define GPIOR26 6 |
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292 | #define GPIOR27 7 |
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293 | |
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294 | #define SPCR _SFR_IO8(0x2C) |
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295 | #define SPR0 0 |
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296 | #define SPR1 1 |
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297 | #define CPHA 2 |
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298 | #define CPOL 3 |
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299 | #define MSTR 4 |
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300 | #define DORD 5 |
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301 | #define SPE 6 |
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302 | #define SPIE 7 |
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303 | |
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304 | #define SPSR _SFR_IO8(0x2D) |
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305 | #define SPI2X 0 |
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306 | #define WCOL 6 |
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307 | #define SPIF 7 |
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308 | |
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309 | #define SPDR _SFR_IO8(0x2E) |
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310 | #define SPDR0 0 |
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311 | #define SPDR1 1 |
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312 | #define SPDR2 2 |
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313 | #define SPDR3 3 |
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314 | #define SPDR4 4 |
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315 | #define SPDR5 5 |
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316 | #define SPDR6 6 |
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317 | #define SPDR7 7 |
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318 | |
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319 | #define T2MDR _SFR_IO8(0x2F) |
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320 | #define T2MDR0 0 |
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321 | #define T2MDR1 1 |
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322 | #define T2MDR2 2 |
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323 | #define T2MDR3 3 |
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324 | #define T2MDR4 4 |
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325 | #define T2MDR5 5 |
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326 | #define T2MDR6 6 |
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327 | #define T2MDR7 7 |
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328 | |
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329 | #define LFRR _SFR_IO8(0x30) |
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330 | #define LFRR0 0 |
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331 | #define LFRR1 1 |
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332 | #define LFRR2 2 |
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333 | #define LFRR3 3 |
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334 | #define LFRR4 4 |
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335 | #define LFRR5 5 |
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336 | #define LFRR6 6 |
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337 | |
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338 | #define LFCDR _SFR_IO8(0x32) |
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339 | #define LFDO 0 |
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340 | #define LFRST 6 |
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341 | #define LFSCE 7 |
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342 | |
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343 | #define SMCR _SFR_IO8(0x33) |
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344 | #define SE 0 |
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345 | #define SM0 1 |
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346 | #define SM1 2 |
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347 | #define SM2 3 |
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348 | |
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349 | #define MCUSR _SFR_IO8(0x34) |
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350 | #define PORF 0 |
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351 | #define EXTRF 1 |
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352 | #define BORF 2 |
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353 | #define WDRF 3 |
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354 | #define TSRF 5 |
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355 | |
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356 | #define MCUCR _SFR_IO8(0x35) |
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357 | #define IVCE 0 |
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358 | #define IVSEL 1 |
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359 | #define PUD 4 |
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360 | |
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361 | #define LFRB _SFR_IO8(0x36) |
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362 | #define LFRB0 0 |
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363 | #define LFRB1 1 |
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364 | #define LFRB2 2 |
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365 | #define LFRB3 3 |
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366 | #define LFRB4 4 |
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367 | #define LFRB5 5 |
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368 | #define LFRB6 6 |
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369 | #define LFRB7 7 |
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370 | |
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371 | #define SPMCSR _SFR_IO8(0x37) |
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372 | #define SELFPRGEN 0 |
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373 | #define PGERS 1 |
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374 | #define PGWRT 2 |
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375 | #define BLBSET 3 |
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376 | #define RWWSRE 4 |
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377 | #define RWWSB 6 |
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378 | #define SPMIE 7 |
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379 | |
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380 | #define T1CR _SFR_IO8(0x38) |
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381 | #define T1PS0 0 |
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382 | #define T1PS1 1 |
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383 | #define T1PS2 2 |
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384 | #define T1CS0 3 |
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385 | #define T1CS1 4 |
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386 | #define T1CS2 5 |
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387 | #define T1IE 7 |
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388 | |
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389 | #define T0CR _SFR_IO8(0x39) |
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390 | #define T0PAS0 0 |
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391 | #define T0PAS1 1 |
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392 | #define T0PAS2 2 |
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393 | #define T0IE 3 |
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394 | #define T0PR 4 |
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395 | #define T0PBS0 5 |
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396 | #define T0PBS1 6 |
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397 | #define T0PBS2 7 |
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398 | |
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399 | #define CMIMR _SFR_IO8(0x3B) |
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400 | #define ECIE 0 |
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401 | |
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402 | #define CLKPR _SFR_IO8(0x3C) |
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403 | #define CLKPS0 0 |
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404 | #define CLKPS1 1 |
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405 | #define CLKPS2 2 |
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406 | #define CLTPS0 3 |
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407 | #define CLTPS1 4 |
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408 | #define CLTPS2 5 |
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409 | #define CLPCE 7 |
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410 | |
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411 | #define WDTCR _SFR_MEM8(0x60) |
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412 | #define WDPS0 0 |
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413 | #define WDPS1 1 |
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414 | #define WDPS2 2 |
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415 | #define WDE 3 |
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416 | #define WDCE 4 |
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417 | |
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418 | #define SIMSK _SFR_MEM8(0x61) |
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419 | #define MSIE 0 |
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420 | |
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421 | #define TSCR _SFR_MEM8(0x64) |
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422 | #define TSSD 0 |
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423 | |
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424 | #define SRCCAL _SFR_MEM8(0x65) |
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425 | #define SCAL0 0 |
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426 | #define SCAL1 1 |
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427 | #define SCAL2 2 |
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428 | #define SCAL3 3 |
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429 | #define SCAL4 4 |
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430 | #define SCAL5 5 |
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431 | #define SCAL6 6 |
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432 | #define SCAL7 7 |
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433 | |
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434 | #define FRCCAL _SFR_MEM8(0x66) |
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435 | #define FCAL0 0 |
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436 | #define FCAL1 1 |
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437 | #define FCAL2 2 |
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438 | #define FCAL3 3 |
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439 | #define FCAL4 4 |
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440 | #define FCAL5 5 |
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441 | #define FCAL6 6 |
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442 | #define FCAL7 7 |
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443 | |
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444 | #define MSVCAL _SFR_MEM8(0x67) |
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445 | #define VRCAL0 0 |
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446 | #define VRCAL1 1 |
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447 | #define VRCAL2 2 |
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448 | #define VRCAL3 3 |
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449 | #define VRCAL4 4 |
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450 | #define VRCAL5 5 |
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451 | #define VRCAL6 6 |
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452 | #define VRCAL7 7 |
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453 | |
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454 | #define BGCAL _SFR_MEM8(0x68) |
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455 | #define BGCAL0 0 |
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456 | #define BGCAL1 1 |
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457 | #define BGCAL2 2 |
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458 | #define BGCAL3 3 |
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459 | #define BGCAL4 4 |
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460 | #define BGCAL5 5 |
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461 | #define BGCAL6 6 |
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462 | #define BGCAL7 7 |
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463 | |
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464 | #define EICRA _SFR_MEM8(0x69) |
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465 | #define ISC00 0 |
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466 | #define ISC01 1 |
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467 | #define ISC10 2 |
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468 | #define ISC11 3 |
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469 | |
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470 | #define PCMSK0 _SFR_MEM8(0x6A) |
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471 | #define PCINT0 0 |
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472 | #define PCINT1 1 |
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473 | #define PCINT2 2 |
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474 | #define PCINT3 3 |
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475 | #define PCINT4 4 |
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476 | #define PCINT5 5 |
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477 | #define PCINT6 6 |
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478 | #define PCINT7 7 |
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479 | |
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480 | #define PCMSK1 _SFR_MEM8(0x6B) |
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481 | #define PCINT8 0 |
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482 | #define PCINT9 1 |
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483 | #define PCINT10 2 |
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484 | |
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485 | #define PCMSK2 _SFR_MEM8(0x6C) |
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486 | #define PCINT16 0 |
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487 | #define PCINT17 1 |
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488 | #define PCINT18 2 |
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489 | #define PCINT19 3 |
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490 | #define PCINT20 4 |
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491 | #define PCINT21 5 |
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492 | #define PCINT22 6 |
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493 | #define PCINT23 7 |
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494 | |
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495 | #define T2ICR _SFR_MEM16(0x6E) |
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496 | |
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497 | #define T2ICRL _SFR_MEM8(0x6E) |
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498 | #define T2ICRL0 0 |
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499 | #define T2ICRL1 1 |
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500 | #define T2ICRL2 2 |
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501 | #define T2ICRL3 3 |
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502 | #define T2ICRL4 4 |
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503 | #define T2ICRL5 5 |
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504 | #define T2ICRL6 6 |
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505 | #define T2ICRL7 7 |
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506 | |
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507 | #define T2ICRH _SFR_MEM8(0x6F) |
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508 | #define T2ICRH0 0 |
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509 | #define T2ICRH1 1 |
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510 | #define T2ICRH2 2 |
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511 | #define T2ICRH3 3 |
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512 | #define T2ICRH4 4 |
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513 | #define T2ICRH5 5 |
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514 | #define T2ICRH6 6 |
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515 | #define T2ICRH7 7 |
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516 | |
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517 | #define T2COR _SFR_MEM16(0x70) |
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518 | |
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519 | #define T2CORL _SFR_MEM8(0x70) |
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520 | #define T2CORL0 0 |
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521 | #define T2CORL1 1 |
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522 | #define T2CORL2 2 |
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523 | #define T2CORL3 3 |
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524 | #define T2CORL4 4 |
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525 | #define T2CORL5 5 |
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526 | #define T2CORL6 6 |
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527 | #define T2CORL7 7 |
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528 | |
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529 | #define T2CORH _SFR_MEM8(0x71) |
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530 | #define T2CORH0 0 |
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531 | #define T2CORH1 1 |
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532 | #define T2CORH2 2 |
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533 | #define T2CORH3 3 |
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534 | #define T2CORH4 4 |
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535 | #define T2CORH5 5 |
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536 | #define T2CORH6 6 |
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537 | #define T2CORH7 7 |
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538 | |
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539 | #define T2MRA _SFR_MEM8(0x72) |
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540 | #define T2CS0 0 |
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541 | #define T2CS1 1 |
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542 | #define T2CS2 2 |
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543 | #define T2CE0 3 |
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544 | #define T2CE1 4 |
---|
545 | #define T2CNC 5 |
---|
546 | #define T2TP0 6 |
---|
547 | #define T2TP1 7 |
---|
548 | |
---|
549 | #define T2MRB _SFR_MEM8(0x73) |
---|
550 | #define T2M0 0 |
---|
551 | #define T2M1 1 |
---|
552 | #define T2M2 2 |
---|
553 | #define T2M3 3 |
---|
554 | #define T2TOP 4 |
---|
555 | #define T2CPOL 6 |
---|
556 | #define T2SSIE 7 |
---|
557 | |
---|
558 | #define T2IMR _SFR_MEM8(0x74) |
---|
559 | #define T2OIM 0 |
---|
560 | #define T2CIM 1 |
---|
561 | #define T2CPIM 2 |
---|
562 | #define T2RXIM 3 |
---|
563 | #define T2TXIM 4 |
---|
564 | #define T2TCIM 5 |
---|
565 | |
---|
566 | #define T3ICR _SFR_MEM16(0x76) |
---|
567 | |
---|
568 | #define T3ICRL _SFR_MEM8(0x76) |
---|
569 | #define T3ICRL0 0 |
---|
570 | #define T3ICRL1 1 |
---|
571 | #define T3ICRL2 2 |
---|
572 | #define T3ICRL3 3 |
---|
573 | #define T3ICRL4 4 |
---|
574 | #define T3ICRL5 5 |
---|
575 | #define T3ICRL6 6 |
---|
576 | #define T3ICRL7 7 |
---|
577 | |
---|
578 | #define T3ICRH _SFR_MEM8(0x77) |
---|
579 | #define T3ICRH0 0 |
---|
580 | #define T3ICRH1 1 |
---|
581 | #define T3ICRH2 2 |
---|
582 | #define T3ICRH3 3 |
---|
583 | #define T3ICRH4 4 |
---|
584 | #define T3ICRH5 5 |
---|
585 | #define T3ICRH6 6 |
---|
586 | #define T3ICRH7 7 |
---|
587 | |
---|
588 | #define T3CORA _SFR_MEM16(0x78) |
---|
589 | |
---|
590 | #define T3CORAL _SFR_MEM8(0x78) |
---|
591 | #define T3CORAL0 0 |
---|
592 | #define T3CORAL1 1 |
---|
593 | #define T3CORAL2 2 |
---|
594 | #define T3CORAL3 3 |
---|
595 | #define T3CORAL4 4 |
---|
596 | #define T3CORAL5 5 |
---|
597 | #define T3CORAL6 6 |
---|
598 | #define T3CORAL7 7 |
---|
599 | |
---|
600 | #define T3CORAH _SFR_MEM8(0x79) |
---|
601 | #define T3CORAH0 0 |
---|
602 | #define T3CORAH1 1 |
---|
603 | #define T3CORAH2 2 |
---|
604 | #define T3CORAH3 3 |
---|
605 | #define T3CORAH4 4 |
---|
606 | #define T3CORAH5 5 |
---|
607 | #define T3CORAH6 6 |
---|
608 | #define T3CORAH7 7 |
---|
609 | |
---|
610 | #define T3CORB _SFR_MEM16(0x7A) |
---|
611 | |
---|
612 | #define T3CORBL _SFR_MEM8(0x7A) |
---|
613 | #define T3CORBL0 0 |
---|
614 | #define T3CORBL1 1 |
---|
615 | #define T3CORBL2 2 |
---|
616 | #define T3CORBL3 3 |
---|
617 | #define T3CORBL4 4 |
---|
618 | #define T3CORBL5 5 |
---|
619 | #define T3CORBL6 6 |
---|
620 | #define T3CORBL7 7 |
---|
621 | |
---|
622 | #define T3CORBH _SFR_MEM8(0x7B) |
---|
623 | #define T3CORBH0 0 |
---|
624 | #define T3CORBH1 1 |
---|
625 | #define T3CORBH2 2 |
---|
626 | #define T3CORBH3 3 |
---|
627 | #define T3CORBH4 4 |
---|
628 | #define T3CORBH5 5 |
---|
629 | #define T3CORBH6 6 |
---|
630 | #define T3CORBH7 7 |
---|
631 | |
---|
632 | #define T3MRA _SFR_MEM8(0x7C) |
---|
633 | #define T3CS0 0 |
---|
634 | #define T3CS1 1 |
---|
635 | #define T3CS2 2 |
---|
636 | #define T3CE0 3 |
---|
637 | #define T3CE1 4 |
---|
638 | #define T3CNC 5 |
---|
639 | #define T3ICS0 6 |
---|
640 | #define T3ICS1 7 |
---|
641 | |
---|
642 | #define T3MRB _SFR_MEM8(0x7D) |
---|
643 | #define T3M0 0 |
---|
644 | #define T3M1 1 |
---|
645 | #define T3M2 2 |
---|
646 | #define T3TOP 4 |
---|
647 | |
---|
648 | #define T3CRB _SFR_MEM8(0x7E) |
---|
649 | #define T3CTMA 0 |
---|
650 | #define T3SAMA 1 |
---|
651 | #define T3CRMA 2 |
---|
652 | #define T3CTMB 3 |
---|
653 | #define T3SAMB 4 |
---|
654 | #define T3CRMB 5 |
---|
655 | #define T3CPRM 6 |
---|
656 | |
---|
657 | #define T3IMR _SFR_MEM8(0x7F) |
---|
658 | #define T3OIM 0 |
---|
659 | #define T3CAIM 1 |
---|
660 | #define T3CBIM 2 |
---|
661 | #define T3CPIM 3 |
---|
662 | |
---|
663 | #define LFIMR _SFR_MEM8(0x81) |
---|
664 | #define LFWIM 0 |
---|
665 | #define LFBIM 1 |
---|
666 | #define LFEIM 2 |
---|
667 | |
---|
668 | #define LFRCR _SFR_MEM8(0x82) |
---|
669 | #define LFEN 0 |
---|
670 | #define LFBM 1 |
---|
671 | #define LFWM0 2 |
---|
672 | #define LFWM1 3 |
---|
673 | #define LFRSS 4 |
---|
674 | #define LFCS0 5 |
---|
675 | #define LFCS1 6 |
---|
676 | #define LFCS2 7 |
---|
677 | |
---|
678 | #define LFHCR _SFR_MEM8(0x83) |
---|
679 | #define LFHCR0 0 |
---|
680 | #define LFHCR1 1 |
---|
681 | #define LFHCR2 2 |
---|
682 | #define LFHCR3 3 |
---|
683 | #define LFHCR4 4 |
---|
684 | #define LFHCR5 5 |
---|
685 | #define LFHCR6 6 |
---|
686 | |
---|
687 | #define LFIDC _SFR_MEM16(0x84) |
---|
688 | |
---|
689 | #define LFIDCL _SFR_MEM8(0x84) |
---|
690 | #define LFIDCL_0 0 |
---|
691 | #define LFIDCL_1 1 |
---|
692 | #define LFIDCL_2 2 |
---|
693 | #define LFIDCL_3 3 |
---|
694 | #define LFIDCL_4 4 |
---|
695 | #define LFIDCL_5 5 |
---|
696 | #define LFIDCL_6 6 |
---|
697 | #define LFIDCL_7 7 |
---|
698 | |
---|
699 | #define LFIDCH _SFR_MEM8(0x85) |
---|
700 | #define LFIDCH_8 0 |
---|
701 | #define LFIDCH_9 1 |
---|
702 | #define LFIDCH_10 2 |
---|
703 | #define LFIDCH_11 3 |
---|
704 | #define LFIDCH_12 4 |
---|
705 | #define LFIDCH_13 5 |
---|
706 | #define LFIDCH_14 6 |
---|
707 | #define LFIDCH_15 7 |
---|
708 | |
---|
709 | #define LFCAL _SFR_MEM16(0x86) |
---|
710 | |
---|
711 | #define LFCALL _SFR_MEM8(0x86) |
---|
712 | #define LFCAL_00 0 |
---|
713 | #define LFCAL_01 1 |
---|
714 | #define LFCAL_02 2 |
---|
715 | #define LFCAL_03 3 |
---|
716 | #define LFCAL_04 4 |
---|
717 | #define LFCAL_05 5 |
---|
718 | #define LFCAL_06 6 |
---|
719 | #define LFCAL_07 7 |
---|
720 | |
---|
721 | #define LFCALH _SFR_MEM8(0x87) |
---|
722 | #define LFCAL_08 0 |
---|
723 | #define LFCAL_09 1 |
---|
724 | #define LFCAL_10 2 |
---|
725 | #define LFCAL_11 3 |
---|
726 | #define LFCAL_12 4 |
---|
727 | #define LFCAL_13 5 |
---|
728 | #define LFCAL_14 6 |
---|
729 | #define LFCAL_15 7 |
---|
730 | |
---|
731 | |
---|
732 | /* Interrupt vectors */ |
---|
733 | /* Vector 0 is the reset vector */ |
---|
734 | #define INT0_vect_num 1 |
---|
735 | #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ |
---|
736 | #define INT1_vect_num 2 |
---|
737 | #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ |
---|
738 | #define PCINT0_vect_num 3 |
---|
739 | #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ |
---|
740 | #define PCINT1_vect_num 4 |
---|
741 | #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ |
---|
742 | #define PCINT2_vect_num 5 |
---|
743 | #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 2 */ |
---|
744 | #define INTVM_vect_num 6 |
---|
745 | #define INTVM_vect _VECTOR(6) /* Voltage Monitor Interrupt */ |
---|
746 | #define SENINT_vect_num 7 |
---|
747 | #define SENINT_vect _VECTOR(7) /* Sensor Interface Interrupt */ |
---|
748 | #define INTT0_vect_num 8 |
---|
749 | #define INTT0_vect _VECTOR(8) /* Timer0 Interval Interrupt */ |
---|
750 | #define LFWP_vect_num 9 |
---|
751 | #define LFWP_vect _VECTOR(9) /* LF-Receiver Wake-up Interrupt */ |
---|
752 | #define T3CAP_vect_num 10 |
---|
753 | #define T3CAP_vect _VECTOR(10) /* Timer/Counter3 Capture Event */ |
---|
754 | #define T3COMA_vect_num 11 |
---|
755 | #define T3COMA_vect _VECTOR(11) /* Timer/Counter3 Compare Match A */ |
---|
756 | #define T3COMB_vect_num 12 |
---|
757 | #define T3COMB_vect _VECTOR(12) /* Timer/Counter3 Compare Match B */ |
---|
758 | #define T3OVF_vect_num 13 |
---|
759 | #define T3OVF_vect _VECTOR(13) /* Timer/Counter3 Overflow */ |
---|
760 | #define T2CAP_vect_num 14 |
---|
761 | #define T2CAP_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ |
---|
762 | #define T2COM_vect_num 15 |
---|
763 | #define T2COM_vect _VECTOR(15) /* Timer/Counter2 Compare Match */ |
---|
764 | #define T2OVF_vect_num 16 |
---|
765 | #define T2OVF_vect _VECTOR(16) /* Timer/Counter2 Overflow */ |
---|
766 | #define SPISTC_vect_num 17 |
---|
767 | #define SPISTC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ |
---|
768 | #define LFRXB_vect_num 18 |
---|
769 | #define LFRXB_vect _VECTOR(18) /* LF Receive Buffer Interrupt */ |
---|
770 | #define INTT1_vect_num 19 |
---|
771 | #define INTT1_vect _VECTOR(19) /* Timer1 Interval Interrupt */ |
---|
772 | #define T2RXB_vect_num 20 |
---|
773 | #define T2RXB_vect _VECTOR(20) /* Timer2 SSI Receive Buffer Interrupt */ |
---|
774 | #define T2TXB_vect_num 21 |
---|
775 | #define T2TXB_vect _VECTOR(21) /* Timer2 SSI Transmit Buffer Interrupt */ |
---|
776 | #define T2TXC_vect_num 22 |
---|
777 | #define T2TXC_vect _VECTOR(22) /* Timer2 SSI Transmit Complete Interrupt */ |
---|
778 | #define LFREOB_vect_num 23 |
---|
779 | #define LFREOB_vect _VECTOR(23) /* LF-Receiver End of Burst Interrupt */ |
---|
780 | #define EXCM_vect_num 24 |
---|
781 | #define EXCM_vect _VECTOR(24) /* External Input Clock break down Interrupt */ |
---|
782 | #define EEREADY_vect_num 25 |
---|
783 | #define EEREADY_vect _VECTOR(25) /* EEPROM Ready Interrupt */ |
---|
784 | #define SPM_RDY_vect_num 26 |
---|
785 | #define SPM_RDY_vect _VECTOR(26) /* Store Program Memory Ready */ |
---|
786 | |
---|
787 | #define _VECTOR_SIZE 2 /* Size of individual vector. */ |
---|
788 | #define _VECTORS_SIZE (27 * _VECTOR_SIZE) |
---|
789 | |
---|
790 | |
---|
791 | /* Constants */ |
---|
792 | #define SPM_PAGESIZE (64) |
---|
793 | #define RAMSTART (0x100) |
---|
794 | #define RAMSIZE (512) |
---|
795 | #define RAMEND (RAMSTART + RAMSIZE - 1) |
---|
796 | #define XRAMSTART (NA) |
---|
797 | #define XRAMSIZE (0) |
---|
798 | #define XRAMEND RAMEND |
---|
799 | #define E2END (320 - 1) |
---|
800 | #define E2PAGESIZE (4) |
---|
801 | #define FLASHEND (8192 - 1) |
---|
802 | |
---|
803 | |
---|
804 | /* Fuses */ |
---|
805 | #define FUSE_MEMORY_SIZE 2 |
---|
806 | |
---|
807 | /* Low Fuse Byte */ |
---|
808 | #define FUSE_TSRDI ~_BV(0) /* Disable Temperature shutdown Reset */ |
---|
809 | #define FUSE_BODEN ~_BV(1) /* Enable Brown-out detection */ |
---|
810 | #define FUSE_FRCFS ~_BV(2) /* Fast RC-Oscillator Frequency select */ |
---|
811 | #define FUSE_WDRCON ~_BV(3) /* Enable Watchdog RC-Oscillator */ |
---|
812 | #define FUSE_SUT0 ~_BV(4) /* Select start-up time */ |
---|
813 | #define FUSE_SUT1 ~_BV(5) /* Select start-up time */ |
---|
814 | #define FUSE_CKOUT ~_BV(6) /* Clock output */ |
---|
815 | #define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ |
---|
816 | #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN) |
---|
817 | |
---|
818 | /* High Fuse Byte */ |
---|
819 | #define FUSE_BOOTRST ~_BV(0) /* Select reset vector */ |
---|
820 | #define FUSE_BOOTSZ0 ~_BV(1) /* Boot size select */ |
---|
821 | #define FUSE_BOOTSZ1 ~_BV(2) /* Boot size select */ |
---|
822 | #define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ |
---|
823 | #define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */ |
---|
824 | #define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ |
---|
825 | #define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */ |
---|
826 | #define FUSE_EELOCK ~_BV(7) /* Upper EEPROM Locked (disabled) */ |
---|
827 | #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) |
---|
828 | |
---|
829 | |
---|
830 | /* Lock Bits */ |
---|
831 | #define __LOCK_BITS_EXIST |
---|
832 | #define __BOOT_LOCK_BITS_0_EXIST |
---|
833 | #define __BOOT_LOCK_BITS_1_EXIST |
---|
834 | |
---|
835 | |
---|
836 | /* Signature */ |
---|
837 | #define SIGNATURE_0 0x1E |
---|
838 | #define SIGNATURE_1 0x93 |
---|
839 | #define SIGNATURE_2 0x82 |
---|
840 | |
---|
841 | |
---|
842 | #endif /* _AVR_ATA6289_H_ */ |
---|
843 | |
---|