source: rtems/cpukit/score/cpu/avr/avr/ioa6289.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 17.2 KB
Line 
1/* Copyright (c) 2008 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/ioa6289.h - definitions for ATA6289 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "ioa6289.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATA6289_H_
49#define _AVR_ATA6289_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINB _SFR_IO8(0x03)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59#define PINB4 4
60#define PINB5 5
61#define PINB6 6
62#define PINB7 7
63
64#define DDRB _SFR_IO8(0x04)
65#define DDB0 0
66#define DDB1 1
67#define DDB2 2
68#define DDB3 3
69#define DDB4 4
70#define DDB5 5
71#define DDB6 6
72#define DDB7 7
73
74#define PORTB _SFR_IO8(0x05)
75#define PORTB0 0
76#define PORTB1 1
77#define PORTB2 2
78#define PORTB3 3
79#define PORTB4 4
80#define PORTB5 5
81#define PORTB6 6
82#define PORTB7 7
83
84#define PINC _SFR_IO8(0x06)
85#define PINC0 0
86#define PINC1 1
87
88#define DDRC _SFR_IO8(0x07)
89
90#define PORTC _SFR_IO8(0x08)
91#define PORTC0 0
92#define PORTC1 1
93
94#define PIND _SFR_IO8(0x09)
95#define PIND0 0
96#define PIND1 1
97#define PIND2 2
98#define PIND3 3
99#define PIND4 4
100#define PIND5 5
101#define PIND6 6
102#define PIND7 7
103
104#define DDRD _SFR_IO8(0x0A)
105#define DDD0 0
106#define DDD1 1
107#define DDD2 2
108#define DDD3 3
109#define DDD4 4
110#define DDD5 5
111#define DDD6 6
112#define DDD7 7
113
114#define PORTD _SFR_IO8(0x0B)
115#define PORTD0 0
116#define PORTD1 1
117#define PORTD2 2
118#define PORTD3 3
119#define PORTD4 4
120#define PORTD5 5
121#define PORTD6 6
122#define PORTD7 7
123
124#define CMCR _SFR_IO8(0x0F)
125#define CMM0 0
126#define CMM1 1
127#define SRCD 2
128#define CMONEN 3
129#define CCS 4
130#define ECINS 5
131#define CMCCE 7
132
133#define CMSR _SFR_IO8(0x10)
134#define ECF 0
135
136#define T2CRA _SFR_IO8(0x11)
137#define T2OTM 0
138#define T2CTM 1
139#define T2CR 2
140#define T2CRM 3
141#define T2CPRM 4
142#define T2ICS 5
143#define T2TS 6
144#define T2E 7
145
146#define T2CRB _SFR_IO8(0x12)
147#define T2SCE 0
148
149#define T3CRA _SFR_IO8(0x14)
150#define T3AC 0
151#define T3SCE 1
152#define T3CR 2
153#define T3TS 6
154#define T3E 7
155
156#define VMCSR _SFR_IO8(0x16)
157#define VMEN 0
158#define VMLS0 1
159#define VMLS1 2
160#define VMLS2 3
161#define VMIM 4
162#define VMF 5
163#define BODPD 6
164#define BODLS 7
165
166#define PCIFR _SFR_IO8(0x17)
167#define PCIF0 0
168#define PCIF1 1
169#define PCIF2 2
170
171#define LFFR _SFR_IO8(0x18)
172#define LFWPF 0
173#define LFBF 1
174#define LFEDF 2
175#define LFRF 3
176
177#define SSFR _SFR_IO8(0x19)
178#define MSENF 0
179#define MSENO 1
180
181#define T10IFR _SFR_IO8(0x1A)
182#define T0F 0
183#define T1F 1
184
185#define T2IFR _SFR_IO8(0x1B)
186#define T2OFF 0
187#define T2COF 1
188#define T2ICF 2
189#define T2RXF 3
190#define T2TXF 4
191#define T2TCF 5
192
193#define T3IFR _SFR_IO8(0x1C)
194#define T3OFF 0
195#define T3COAF 1
196#define T3COBF 2
197#define T3ICF 3
198
199#define EIFR _SFR_IO8(0x1D)
200#define INTF0 0
201#define INTF1 1
202
203#define GPIOR0 _SFR_IO8(0x1E)
204#define GPIOR00 0
205#define GPIOR01 1
206#define GPIOR02 2
207#define GPIOR03 3
208#define GPIOR04 4
209#define GPIOR05 5
210#define GPIOR06 6
211#define GPIOR07 7
212
213#define EECR _SFR_IO8(0x1F)
214#define EERE 0
215#define EEWE 1
216#define EEMWE 2
217#define EERIE 3
218#define EEPM0 4
219#define EEPM1 5
220
221#define EEDR _SFR_IO8(0x20)
222#define EEDR0 0
223#define EEDR1 1
224#define EEDR2 2
225#define EEDR3 3
226#define EEDR4 4
227#define EEDR5 5
228#define EEDR6 6
229#define EEDR7 7
230
231#define EEAR _SFR_IO16(0x21)
232
233#define EEARL _SFR_IO8(0x21)
234#define EEAR0 0
235#define EEAR1 1
236#define EEAR2 2
237#define EEAR3 3
238#define EEAR4 4
239#define EEAR5 5
240#define EEAR6 6
241#define EEAR7 7
242
243#define EEARH _SFR_IO8(0x22)
244#define EEAR8 0
245
246#define PCICR _SFR_IO8(0x23)
247#define PCIE0 0
248#define PCIE1 1
249#define PCIE2 2
250
251#define EIMSK _SFR_IO8(0x24)
252#define INT0 0
253#define INT1 1
254
255#define SVCR _SFR_IO8(0x27)
256#define SVCS0 0
257#define SVCS1 1
258#define SVCS2 2
259#define SVCS3 3
260#define SVCS4 4
261
262#define SCR _SFR_IO8(0x28)
263#define SMS 0
264#define SEN0 1
265#define SEN1 2
266#define SMEN 3
267
268#define SCCR _SFR_IO8(0x29)
269#define SRCC0 0
270#define SRCC1 1
271#define SCCS0 2
272#define SCCS1 3
273#define SCCS2 4
274
275#define GPIOR1 _SFR_IO8(0x2A)
276#define GPIOR10 0
277#define GPIOR11 1
278#define GPIOR12 2
279#define GPIOR13 3
280#define GPIOR14 4
281#define GPIOR15 5
282#define GPIOR16 6
283#define GPIOR17 7
284
285#define GPIOR2 _SFR_IO8(0x2B)
286#define GPIOR20 0
287#define GPIOR21 1
288#define GPIOR22 2
289#define GPIOR23 3
290#define GPIOR24 4
291#define GPIOR25 5
292#define GPIOR26 6
293#define GPIOR27 7
294
295#define SPCR _SFR_IO8(0x2C)
296#define SPR0 0
297#define SPR1 1
298#define CPHA 2
299#define CPOL 3
300#define MSTR 4
301#define DORD 5
302#define SPE 6
303#define SPIE 7
304
305#define SPSR _SFR_IO8(0x2D)
306#define SPI2X 0
307#define WCOL 6
308#define SPIF 7
309
310#define SPDR _SFR_IO8(0x2E)
311#define SPDR0 0
312#define SPDR1 1
313#define SPDR2 2
314#define SPDR3 3
315#define SPDR4 4
316#define SPDR5 5
317#define SPDR6 6
318#define SPDR7 7
319
320#define T2MDR _SFR_IO8(0x2F)
321#define T2MDR0 0
322#define T2MDR1 1
323#define T2MDR2 2
324#define T2MDR3 3
325#define T2MDR4 4
326#define T2MDR5 5
327#define T2MDR6 6
328#define T2MDR7 7
329
330#define LFRR _SFR_IO8(0x30)
331#define LFRR0 0
332#define LFRR1 1
333#define LFRR2 2
334#define LFRR3 3
335#define LFRR4 4
336#define LFRR5 5
337#define LFRR6 6
338
339#define LFCDR _SFR_IO8(0x32)
340#define LFDO 0
341#define LFRST 6
342#define LFSCE 7
343
344#define SMCR _SFR_IO8(0x33)
345#define SE 0
346#define SM0 1
347#define SM1 2
348#define SM2 3
349
350#define MCUSR _SFR_IO8(0x34)
351#define PORF 0
352#define EXTRF 1
353#define BORF 2
354#define WDRF 3
355#define TSRF 5
356
357#define MCUCR _SFR_IO8(0x35)
358#define IVCE 0
359#define IVSEL 1
360#define PUD 4
361
362#define LFRB _SFR_IO8(0x36)
363#define LFRB0 0
364#define LFRB1 1
365#define LFRB2 2
366#define LFRB3 3
367#define LFRB4 4
368#define LFRB5 5
369#define LFRB6 6
370#define LFRB7 7
371
372#define SPMCSR _SFR_IO8(0x37)
373#define SELFPRGEN 0
374#define PGERS 1
375#define PGWRT 2
376#define BLBSET 3
377#define RWWSRE 4
378#define RWWSB 6
379#define SPMIE 7
380
381#define T1CR _SFR_IO8(0x38)
382#define T1PS0 0
383#define T1PS1 1
384#define T1PS2 2
385#define T1CS0 3
386#define T1CS1 4
387#define T1CS2 5
388#define T1IE 7
389
390#define T0CR _SFR_IO8(0x39)
391#define T0PAS0 0
392#define T0PAS1 1
393#define T0PAS2 2
394#define T0IE 3
395#define T0PR 4
396#define T0PBS0 5
397#define T0PBS1 6
398#define T0PBS2 7
399
400#define CMIMR _SFR_IO8(0x3B)
401#define ECIE 0
402
403#define CLKPR _SFR_IO8(0x3C)
404#define CLKPS0 0
405#define CLKPS1 1
406#define CLKPS2 2
407#define CLTPS0 3
408#define CLTPS1 4
409#define CLTPS2 5
410#define CLPCE 7
411
412#define WDTCR _SFR_MEM8(0x60)
413#define WDPS0 0
414#define WDPS1 1
415#define WDPS2 2
416#define WDE 3
417#define WDCE 4
418
419#define SIMSK _SFR_MEM8(0x61)
420#define MSIE 0
421
422#define TSCR _SFR_MEM8(0x64)
423#define TSSD 0
424
425#define SRCCAL _SFR_MEM8(0x65)
426#define SCAL0 0
427#define SCAL1 1
428#define SCAL2 2
429#define SCAL3 3
430#define SCAL4 4
431#define SCAL5 5
432#define SCAL6 6
433#define SCAL7 7
434
435#define FRCCAL _SFR_MEM8(0x66)
436#define FCAL0 0
437#define FCAL1 1
438#define FCAL2 2
439#define FCAL3 3
440#define FCAL4 4
441#define FCAL5 5
442#define FCAL6 6
443#define FCAL7 7
444
445#define MSVCAL _SFR_MEM8(0x67)
446#define VRCAL0 0
447#define VRCAL1 1
448#define VRCAL2 2
449#define VRCAL3 3
450#define VRCAL4 4
451#define VRCAL5 5
452#define VRCAL6 6
453#define VRCAL7 7
454
455#define BGCAL _SFR_MEM8(0x68)
456#define BGCAL0 0
457#define BGCAL1 1
458#define BGCAL2 2
459#define BGCAL3 3
460#define BGCAL4 4
461#define BGCAL5 5
462#define BGCAL6 6
463#define BGCAL7 7
464
465#define EICRA _SFR_MEM8(0x69)
466#define ISC00 0
467#define ISC01 1
468#define ISC10 2
469#define ISC11 3
470
471#define PCMSK0 _SFR_MEM8(0x6A)
472#define PCINT0 0
473#define PCINT1 1
474#define PCINT2 2
475#define PCINT3 3
476#define PCINT4 4
477#define PCINT5 5
478#define PCINT6 6
479#define PCINT7 7
480
481#define PCMSK1 _SFR_MEM8(0x6B)
482#define PCINT8 0
483#define PCINT9 1
484#define PCINT10 2
485
486#define PCMSK2 _SFR_MEM8(0x6C)
487#define PCINT16 0
488#define PCINT17 1
489#define PCINT18 2
490#define PCINT19 3
491#define PCINT20 4
492#define PCINT21 5
493#define PCINT22 6
494#define PCINT23 7
495
496#define T2ICR _SFR_MEM16(0x6E)
497
498#define T2ICRL _SFR_MEM8(0x6E)
499#define T2ICRL0 0
500#define T2ICRL1 1
501#define T2ICRL2 2
502#define T2ICRL3 3
503#define T2ICRL4 4
504#define T2ICRL5 5
505#define T2ICRL6 6
506#define T2ICRL7 7
507
508#define T2ICRH _SFR_MEM8(0x6F)
509#define T2ICRH0 0
510#define T2ICRH1 1
511#define T2ICRH2 2
512#define T2ICRH3 3
513#define T2ICRH4 4
514#define T2ICRH5 5
515#define T2ICRH6 6
516#define T2ICRH7 7
517
518#define T2COR _SFR_MEM16(0x70)
519
520#define T2CORL _SFR_MEM8(0x70)
521#define T2CORL0 0
522#define T2CORL1 1
523#define T2CORL2 2
524#define T2CORL3 3
525#define T2CORL4 4
526#define T2CORL5 5
527#define T2CORL6 6
528#define T2CORL7 7
529
530#define T2CORH _SFR_MEM8(0x71)
531#define T2CORH0 0
532#define T2CORH1 1
533#define T2CORH2 2
534#define T2CORH3 3
535#define T2CORH4 4
536#define T2CORH5 5
537#define T2CORH6 6
538#define T2CORH7 7
539
540#define T2MRA _SFR_MEM8(0x72)
541#define T2CS0 0
542#define T2CS1 1
543#define T2CS2 2
544#define T2CE0 3
545#define T2CE1 4
546#define T2CNC 5
547#define T2TP0 6
548#define T2TP1 7
549
550#define T2MRB _SFR_MEM8(0x73)
551#define T2M0 0
552#define T2M1 1
553#define T2M2 2
554#define T2M3 3
555#define T2TOP 4
556#define T2CPOL 6
557#define T2SSIE 7
558
559#define T2IMR _SFR_MEM8(0x74)
560#define T2OIM 0
561#define T2CIM 1
562#define T2CPIM 2
563#define T2RXIM 3
564#define T2TXIM 4
565#define T2TCIM 5
566
567#define T3ICR _SFR_MEM16(0x76)
568
569#define T3ICRL _SFR_MEM8(0x76)
570#define T3ICRL0 0
571#define T3ICRL1 1
572#define T3ICRL2 2
573#define T3ICRL3 3
574#define T3ICRL4 4
575#define T3ICRL5 5
576#define T3ICRL6 6
577#define T3ICRL7 7
578
579#define T3ICRH _SFR_MEM8(0x77)
580#define T3ICRH0 0
581#define T3ICRH1 1
582#define T3ICRH2 2
583#define T3ICRH3 3
584#define T3ICRH4 4
585#define T3ICRH5 5
586#define T3ICRH6 6
587#define T3ICRH7 7
588
589#define T3CORA _SFR_MEM16(0x78)
590
591#define T3CORAL _SFR_MEM8(0x78)
592#define T3CORAL0 0
593#define T3CORAL1 1
594#define T3CORAL2 2
595#define T3CORAL3 3
596#define T3CORAL4 4
597#define T3CORAL5 5
598#define T3CORAL6 6
599#define T3CORAL7 7
600
601#define T3CORAH _SFR_MEM8(0x79)
602#define T3CORAH0 0
603#define T3CORAH1 1
604#define T3CORAH2 2
605#define T3CORAH3 3
606#define T3CORAH4 4
607#define T3CORAH5 5
608#define T3CORAH6 6
609#define T3CORAH7 7
610
611#define T3CORB _SFR_MEM16(0x7A)
612
613#define T3CORBL _SFR_MEM8(0x7A)
614#define T3CORBL0 0
615#define T3CORBL1 1
616#define T3CORBL2 2
617#define T3CORBL3 3
618#define T3CORBL4 4
619#define T3CORBL5 5
620#define T3CORBL6 6
621#define T3CORBL7 7
622
623#define T3CORBH _SFR_MEM8(0x7B)
624#define T3CORBH0 0
625#define T3CORBH1 1
626#define T3CORBH2 2
627#define T3CORBH3 3
628#define T3CORBH4 4
629#define T3CORBH5 5
630#define T3CORBH6 6
631#define T3CORBH7 7
632
633#define T3MRA _SFR_MEM8(0x7C)
634#define T3CS0 0
635#define T3CS1 1
636#define T3CS2 2
637#define T3CE0 3
638#define T3CE1 4
639#define T3CNC 5
640#define T3ICS0 6
641#define T3ICS1 7
642
643#define T3MRB _SFR_MEM8(0x7D)
644#define T3M0 0
645#define T3M1 1
646#define T3M2 2
647#define T3TOP 4
648
649#define T3CRB _SFR_MEM8(0x7E)
650#define T3CTMA 0
651#define T3SAMA 1
652#define T3CRMA 2
653#define T3CTMB 3
654#define T3SAMB 4
655#define T3CRMB 5
656#define T3CPRM 6
657
658#define T3IMR _SFR_MEM8(0x7F)
659#define T3OIM 0
660#define T3CAIM 1
661#define T3CBIM 2
662#define T3CPIM 3
663
664#define LFIMR _SFR_MEM8(0x81)
665#define LFWIM 0
666#define LFBIM 1
667#define LFEIM 2
668
669#define LFRCR _SFR_MEM8(0x82)
670#define LFEN 0
671#define LFBM 1
672#define LFWM0 2
673#define LFWM1 3
674#define LFRSS 4
675#define LFCS0 5
676#define LFCS1 6
677#define LFCS2 7
678
679#define LFHCR _SFR_MEM8(0x83)
680#define LFHCR0 0
681#define LFHCR1 1
682#define LFHCR2 2
683#define LFHCR3 3
684#define LFHCR4 4
685#define LFHCR5 5
686#define LFHCR6 6
687
688#define LFIDC _SFR_MEM16(0x84)
689
690#define LFIDCL _SFR_MEM8(0x84)
691#define LFIDCL_0 0
692#define LFIDCL_1 1
693#define LFIDCL_2 2
694#define LFIDCL_3 3
695#define LFIDCL_4 4
696#define LFIDCL_5 5
697#define LFIDCL_6 6
698#define LFIDCL_7 7
699
700#define LFIDCH _SFR_MEM8(0x85)
701#define LFIDCH_8 0
702#define LFIDCH_9 1
703#define LFIDCH_10 2
704#define LFIDCH_11 3
705#define LFIDCH_12 4
706#define LFIDCH_13 5
707#define LFIDCH_14 6
708#define LFIDCH_15 7
709
710#define LFCAL _SFR_MEM16(0x86)
711
712#define LFCALL _SFR_MEM8(0x86)
713#define LFCAL_00 0
714#define LFCAL_01 1
715#define LFCAL_02 2
716#define LFCAL_03 3
717#define LFCAL_04 4
718#define LFCAL_05 5
719#define LFCAL_06 6
720#define LFCAL_07 7
721
722#define LFCALH _SFR_MEM8(0x87)
723#define LFCAL_08 0
724#define LFCAL_09 1
725#define LFCAL_10 2
726#define LFCAL_11 3
727#define LFCAL_12 4
728#define LFCAL_13 5
729#define LFCAL_14 6
730#define LFCAL_15 7
731
732
733/* Interrupt vectors */
734/* Vector 0 is the reset vector */
735#define INT0_vect_num  1
736#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
737#define INT1_vect_num  2
738#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
739#define PCINT0_vect_num  3
740#define PCINT0_vect      _VECTOR(3)  /* Pin Change Interrupt Request 0 */
741#define PCINT1_vect_num  4
742#define PCINT1_vect      _VECTOR(4)  /* Pin Change Interrupt Request 1 */
743#define PCINT2_vect_num  5
744#define PCINT2_vect      _VECTOR(5)  /* Pin Change Interrupt Request 2 */
745#define INTVM_vect_num  6
746#define INTVM_vect      _VECTOR(6)  /* Voltage Monitor Interrupt */
747#define SENINT_vect_num  7
748#define SENINT_vect      _VECTOR(7)  /* Sensor Interface Interrupt */
749#define INTT0_vect_num  8
750#define INTT0_vect      _VECTOR(8)  /* Timer0 Interval Interrupt */
751#define LFWP_vect_num  9
752#define LFWP_vect      _VECTOR(9)  /* LF-Receiver Wake-up Interrupt */
753#define T3CAP_vect_num  10
754#define T3CAP_vect      _VECTOR(10)  /* Timer/Counter3 Capture Event */
755#define T3COMA_vect_num  11
756#define T3COMA_vect      _VECTOR(11)  /* Timer/Counter3 Compare Match A */
757#define T3COMB_vect_num  12
758#define T3COMB_vect      _VECTOR(12)  /* Timer/Counter3 Compare Match B */
759#define T3OVF_vect_num  13
760#define T3OVF_vect      _VECTOR(13)  /* Timer/Counter3 Overflow */
761#define T2CAP_vect_num  14
762#define T2CAP_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
763#define T2COM_vect_num  15
764#define T2COM_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match */
765#define T2OVF_vect_num  16
766#define T2OVF_vect      _VECTOR(16)  /* Timer/Counter2 Overflow */
767#define SPISTC_vect_num  17
768#define SPISTC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
769#define LFRXB_vect_num  18
770#define LFRXB_vect      _VECTOR(18)  /* LF Receive Buffer Interrupt */
771#define INTT1_vect_num  19
772#define INTT1_vect      _VECTOR(19)  /* Timer1 Interval Interrupt */
773#define T2RXB_vect_num  20
774#define T2RXB_vect      _VECTOR(20)  /* Timer2 SSI Receive Buffer Interrupt */
775#define T2TXB_vect_num  21
776#define T2TXB_vect      _VECTOR(21)  /* Timer2 SSI Transmit Buffer Interrupt */
777#define T2TXC_vect_num  22
778#define T2TXC_vect      _VECTOR(22)  /* Timer2 SSI Transmit Complete Interrupt */
779#define LFREOB_vect_num  23
780#define LFREOB_vect      _VECTOR(23)  /* LF-Receiver End of Burst Interrupt */
781#define EXCM_vect_num  24
782#define EXCM_vect      _VECTOR(24)  /* External Input Clock break down Interrupt */
783#define EEREADY_vect_num  25
784#define EEREADY_vect      _VECTOR(25)  /* EEPROM Ready Interrupt */
785#define SPM_RDY_vect_num  26
786#define SPM_RDY_vect      _VECTOR(26)  /* Store Program Memory Ready */
787
788#define _VECTOR_SIZE 2 /* Size of individual vector. */
789#define _VECTORS_SIZE (27 * _VECTOR_SIZE)
790
791
792/* Constants */
793#define SPM_PAGESIZE (64)
794#define RAMSTART     (0x100)
795#define RAMSIZE      (512)
796#define RAMEND       (RAMSTART + RAMSIZE - 1)
797#define XRAMSTART    (NA)
798#define XRAMSIZE     (0)
799#define XRAMEND      RAMEND
800#define E2END        (320 - 1)
801#define E2PAGESIZE   (4)
802#define FLASHEND     (8192 - 1)
803
804
805/* Fuses */
806#define FUSE_MEMORY_SIZE 2
807
808/* Low Fuse Byte */
809#define FUSE_TSRDI ~_BV(0)  /* Disable Temperature shutdown Reset  */
810#define FUSE_BODEN ~_BV(1)  /* Enable Brown-out detection */
811#define FUSE_FRCFS ~_BV(2)  /* Fast RC-Oscillator Frequency select */
812#define FUSE_WDRCON ~_BV(3)  /* Enable Watchdog RC-Oscillator */
813#define FUSE_SUT0 ~_BV(4)  /* Select start-up time */
814#define FUSE_SUT1 ~_BV(5)  /* Select start-up time */
815#define FUSE_CKOUT ~_BV(6)  /* Clock output */
816#define FUSE_CKDIV8 ~_BV(7)  /* Divide clock by 8 */
817#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN)
818
819/* High Fuse Byte */
820#define FUSE_BOOTRST ~_BV(0)  /* Select reset vector */
821#define FUSE_BOOTSZ0 ~_BV(1)  /* Boot size select */
822#define FUSE_BOOTSZ1 ~_BV(2)  /* Boot size select */
823#define FUSE_EESAVE ~_BV(3)  /* EEPROM memory is preserved through chip erase */
824#define FUSE_WDTON ~_BV(4)  /* Watchdog Timer Always On */
825#define FUSE_SPIEN ~_BV(5)  /* Enable Serial programming and Data Downloading */
826#define FUSE_DWEN ~_BV(6)  /* debugWIRE Enable */
827#define FUSE_EELOCK ~_BV(7)  /* Upper EEPROM Locked (disabled) */
828#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
829
830
831/* Lock Bits */
832#define __LOCK_BITS_EXIST
833#define __BOOT_LOCK_BITS_0_EXIST
834#define __BOOT_LOCK_BITS_1_EXIST
835
836
837/* Signature */
838#define SIGNATURE_0 0x1E
839#define SIGNATURE_1 0x93
840#define SIGNATURE_2 0x82
841
842
843#endif /* _AVR_ATA6289_H_ */
844
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