source: rtems/cpukit/score/cpu/avr/avr/io90pwmx.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 42.2 KB
Line 
1/* Copyright (c) 2005, Andrey Pashchenko
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */
34
35#ifndef _AVR_IO90PWMX_H_
36#define _AVR_IO90PWMX_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "io90pwmX.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* Port B Input Pins Address */
53#define PINB    _SFR_IO8(0x03)
54/* PINB */
55#define PINB7   7
56#define PINB6   6
57#define PINB5   5
58#define PINB4   4
59#define PINB3   3
60#define PINB2   2
61#define PINB1   1
62#define PINB0   0
63
64/* Port B Data Direction Register */
65#define DDRB    _SFR_IO8(0x04)
66/* DDRB */
67#define DDB7    7
68#define DDB6    6
69#define DDB5    5
70#define DDB4    4
71#define DDB3    3
72#define DDB2    2
73#define DDB1    1
74#define DDB0    0
75
76/* Port B Data Register */
77#define PORTB   _SFR_IO8(0x05)
78/* PORTB */
79#define PB7     7
80#define PB6     6
81#define PB5     5
82#define PB4     4
83#define PB3     3
84#define PB2     2
85#define PB1     1
86#define PB0     0
87
88/* Port C Input Pins Address */
89#define PINC    _SFR_IO8(0x06)
90/* PINC */
91#define PINC7   7
92#define PINC6   6
93#define PINC5   5
94#define PINC4   4
95#define PINC3   3
96#define PINC2   2
97#define PINC1   1
98#define PINC0   0
99
100/* Port C Data Direction Register */
101#define DDRC    _SFR_IO8(0x07)
102/* DDRC */
103#define DDC7    7
104#define DDC6    6
105#define DDC5    5
106#define DDC4    4
107#define DDC3    3
108#define DDC2    2
109#define DDC1    1
110#define DDC0    0
111
112/* Port C Data Register */
113#define PORTC   _SFR_IO8(0x08)
114/* PORTC */
115#define PC7     7
116#define PC6     6
117#define PC5     5
118#define PC4     4
119#define PC3     3
120#define PC2     2
121#define PC1     1
122#define PC0     0
123
124/* Port D Input Pins Address */
125#define PIND    _SFR_IO8(0x09)
126/* PIND */
127#define PIND7   7
128#define PIND6   6
129#define PIND5   5
130#define PIND4   4
131#define PIND3   3
132#define PIND2   2
133#define PIND1   1
134#define PIND0   0
135
136/* Port D Data Direction Register */
137#define DDRD    _SFR_IO8(0x0A)
138/* DDRD */
139#define DDD7    7
140#define DDD6    6
141#define DDD5    5
142#define DDD4    4
143#define DDD3    3
144#define DDD2    2
145#define DDD1    1
146#define DDD0    0
147
148/* Port D Data Register */
149#define PORTD   _SFR_IO8(0x0B)
150/* PORTD */
151#define PD7     7
152#define PD6     6
153#define PD5     5
154#define PD4     4
155#define PD3     3
156#define PD2     2
157#define PD1     1
158#define PD0     0
159
160/* Port E Input Pins Address */
161#define PINE    _SFR_IO8(0x0C)
162/* PINE */
163#define PINE2   2
164#define PINE1   1
165#define PINE0   0
166
167/* Port E Data Direction Register */
168#define DDRE    _SFR_IO8(0x0D)
169/* DDRE */
170#define DDE2    2
171#define DDE1    1
172#define DDE0    0
173
174/* Port E Data Register */
175#define PORTE   _SFR_IO8(0x0E)
176/* PORTE */
177#define PE2     2
178#define PE1     1
179#define PE0     0
180
181/* Timer/Counter 0 Interrupt Flag Register */
182#define TIFR0   _SFR_IO8(0x15)
183/* TIFR0 */
184#define OCF0B   2   /* Output Compare Flag 0B */
185#define OCF0A   1   /* Output Compare Flag 0A */
186#define TOV0    0   /* Overflow Flag */
187
188/* Timer/Counter1 Interrupt Flag Register */
189#define TIFR1   _SFR_IO8(0x16)
190/* TIFR1 */
191#define ICF1    5   /* Input Capture Flag 1 */
192#define OCF1B   2   /* Output Compare Flag 1B*/
193#define OCF1A   1   /* Output Compare Flag 1A*/
194#define TOV1    0   /* Overflow Flag */
195
196/* General Purpose I/O Register 1 */
197#define GPIOR1  _SFR_IO8(0x19)
198/* GPIOR1 */
199#define GPIOR17 7
200#define GPIOR16 6
201#define GPIOR15 5
202#define GPIOR14 4
203#define GPIOR13 3
204#define GPIOR12 2
205#define GPIOR11 1
206#define GPIOR10 0
207
208/* General Purpose I/O Register 2 */
209#define GPIOR2  _SFR_IO8(0x1A)
210/* GPIOR2 */
211#define GPIOR27 7
212#define GPIOR26 6
213#define GPIOR25 5
214#define GPIOR24 4
215#define GPIOR23 3
216#define GPIOR22 2
217#define GPIOR21 1
218#define GPIOR20 0
219
220/* General Purpose I/O Register 3 */
221#define GPIOR3  _SFR_IO8(0x1B)
222/* GPIOR3 */
223#define GPIOR37 7
224#define GPIOR36 6
225#define GPIOR35 5
226#define GPIOR34 4
227#define GPIOR33 3
228#define GPIOR32 2
229#define GPIOR31 1
230#define GPIOR30 0
231
232/* External Interrupt Flag Register */
233#define EIFR    _SFR_IO8(0x1C)
234/* EIFR */
235#define INTF3   3
236#define INTF2   2
237#define INTF1   1
238#define INTF0   0
239
240/* External Interrupt Mask Register */
241#define EIMSK   _SFR_IO8(0x1D)
242/* EIMSK */
243#define INT3    3   /* External Interrupt Request 3 Enable */
244#define INT2    2   /* External Interrupt Request 2 Enable */
245#define INT1    1   /* External Interrupt Request 1 Enable */
246#define INT0    0   /* External Interrupt Request 0 Enable */
247
248/* General Purpose I/O Register 0 */
249#define GPIOR0  _SFR_IO8(0x1E)
250/* GPIOR0 */
251#define GPIOR07 7
252#define GPIOR06 6
253#define GPIOR05 5
254#define GPIOR04 4
255#define GPIOR03 3
256#define GPIOR02 2
257#define GPIOR01 1
258#define GPIOR00 0
259
260/* EEPROM Control Register */
261#define EECR    _SFR_IO8(0x1F)
262/* EECR */
263#define EERIE   3   /* EEPROM Ready Interrupt Enable */
264#define EEMWE   2   /* EEPROM Master Write Enable */
265#define EEWE    1   /* EEPROM Write Enable */
266#define EERE    0   /* EEPROM Read Enable */
267
268/* EEPROM Data Register */
269#define EEDR    _SFR_IO8(0x20)
270/* EEDR */
271#define EEDR7   7
272#define EEDR6   6
273#define EEDR5   5
274#define EEDR4   4
275#define EEDR3   3
276#define EEDR2   2
277#define EEDR1   1
278#define EEDR0   0
279
280/* The EEPROM Address Registers */
281#define EEAR    _SFR_IO16(0x21)
282#define EEARL   _SFR_IO8(0x21)
283#define EEARH   _SFR_IO8(0x22)
284/* EEARH */
285#define EEAR11  3
286#define EEAR10  2
287#define EEAR9   1
288#define EEAR8   0
289/* EEARL */
290#define EEAR7   7
291#define EEAR6   6
292#define EEAR5   5
293#define EEAR4   4
294#define EEAR3   3
295#define EEAR2   2
296#define EEAR1   1
297#define EEAR0   0
298
299/* 6-char sequence denoting where to find the EEPROM registers in memory space.
300   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
301   subroutines.
302   First two letters:  EECR address.
303   Second two letters: EEDR address.
304   Last two letters:   EEAR address.  */
305#define __EEPROM_REG_LOCATIONS__ 1F2021
306
307/* General Timer/Counter Control Register */
308#define GTCCR   _SFR_IO8(0x23)
309/* GTCCR */
310#define TSM     7   /* Timer/Counter Synchronization Mode */
311#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
312#define PSR10   0   /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
313
314/* Timer/Counter Control Register A */
315#define TCCR0A  _SFR_IO8(0x24)
316/* TCCR0A */
317#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
318#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
319#define COM0B1  5   /* Compare Output Mode, Fast PWm */
320#define COM0B0  4   /* Compare Output Mode, Fast PWm */
321#define WGM01   1   /* Waveform Generation Mode */
322#define WGM00   0   /* Waveform Generation Mode */
323
324/* Timer/Counter Control Register B */
325#define TCCR0B  _SFR_IO8(0x25)
326/* TCCR0B */
327#define FOC0A   7   /* Force Output Compare A */
328#define FOC0B   6   /* Force Output Compare B */
329#define WGM02   3   /* Waveform Generation Mode */
330#define CS02    2   /* Clock Select */
331#define CS01    1   /* Clock Select */
332#define CS00    0   /* Clock Select */
333
334/* Timer/Counter0 Register */
335#define TCNT0   _SFR_IO8(0x26)
336/* TCNT0 */
337#define TCNT07  7
338#define TCNT06  6
339#define TCNT05  5
340#define TCNT04  4
341#define TCNT03  3
342#define TCNT02  2
343#define TCNT01  1
344#define TCNT00  0
345
346/* Timer/Counter0 Output Compare Register A */
347#define OCR0A   _SFR_IO8(0x27)
348/* OCR0A */
349#define OCR0A7  7
350#define OCR0A6  6
351#define OCR0A5  5
352#define OCR0A4  4
353#define OCR0A3  3
354#define OCR0A2  2
355#define OCR0A1  1
356#define OCR0A0  0
357
358/* Timer/Counter0 Output Compare Register B */
359#define OCR0B   _SFR_IO8(0x28)
360/* OCR0B */
361#define OCR0B7  7
362#define OCR0B6  6
363#define OCR0B5  5
364#define OCR0B4  4
365#define OCR0B3  3
366#define OCR0B2  2
367#define OCR0B1  1
368#define OCR0B0  0
369
370/* PLL Control and Status Register */
371#define PLLCSR  _SFR_IO8(0x29)
372/* PLLCSR */
373#define PCKE    2   /* PCK Enable */
374/* Bit 2 has been renamed in later versions of the datasheet. */
375#define PLLF    2   /* PLL Factor */
376#define PLLE    1   /* PLL Enable */
377#define PLOCK   0   /* PLL Lock Detector */
378
379/* SPI Control Register */
380#define SPCR    _SFR_IO8(0x2C)
381/* SPCR */
382#define SPIE    7   /* SPI Interrupt Enable */
383#define SPE     6   /* SPI Enable */
384#define DORD    5   /* Data Order */
385#define MSTR    4   /* Master/Slave Select */
386#define CPOL    3   /* Clock polarity */
387#define CPHA    2   /* Clock Phase */
388#define SPR1    1   /* SPI Clock Rate Select 1 */
389#define SPR0    0   /* SPI Clock Rate Select 0 */
390
391/* SPI Status Register */
392#define SPSR    _SFR_IO8(0x2D)
393/* SPSR */
394#define SPIF    7   /* SPI Interrupt Flag */
395#define WCOL    6   /* Write Collision Flag */
396#define SPI2X   0   /* Double SPI Speed Bit */
397
398/* SPI Data Register */
399#define SPDR    _SFR_IO8(0x2E)
400/* SPDR */
401#define SPD7    7
402#define SPD6    6
403#define SPD5    5
404#define SPD4    4
405#define SPD3    3
406#define SPD2    2
407#define SPD1    1
408#define SPD0    0
409
410/* Analog Comparator Status Register */
411#define ACSR    _SFR_IO8(0x30)
412/* ACSR */
413#define ACCKDIV 7   /* Analog Comparator Clock Divider */
414#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
415#define AC1IF   5   /* Analog Comparator 1 Interrupt Flag Bit */
416#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
417#define AC2O    2   /* Analog Comparator 2 Output Bit */
418#define AC1O    1   /* Analog Comparator 1 Output Bit */
419#define AC0O    0   /* Analog Comparator 0 Output Bit */
420
421/* Monitor Data Register */
422#define MONDR   _SFR_IO8(0x31)
423
424/* Monitor Stop Mode Control Register */
425#define MSMCR   _SFR_IO8(0x32)
426
427/* Sleep Mode Control Register */
428#define SMCR    _SFR_IO8(0x33)
429/* SMCR */
430#define SM2     3   /* Sleep Mode Select bit2 */
431#define SM1     2   /* Sleep Mode Select bit1 */
432#define SM0     1   /* Sleep Mode Select bit0 */
433#define SE      0   /* Sleep Enable */
434
435/* MCU Status Register */
436#define MCUSR   _SFR_IO8(0x34)
437/* MCUSR */
438#define WDRF    3   /* Watchdog Reset Flag */
439#define BORF    2   /* Brown-out Reset Flag */
440#define EXTRF   1   /* External Reset Flag */
441#define PORF    0   /* Power-on reset flag */
442
443/* MCU Control Register */
444#define MCUCR   _SFR_IO8(0x35)
445/* MCUCR */
446#define SPIPS   7   /* SPI Pin Select */
447#define PUD     4   /* Pull-up disable */
448#define IVSEL   1   /* Interrupt Vector Select */
449#define IVCE    0   /* Interrupt Vector Change Enable */
450
451/* Store Program Memory Control Register */
452#define SPMCSR  _SFR_IO8(0x37)
453/* SPMCSR */
454#define SPMIE   7   /* SPM Interrupt Enable */
455#define RWWSB   6   /* Read While Write Section Busy */
456#define RWWSRE  4   /* Read While Write section read enable */
457#define BLBSET  3   /* Boot Lock Bit Set */
458#define PGWRT   2   /* Page Write */
459#define PGERS   1   /* Page Erase */
460#define SPMEN   0   /* Store Program Memory Enable */
461
462/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
463/* 0x3F SREG      [defined in <avr/io.h>] */
464
465/* Watchdog Timer Control Register */
466#define WDTCSR  _SFR_MEM8(0x60)
467/* WDTCSR */
468#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
469#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
470#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
471#define WDCE    4   /* Watchdog Change Enable */
472#define WDE     3   /* Watchdog Enable */
473#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
474#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
475#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
476
477/* Clock Prescaler Register */
478#define CLKPR   _SFR_MEM8(0x61)
479/* CLKPR */
480#define CLKPCE  7   /* Clock Prescaler Change Enable */
481#define CLKPS3  3   /* Clock Prescaler Select bit3 */
482#define CLKPS2  2   /* Clock Prescaler Select bit2 */
483#define CLKPS1  1   /* Clock Prescaler Select bit1 */
484#define CLKPS0  0   /* Clock Prescaler Select bit0 */
485
486/* Power Reduction Register */
487#define PRR     _SFR_MEM8(0x64)
488/* PRR */
489#define PRPSC2  7   /* Power Reduction PSC2 */
490#define PRPSC1  6   /* Power Reduction PSC1 */
491#define PRPSC0  5   /* Power Reduction PSC0 */
492#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
493#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
494#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
495#define PRUSART 1   /* Power Reduction USART */
496#define PRADC   0   /* Power Reduction ADC */
497
498/* Oscillator Calibration Value */
499#define OSCCAL  _SFR_MEM8(0x66)
500/* OSCCAL */
501#define CAL6    6
502#define CAL5    5
503#define CAL4    4
504#define CAL3    3
505#define CAL2    2
506#define CAL1    1
507#define CAL0    0
508
509/* External Interrupt Control Register A */
510#define EICRA   _SFR_MEM8(0x69)
511/* EICRA */
512#define ISC31   7
513#define ISC30   6
514#define ISC21   5
515#define ISC20   4
516#define ISC11   3
517#define ISC10   2
518#define ISC01   1
519#define ISC00   0
520
521/* Timer/Counter0 Interrupt Mask Register */
522#define TIMSK0  _SFR_MEM8(0x6E)
523/* TIMSK0 */
524#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
525#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
526#define TOIE0   0   /* Overflow Interrupt Enable */
527
528/* Timer/Counter1 Interrupt Mask Register */
529#define TIMSK1  _SFR_MEM8(0x6F)
530/* TIMSK1 */
531#define ICIE1   5   /* Input Capture Interrupt Enable */
532#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
533#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
534#define TOIE1   0   /* Overflow Interrupt Enable */
535
536/* Amplifier 0 Control and Status register */
537#define AMP0CSR _SFR_MEM8(0x76)
538#define AMP0EN  7
539#define AMP0IS  6
540#define AMP0G1  5
541#define AMP0G0  4
542#define AMP0TS1 1
543#define AMP0TS0 0
544
545/* Amplifier 1 Control and Status register */
546#define AMP1CSR _SFR_MEM8(0x77)
547#define AMP1EN  7
548#define AMP1IS  6
549#define AMP1G1  5
550#define AMP1G0  4
551#define AMP1TS1 1
552#define AMP1TS0 0
553
554/* ADC Result Data Register */
555#ifndef __ASSEMBLER__
556#define ADC     _SFR_MEM16(0x78)
557#endif
558#define ADCW    _SFR_MEM16(0x78)
559#define ADCL    _SFR_MEM8(0x78)
560#define ADCH    _SFR_MEM8(0x79)
561
562/* ADC Control and Status Register A */
563#define ADCSRA  _SFR_MEM8(0x7A)
564/* ADCSRA */
565#define ADEN    7   /* ADC Enable */
566#define ADSC    6   /* ADC Start Conversion */
567#define ADATE   5   /* ADC Auto Trigger Enable */
568#define ADIF    4   /* ADC Interrupt Flag */
569#define ADIE    3   /* ADC Interrupt Enable */
570#define ADPS2   2   /* ADC Prescaler Select bit2 */
571#define ADPS1   1   /* ADC Prescaler Select bit1 */
572#define ADPS0   0   /* ADC Prescaler Select bit0 */
573
574/* ADC Control and Status Register B */
575#define ADCSRB  _SFR_MEM8(0x7B)
576/* ADCSRB */
577#define ADHSM   7   /* ADC High Speed Mode */
578#define ADASCR  4
579#define ADTS3   3   /* ADC Auto Trigger Source 3 */
580#define ADTS2   2   /* ADC Auto Trigger Source 2 */
581#define ADTS1   1   /* ADC Auto Trigger Source 1 */
582#define ADTS0   0   /* ADC Auto Trigger Source 0 */
583
584/* ADC multiplexer Selection Register */
585#define ADMUX   _SFR_MEM8(0x7C)
586/* ADMUX */
587#define REFS1   7   /* Reference Selection bit1 */
588#define REFS0   6   /* Reference Selection bit0 */
589#define ADLAR   5   /* Left Adjust Result */
590#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
591#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
592#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
593#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
594
595/* Digital Input Disable Register 0 */
596#define DIDR0   _SFR_MEM8(0x7E)
597/* DIDR0 */
598#define ADC7D   7   /* ADC7 Digital input Disable */
599#define ADC6D   6   /* ADC6 Digital input Disable */
600#define ADC5D   5   /* ADC5 Digital input Disable */
601#define ADC4D   4   /* ADC4 Digital input Disable */
602#define ADC3D   3   /* ADC3 Digital input Disable */
603#define ADC2D   2   /* ADC2 Digital input Disable */
604#define ADC1D   1   /* ADC1 Digital input Disable */
605#define ADC0D   0   /* ADC0 Digital input Disable */
606
607/* Digital Input Disable Register 1 */
608#define DIDR1   _SFR_MEM8(0x7F)
609/* DIDR1 */
610#define ACMP0D  5
611#define AMP0PD  4
612#define AMP0ND  3
613#define ADC10D  2   /* ADC10 Digital input Disable */
614#define ADC9D   1   /* ADC9 Digital input Disable */
615#define ADC8D   0   /* ADC8 Digital input Disable */
616
617/* Timer/Counter1 Control Register A */
618#define TCCR1A  _SFR_MEM8(0x80)
619/* TCCR1A */
620#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
621#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
622#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
623#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
624#define WGM11   1   /* Waveform Generation Mode */
625#define WGM10   0   /* Waveform Generation Mode */
626
627/* Timer/Counter1 Control Register B */
628#define TCCR1B  _SFR_MEM8(0x81)
629/* TCCR1B */
630#define ICNC1   7   /* Input Capture 1 Noise Canceler */
631#define ICES1   6   /* Input Capture 1 Edge Select */
632#define WGM13   4   /* Waveform Generation Mode */
633#define WGM12   3   /* Waveform Generation Mode */
634#define CS12    2   /* Prescaler source of Timer/Counter 1 */
635#define CS11    1   /* Prescaler source of Timer/Counter 1 */
636#define CS10    0   /* Prescaler source of Timer/Counter 1 */
637
638/* Timer/Counter1 Control Register C */
639#define TCCR1C  _SFR_MEM8(0x82)
640/* TCCR1C */
641#define FOC1A   7   /* Force Output Compare for Channel A */
642#define FOC1B   6   /* Force Output Compare for Channel B */
643
644/* Timer/Counter1 */
645#define TCNT1   _SFR_MEM16(0x84)
646#define TCNT1L  _SFR_MEM8(0x84)
647#define TCNT1H  _SFR_MEM8(0x85)
648/* TCNT1H */
649#define TCNT115 7
650#define TCNT114 6
651#define TCNT113 5
652#define TCNT112 4
653#define TCNT111 3
654#define TCNT110 2
655#define TCNT19  1
656#define TCNT18  0
657/* TCNT1L */
658#define TCNT17  7
659#define TCNT16  6
660#define TCNT15  5
661#define TCNT14  4
662#define TCNT13  3
663#define TCNT12  2
664#define TCNT11  1
665#define TCNT10  0
666
667/* Input Capture Register 1 */
668#define ICR1    _SFR_MEM16(0x86)
669#define ICR1L   _SFR_MEM8(0x86)
670#define ICR1H   _SFR_MEM8(0x87)
671/* ICR1H */
672#define ICR115  7
673#define ICR114  6
674#define ICR113  5
675#define ICR112  4
676#define ICR111  3
677#define ICR110  2
678#define ICR19   1
679#define ICR18   0
680/* ICR1L */
681#define ICR17   7
682#define ICR16   6
683#define ICR15   5
684#define ICR14   4
685#define ICR13   3
686#define ICR12   2
687#define ICR11   1
688#define ICR10   0
689
690/* Output Compare Register 1 A */
691#define OCR1A   _SFR_MEM16(0x88)
692#define OCR1AL  _SFR_MEM8(0x88)
693#define OCR1AH  _SFR_MEM8(0x89)
694/* OCR1AH */
695#define OCR1A15 7
696#define OCR1A14 6
697#define OCR1A13 5
698#define OCR1A12 4
699#define OCR1A11 3
700#define OCR1A10 2
701#define OCR1A9  1
702#define OCR1A8  0
703/* OCR1AL */
704#define OCR1A7  7
705#define OCR1A6  6
706#define OCR1A5  5
707#define OCR1A4  4
708#define OCR1A3  3
709#define OCR1A2  2
710#define OCR1A1  1
711#define OCR1A0  0
712
713/* Output Compare Register 1 B */
714#define OCR1B   _SFR_MEM16(0x8A)
715#define OCR1BL  _SFR_MEM8(0x8A)
716#define OCR1BH  _SFR_MEM8(0x8B)
717/* OCR1BH */
718#define OCR1B15 7
719#define OCR1B14 6
720#define OCR1B13 5
721#define OCR1B12 4
722#define OCR1B11 3
723#define OCR1B10 2
724#define OCR1B9  1
725#define OCR1B8  0
726/* OCR1BL */
727#define OCR1B7  7
728#define OCR1B6  6
729#define OCR1B5  5
730#define OCR1B4  4
731#define OCR1B3  3
732#define OCR1B2  2
733#define OCR1B1  1
734#define OCR1B0  0
735
736/* PSC0 Interrupt Flag Register */
737#define PIFR0   _SFR_MEM8(0xA0)
738/* PIFR0 */
739#define POAC0B  7   /* PSC0 Output B Activity */
740#define POAC0A  6   /* PSC0 Output A Activity */
741#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
742#define PEV0B   4   /* PSC0 External Event B Interrupt */
743#define PEV0A   3   /* PSC0 External Event A Interrupt */
744#define PRN01   2   /* PSC0 Ramp Number bit1 */
745#define PRN00   1   /* PSC0 Ramp Number bit0 */
746#define PEOP0   0   /* End Of PSC0 Interrupt */
747
748/* PSC0 Interrupt Mask Register */
749#define PIM0    _SFR_MEM8(0xA1)
750/* PIM0 */
751#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
752#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
753#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
754#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
755
756/* PSC1 Interrupt Flag Register */
757#define PIFR1   _SFR_MEM8(0xA2)
758/* PIFR1 */
759#define POAC1B  7   /* PSC1 Output B Activity */
760#define POAC1A  6   /* PSC1 Output A Activity */
761#define PSEI1   5   /* PSC1 Synchro Error Interrupt */
762#define PEV1B   4   /* PSC1 External Event B Interrupt */
763#define PEV1A   3   /* PSC1 External Event A Interrupt */
764#define PRN11   2   /* PSC1 Ramp Number bit1 */
765#define PRN10   1   /* PSC1 Ramp Number bit0 */
766#define PEOP1   0   /* End Of PSC1 Interrupt */
767
768/* PSC1 Interrupt Mask Register */
769#define PIM1    _SFR_MEM8(0xA3)
770/* PIM1 */
771#define PSEIE1  5   /* PSC1 Synchro Error Interrupt Enable */
772#define PEVE1B  4   /* PSC1 External Event B Interrupt Enable */
773#define PEVE1A  3   /* PSC1 External Event A Interrupt Enable */
774#define PEOPE1  0   /* PSC1 End Of Cycle Interrupt Enable */
775
776/* PSC2 Interrupt Flag Register */
777#define PIFR2   _SFR_MEM8(0xA4)
778/* PIFR2 */
779#define POAC2B  7   /* PSC2 Output B Activity */
780#define POAC2A  6   /* PSC2 Output A Activity */
781#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
782#define PEV2B   4   /* PSC2 External Event B Interrupt */
783#define PEV2A   3   /* PSC2 External Event A Interrupt */
784#define PRN21   2   /* PSC2 Ramp Number bit1 */
785#define PRN20   1   /* PSC2 Ramp Number bit0 */
786#define PEOP2   0   /* End Of PSC2 Interrupt */
787
788/* PSC2 Interrupt Mask Register */
789#define PIM2    _SFR_MEM8(0xA5)
790/* PIM2 */
791#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
792#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
793#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
794#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
795
796/* Digital to Analog Conversion Control Register */
797#define DACON   _SFR_MEM8(0xAA)
798/* DACON */
799#define DAATE   7   /* DAC Auto Trigger Enable bit */
800#define DATS2   6   /* DAC Trigger Selection bit2 */
801#define DATS1   5   /* DAC Trigger Selection bit1 */
802#define DATS0   4   /* DAC Trigger Selection bit0 */
803#define DALA    2   /* Digital to Analog Left Adjust */
804#define DAOE    1   /* Digital to Analog Output Enable bit */
805#define DAEN    0   /* Digital to Analog Enable bit */
806
807/* Digital to Analog Converter input Register */
808#define DAC     _SFR_MEM16(0xAB)
809#define DACL    _SFR_MEM8(0xAB)
810#define DACH    _SFR_MEM8(0xAC)
811
812/* Analog Comparator 0 Control Register */
813#define AC0CON  _SFR_MEM8(0xAD)
814/* AC0CON */
815#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
816#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
817#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
818#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
819#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
820#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
821#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
822
823/* Analog Comparator 1 Control Register */
824#define AC1CON  _SFR_MEM8(0xAE)
825/* AC1CON */
826#define AC1EN   7   /* Analog Comparator 1 Enable Bit */
827#define AC1IE   6   /* Analog Comparator 1 Interrupt Enable bit */
828#define AC1IS1  5   /* Analog Comparator 1 Interrupt Select bit1 */
829#define AC1IS0  4   /* Analog Comparator 1 Interrupt Select bit0 */
830#define AC1ICE  3   /* Analog Comparator 1 Interrupt Capture Enable bit */
831#define AC1M2   2   /* Analog Comparator 1 Multiplexer register bit2 */
832#define AC1M1   1   /* Analog Comparator 1 Multiplexer register bit1 */
833#define AC1M0   0   /* Analog Comparator 1 Multiplexer register bit0 */
834
835/* Analog Comparator 2 Control Register */
836#define AC2CON  _SFR_MEM8(0xAF)
837/* AC2CON */
838#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
839#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
840#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
841#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
842#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
843#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
844#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
845
846/* USART Control and Status Register A */
847#define UCSRA   _SFR_MEM8(0xC0)
848/* UCSRA */
849#define RXC     7   /* USART Receive Complete */
850#define TXC     6   /* USART Transmit Complete */
851#define UDRE    5   /* USART Data Register Empty */
852#define FE      4   /* Frame Error */
853#define DOR     3   /* Data OverRun */
854#define UPE     2   /* USART Parity Error */
855#define U2X     1   /* Double the USART Transmission Speed */
856#define MPCM    0   /* Multi-processor Communication Mode */
857
858/* USART Control and Status Register B */
859#define UCSRB   _SFR_MEM8(0xC1)
860/* UCSRB */
861#define RXCIE   7   /* RX Complete Interrupt Enable */
862#define TXCIE   6   /* TX Complete Interrupt Enable */
863#define UDRIE   5   /* USART Data Register Empty Interrupt Enable */
864#define RXEN    4   /* Receiver Enable */
865#define TXEN    3   /* Transmitter Enable */
866#define UCSZ2   2   /* Character Size */
867#define RXB8    1   /* Receive Data Bit 8 */
868#define TXB8    0   /* Transmit Data Bit 8 */
869
870/* USART Control and Status Register C */
871#define UCSRC   _SFR_MEM8(0xC2)
872/* UCSRC */
873#define UMSEL   6   /* USART Mode Select */
874#define UPM1    5   /* Parity Mode bit1 */
875#define UPM0    4   /* Parity Mode bit0 */
876#define USBS    3   /* Stop Bit Select */
877#define UCSZ1   2   /* Character Size bit1 */
878#define UCSZ0   1   /* Character Size bit0 */
879#define UCPOL   0   /* Clock Polarity */
880
881/* USART Baud Rate Register */
882#define UBRR    _SFR_MEM16(0xC4)
883#define UBRRL   _SFR_MEM8(0xC4)
884#define UBRRH   _SFR_MEM8(0xC5)
885
886/* USART I/O Data Register */
887#define UDR     _SFR_MEM8(0xC6)
888
889/* EUSART Control and Status Register A */
890#define EUCSRA  _SFR_MEM8(0xC8)
891/* EUCSRA */
892#define UTxS3   7   /* EUSART Transmit Character Size bit3 */
893#define UTxS2   6   /* EUSART Transmit Character Size bit2 */
894#define UTxS1   5   /* EUSART Transmit Character Size bit1 */
895#define UTxS0   4   /* EUSART Transmit Character Size bit0 */
896#define URxS3   3   /* EUSART Receive Character Size bit3 */
897#define URxS2   2   /* EUSART Receive Character Size bit2 */
898#define URxS1   1   /* EUSART Receive Character Size bit1 */
899#define URxS0   0   /* EUSART Receive Character Size bit0 */
900
901/* EUSART Control and Status Register B */
902#define EUCSRB  _SFR_MEM8(0xC9)
903/* EUCSRB */
904#define EUSART  4   /* EUSART Enable Bit */
905#define EUSBS   3   /* EUSBS Enable Bit */
906#define EMCH    1   /* Manchester mode */
907#define BODR    0   /* Bit Order */
908
909/* EUSART Control and Status Register C */
910#define EUCSRC  _SFR_MEM8(0xCA)
911/* EUCSRC */
912#define FEM     3   /* Frame Error Manchester */
913#define F1617   2
914#define STP1    1   /* Stop bits values bit1 */
915#define STP0    0   /* Stop bits values bit0 */
916
917/* Manchester receiver Baud Rate Registers */
918#define MUBRR   _SFR_MEM16(0xCC)
919#define MUBRRL  _SFR_MEM8(0xCC)
920#define MUBRRH  _SFR_MEM8(0xCD)
921
922/* EUSART I/O Data Register */
923#define EUDR    _SFR_MEM8(0xCE)
924
925/* PSC 0 Synchro and Output Configuration */
926#define PSOC0   _SFR_MEM8(0xD0)
927/* PSOC0 */
928#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
929#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
930#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
931#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
932
933/* Output Compare SA Registers */
934#define OCR0SA  _SFR_MEM16(0xD2)
935#define OCR0SAL _SFR_MEM8(0xD2)
936#define OCR0SAH _SFR_MEM8(0xD3)
937
938/* Output Compare RA Registers */
939#define OCR0RA  _SFR_MEM16(0xD4)
940#define OCR0RAL _SFR_MEM8(0xD4)
941#define OCR0RAH _SFR_MEM8(0xD5)
942
943/* Output Compare SB Registers */
944#define OCR0SB  _SFR_MEM16(0xD6)
945#define OCR0SBL _SFR_MEM8(0xD6)
946#define OCR0SBH _SFR_MEM8(0xD7)
947
948/* Output Compare RB Registers */
949#define OCR0RB  _SFR_MEM16(0xD8)
950#define OCR0RBL _SFR_MEM8(0xD8)
951#define OCR0RBH _SFR_MEM8(0xD9)
952
953/* PSC 0 Configuration Register */
954#define PCNF0   _SFR_MEM8(0xDA)
955/* PCNF0 */
956#define PFIFTY0  7  /* PSC 0 Fifty */
957#define PALOCK0  6  /* PSC 0 Autolock */
958#define PLOCK0   5  /* PSC 0 Lock */
959#define PMODE01  4  /* PSC 0 Mode bit1 */
960#define PMODE00  3  /* PSC 0 Mode bit0 */
961#define POP0     2  /* PSC 0 Output Polarity */
962#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
963
964/* PSC 0 Control Register */
965#define PCTL0   _SFR_MEM8(0xDB)
966/* PCTL0 */
967#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
968#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
969#define PBFM0   5   /* Balance Flank Width Modulation */
970#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
971#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
972#define PARUN0  2   /* PSC 0 Autorun */
973#define PCCYC0  1   /* PSC 0 Complete Cycle */
974#define PRUN0   0   /* PSC 0 Run */
975
976/* PSC 0 Input A Control Register */
977#define PFRC0A  _SFR_MEM8(0xDC)
978/* PFRC0A */
979#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
980#define PISEL0A 6   /* PSC 0 Input Select for Part A */
981#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
982#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
983#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
984#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
985#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
986#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
987
988/* PSC 0 Input B Control Register */
989#define PFRC0B  _SFR_MEM8(0xDD)
990/* PFRC0B */
991#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
992#define PISEL0B 6   /* PSC 0 Input Select for Part B */
993#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
994#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
995#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
996#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
997#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
998#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
999
1000/* PSC 0 Input Capture Registers */
1001#define PICR0   _SFR_MEM16(0xDE)
1002
1003#define PICR0L  _SFR_MEM8(0xDE)
1004
1005#define PICR0H  _SFR_MEM8(0xDF)
1006#define PCST0   7   /* PSC Capture Software Trig bit */
1007                    /* not implemented on AT90PWM2/AT90PWM3 */
1008
1009/* PSC 1 Synchro and Output Configuration */
1010#define PSOC1   _SFR_MEM8(0xE0)
1011/* PSOC1 */
1012#define PSYNC11 5   /* Synchronization Out for ADC Selection bit1 */
1013#define PSYNC10 4   /* Synchronization Out for ADC Selection bit0 */
1014#define POEN1B  2   /* PSC 1 OUT Part B Output Enable */
1015#define POEN1A  0   /* PSC 1 OUT Part A Output Enable */
1016
1017/* Output Compare SA Registers */
1018#define OCR1SA  _SFR_MEM16(0xE2)
1019#define OCR1SAL _SFR_MEM8(0xE2)
1020#define OCR1SAH _SFR_MEM8(0xE3)
1021
1022/* Output Compare RA Registers */
1023#define OCR1RA  _SFR_MEM16(0xE4)
1024#define OCR1RAL _SFR_MEM8(0xE4)
1025#define OCR1RAH _SFR_MEM8(0xE5)
1026
1027/* Output Compare SB Registers */
1028#define OCR1SB  _SFR_MEM16(0xE6)
1029#define OCR1SBL _SFR_MEM8(0xE6)
1030#define OCR1SBH _SFR_MEM8(0xE7)
1031
1032/* Output Compare RB Registers */
1033#define OCR1RB  _SFR_MEM16(0xE8)
1034#define OCR1RBL _SFR_MEM8(0xE8)
1035#define OCR1RBH _SFR_MEM8(0xE9)
1036
1037/* PSC 1 Configuration Register */
1038#define PCNF1   _SFR_MEM8(0xEA)
1039/* PCNF1 */
1040#define PFIFTY1  7  /* PSC 1 Fifty */
1041#define PALOCK1  6  /* PSC 1 Autolock */
1042#define PLOCK1   5  /* PSC 1 Lock */
1043#define PMODE11  4  /* PSC 1 Mode bit1 */
1044#define PMODE10  3  /* PSC 1 Mode bit0 */
1045#define POP1     2  /* PSC 1 Output Polarity */
1046#define PCLKSEL1 1  /* PSC 1 Input Clock Select */
1047
1048/* PSC 1 Control Register */
1049#define PCTL1   _SFR_MEM8(0xEB)
1050/* PCTL1 */
1051#define PPRE11  7   /* PSC 1 Prescaler Select bit1 */
1052#define PPRE10  6   /* PSC 1 Prescaler Select bit0 */
1053#define PBFM1   5   /* Balance Flank Width Modulation */
1054#define PAOC1B  4   /* PSC 1 Asynchronous Output Control B */
1055#define PAOC1A  3   /* PSC 1 Asynchronous Output Control A */
1056#define PARUN1  2   /* PSC 1 Autorun */
1057#define PCCYC1  1   /* PSC 1 Complete Cycle */
1058#define PRUN1   0   /* PSC 1 Run */
1059
1060/* PSC 1 Input A Control Register */
1061#define PFRC1A  _SFR_MEM8(0xEC)
1062/* PFRC1A */
1063#define PCAE1A  7   /* PSC 1 Capture Enable Input Part A */
1064#define PISEL1A 6   /* PSC 1 Input Select for Part A */
1065#define PELEV1A 5   /* PSC 1 Edge Level Selector of Input Part A */
1066#define PFLTE1A 4   /* PSC 1 Filter Enable on Input Part A */
1067#define PRFM1A3 3   /* PSC 1 Fault Mode bit3 */
1068#define PRFM1A2 2   /* PSC 1 Fault Mode bit2 */
1069#define PRFM1A1 1   /* PSC 1 Fault Mode bit1 */
1070#define PRFM1A0 0   /* PSC 1 Fault Mode bit0 */
1071
1072/* PSC 1 Input B Control Register */
1073#define PFRC1B  _SFR_MEM8(0xED)
1074/* PFRC1B */
1075#define PCAE1B  7   /* PSC 1 Capture Enable Input Part B */
1076#define PISEL1B 6   /* PSC 1 Input Select for Part B */
1077#define PELEV1B 5   /* PSC 1 Edge Level Selector of Input Part B */
1078#define PFLTE1B 4   /* PSC 1 Filter Enable on Input Part B */
1079#define PRFM1B3 3   /* PSC 1 Fault Mode bit3 */
1080#define PRFM1B2 2   /* PSC 1 Fault Mode bit2 */
1081#define PRFM1B1 1   /* PSC 1 Fault Mode bit1 */
1082#define PRFM1B0 0   /* PSC 1 Fault Mode bit0 */
1083
1084/* PSC 1 Input Capture Registers */
1085#define PICR1   _SFR_MEM16(0xEE)
1086
1087#define PICR1L  _SFR_MEM8(0xEE)
1088
1089#define PICR1H  _SFR_MEM8(0xEF)
1090#define PCST1   7   /* PSC Capture Software Trig bit */
1091                    /* not implemented on AT90PWM2/AT90PWM3 */
1092
1093/* PSC 2 Synchro and Output Configuration */
1094#define PSOC2   _SFR_MEM8(0xF0)
1095/* PSOC2 */
1096#define POS23   7   /* PSCOUT23 Selection */
1097#define POS22   6   /* PSCOUT22 Selection */
1098#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
1099#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
1100#define POEN2D  3   /* PSCOUT23 Output Enable */
1101#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
1102#define POEN2C  1   /* PSCOUT22 Output Enable */
1103#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
1104
1105/* PSC 2 Output Matrix */
1106#define POM2    _SFR_MEM8(0xF1)
1107/* POM2 */
1108#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
1109#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
1110#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
1111#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
1112#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
1113#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
1114#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
1115#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
1116
1117/* Output Compare SA Registers */
1118#define OCR2SA  _SFR_MEM16(0xF2)
1119#define OCR2SAL _SFR_MEM8(0xF2)
1120#define OCR2SAH _SFR_MEM8(0xF3)
1121
1122/* Output Compare RA Registers */
1123#define OCR2RA  _SFR_MEM16(0xF4)
1124#define OCR2RAL _SFR_MEM8(0xF4)
1125#define OCR2RAH _SFR_MEM8(0xF5)
1126
1127/* Output Compare SB Registers */
1128#define OCR2SB  _SFR_MEM16(0xF6)
1129#define OCR2SBL _SFR_MEM8(0xF6)
1130#define OCR2SBH _SFR_MEM8(0xF7)
1131
1132/* Output Compare RB Registers */
1133#define OCR2RB  _SFR_MEM16(0xF8)
1134#define OCR2RBL _SFR_MEM8(0xF8)
1135#define OCR2RBH _SFR_MEM8(0xF9)
1136
1137/* PSC 2 Configuration Register */
1138#define PCNF2   _SFR_MEM8(0xFA)
1139/* PCNF2 */
1140#define PFIFTY2  7  /* PSC 2 Fifty */
1141#define PALOCK2  6  /* PSC 2 Autolock */
1142#define PLOCK2   5  /* PSC 2 Lock */
1143#define PMODE21  4  /* PSC 2 Mode bit1 */
1144#define PMODE20  3  /* PSC 2 Mode bit0 */
1145#define POP2     2  /* PSC 2 Output Polarity */
1146#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
1147#define POME2    0  /* PSC 2 Output Matrix Enable */
1148
1149/* PSC 2 Control Register */
1150#define PCTL2   _SFR_MEM8(0xFB)
1151/* PCTL2 */
1152#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
1153#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
1154#define PBFM2   5   /* Balance Flank Width Modulation */
1155#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
1156#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
1157#define PARUN2  2   /* PSC 2 Autorun */
1158#define PCCYC2  1   /* PSC 2 Complete Cycle */
1159#define PRUN2   0   /* PSC 2 Run */
1160
1161/* PSC 2 Input A Control Register */
1162#define PFRC2A  _SFR_MEM8(0xFC)
1163/* PFRC2A */
1164#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
1165#define PISEL2A 6   /* PSC 2 Input Select for Part A */
1166#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
1167#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
1168#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
1169#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
1170#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
1171#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
1172
1173/* PSC 2 Input B Control Register */
1174#define PFRC2B  _SFR_MEM8(0xFD)
1175/* PFRC2B */
1176#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
1177#define PISEL2B 6   /* PSC 2 Input Select for Part B */
1178#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
1179#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
1180#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
1181#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
1182#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
1183#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
1184
1185/* PSC 2 Input Capture Registers */
1186#define PICR2   _SFR_MEM16(0xFE)
1187
1188#define PICR2L  _SFR_MEM8(0xFE)
1189
1190#define PICR2H  _SFR_MEM8(0xFF)
1191#define PCST2   7   /* PSC Capture Software Trig bit */
1192                    /* not implemented on AT90PWM2/AT90PWM3 */
1193
1194
1195/* Interrupt vectors */
1196/* PSC2 Capture Event */
1197#define PSC2_CAPT_vect                  _VECTOR(1)
1198#define SIG_PSC2_CAPTURE                _VECTOR(1)
1199
1200/* PSC2 End Cycle */
1201#define PSC2_EC_vect                    _VECTOR(2)
1202#define SIG_PSC2_END_CYCLE              _VECTOR(2)
1203
1204/* PSC1 Capture Event */
1205#define PSC1_CAPT_vect                  _VECTOR(3)
1206#define SIG_PSC1_CAPTURE                _VECTOR(3)
1207
1208/* PSC1 End Cycle */
1209#define PSC1_EC_vect                    _VECTOR(4)
1210#define SIG_PSC1_END_CYCLE              _VECTOR(4)
1211
1212/* PSC0 Capture Event */
1213#define PSC0_CAPT_vect                  _VECTOR(5)
1214#define SIG_PSC0_CAPTURE                _VECTOR(5)
1215
1216/* PSC0 End Cycle */
1217#define PSC0_EC_vect                    _VECTOR(6)
1218#define SIG_PSC0_END_CYCLE              _VECTOR(6)
1219
1220/* Analog Comparator 0 */
1221#define ANALOG_COMP_0_vect              _VECTOR(7)
1222#define SIG_COMPARATOR0                 _VECTOR(7)
1223
1224/* Analog Comparator 1 */
1225#define ANALOG_COMP_1_vect              _VECTOR(8)
1226#define SIG_COMPARATOR1                 _VECTOR(8)
1227
1228/* Analog Comparator 2 */
1229#define ANALOG_COMP_2_vect              _VECTOR(9)
1230#define SIG_COMPARATOR2                 _VECTOR(9)
1231
1232/* External Interrupt Request 0 */
1233#define INT0_vect                       _VECTOR(10)
1234#define SIG_INTERRUPT0                  _VECTOR(10)
1235
1236/* Timer/Counter1 Capture Event */
1237#define TIMER1_CAPT_vect                _VECTOR(11)
1238#define SIG_INPUT_CAPTURE1              _VECTOR(11)
1239
1240/* Timer/Counter1 Compare Match A */
1241#define TIMER1_COMPA_vect               _VECTOR(12)
1242#define SIG_OUTPUT_COMPARE1A            _VECTOR(12)
1243#define SIG_OUTPUT_COMPARE1_A           _VECTOR(12)
1244
1245/* Timer/Counter Compare Match B */
1246#define TIMER1_COMPB_vect               _VECTOR(13)
1247#define SIG_OUTPUT_COMPARE1B            _VECTOR(13)
1248#define SIG_OUTPUT_COMPARE1_B           _VECTOR(13)
1249
1250/* Timer/Counter1 Overflow */
1251#define TIMER1_OVF_vect                 _VECTOR(15)
1252#define SIG_OVERFLOW1                   _VECTOR(15)
1253
1254/* Timer/Counter0 Compare Match A */
1255#define TIMER0_COMP_A_vect              _VECTOR(16)
1256#define SIG_OUTPUT_COMPARE0A            _VECTOR(16)
1257#define SIG_OUTPUT_COMPARE0_A           _VECTOR(16)
1258
1259/* Timer/Counter0 Overflow */
1260#define TIMER0_OVF_vect                 _VECTOR(17)
1261#define SIG_OVERFLOW0                   _VECTOR(17)
1262
1263/* ADC Conversion Complete */
1264#define ADC_vect                        _VECTOR(18)
1265#define SIG_ADC                         _VECTOR(18)
1266
1267/* External Interrupt Request 1 */
1268#define INT1_vect                       _VECTOR(19)
1269#define SIG_INTERRUPT1                  _VECTOR(19)
1270
1271/* SPI Serial Transfer Complete */
1272#define SPI_STC_vect                    _VECTOR(20)
1273#define SIG_SPI                         _VECTOR(20)
1274
1275/* USART, Rx Complete */
1276#define USART_RX_vect                   _VECTOR(21)
1277#define SIG_USART_RECV                  _VECTOR(21)
1278#define SIG_UART_RECV                   _VECTOR(21)
1279
1280/* USART Data Register Empty */
1281#define USART_UDRE_vect                 _VECTOR(22)
1282#define SIG_USART_DATA                  _VECTOR(22)
1283#define SIG_UART_DATA                   _VECTOR(22)
1284
1285/* USART, Tx Complete */
1286#define USART_TX_vect                   _VECTOR(23)
1287#define SIG_USART_TRANS                 _VECTOR(23)
1288#define SIG_UART_TRANS                  _VECTOR(23)
1289
1290/* External Interrupt Request 2 */
1291#define INT2_vect                       _VECTOR(24)
1292#define SIG_INTERRUPT2                  _VECTOR(24)
1293
1294/* Watchdog Timeout Interrupt */
1295#define WDT_vect                        _VECTOR(25)
1296#define SIG_WDT                         _VECTOR(25)
1297#define SIG_WATCHDOG_TIMEOUT            _VECTOR(25)
1298
1299/* EEPROM Ready */
1300#define EE_READY_vect                   _VECTOR(26)
1301#define SIG_EEPROM_READY                _VECTOR(26)
1302
1303/* Timer Counter 0 Compare Match B */
1304#define TIMER0_COMPB_vect               _VECTOR(27)
1305#define SIG_OUTPUT_COMPARE0B            _VECTOR(27)
1306#define SIG_OUTPUT_COMPARE0_B           _VECTOR(27)
1307
1308/* External Interrupt Request 3 */
1309#define INT3_vect                       _VECTOR(28)
1310#define SIG_INTERRUPT3                  _VECTOR(28)
1311
1312/* Store Program Memory Read */
1313#define SPM_READY_vect                  _VECTOR(31)
1314#define SIG_SPM_READY                   _VECTOR(31)
1315
1316#define _VECTORS_SIZE   64
1317
1318/* Constants */
1319#define SPM_PAGESIZE    64
1320
1321#define RAMEND      0x02FF
1322#define XRAMEND     RAMEND
1323#define E2END       0x01FF
1324#define E2PAGESIZE  4
1325#define FLASHEND    0x0FFF
1326
1327
1328/* Fuse Information */
1329
1330#define FUSE_MEMORY_SIZE 3
1331
1332/* Low Fuse Byte */
1333#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
1334#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
1335#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
1336#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
1337#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
1338#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
1339#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
1340#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
1341#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
1342
1343/* High Fuse Byte */
1344#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)
1345#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)
1346#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)
1347#define FUSE_EESAVE     (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1348#define FUSE_WDTON      (unsigned char)~_BV(4)  /* Watchdog timer always on */
1349#define FUSE_SPIEN      (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1350#define FUSE_DWEN       (unsigned char)~_BV(6)  /* debugWIRE Enable */
1351#define FUSE_RSTDISBL   (unsigned char)~_BV(7)  /* External Reset Diasble */
1352#define HFUSE_DEFAULT (FUSE_SPIEN)
1353
1354/* Extended Fuse Byte */
1355#define FUSE_BOOTRST     (unsigned char)~_BV(0)
1356#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
1357#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
1358#define FUSE_PSCRV       (unsigned char)~_BV(4)
1359#define FUSE_PSC0RB      (unsigned char)~_BV(5)
1360#define FUSE_PSC1RB      (unsigned char)~_BV(6)
1361#define FUSE_PSC2RB      (unsigned char)~_BV(7)
1362#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
1363
1364
1365/* Lock Bits */
1366#define __LOCK_BITS_EXIST
1367#define __BOOT_LOCK_BITS_0_EXIST
1368#define __BOOT_LOCK_BITS_1_EXIST
1369
1370
1371#endif /* _AVR_IO90PWMX_H_ */
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