source: rtems/cpukit/score/cpu/avr/avr/io90pwm1.h @ b697bc6

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1/**
2 * @file
3 *
4 * @brief Definitions for AT90PWM1
5 *
6 * This file should only be included from <avr/io.h>, never directly.
7 */
8
9/* Copyright (c) 2005, Andrey Pashchenko
10   Copyright (c) 2007, Anatoly Sokolov
11   All rights reserved.
12
13   Redistribution and use in source and binary forms, with or without
14   modification, are permitted provided that the following conditions are met:
15
16   * Redistributions of source code must retain the above copyright
17     notice, this list of conditions and the following disclaimer.
18
19   * Redistributions in binary form must reproduce the above copyright
20     notice, this list of conditions and the following disclaimer in
21     the documentation and/or other materials provided with the
22     distribution.
23
24   * Neither the name of the copyright holders nor the names of
25     contributors may be used to endorse or promote products derived
26     from this software without specific prior written permission.
27
28  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  POSSIBILITY OF SUCH DAMAGE. */
39
40
41/* avr/iopwm1.h - definitions for AT90PWM1 device */
42
43#ifndef _AVR_IOPWM1_H_
44#define _AVR_IOPWM1_H_ 1
45
46/* This file should only be included from <avr/io.h>, never directly. */
47
48#ifndef _AVR_IO_H_
49#  error "Include <avr/io.h> instead of this file."
50#endif
51
52#ifndef _AVR_IOXXX_H_
53#  define _AVR_IOXXX_H_ "iopwm1.h"
54#else
55#  error "Attempt to include more than one <avr/ioXXX.h> file."
56#endif
57
58/**
59 * @defgroup AvrDef_io90pwm1 AT90PWM1 Definitions
60 *
61 * @ingroup avr
62 *
63 */
64/**@{**/
65
66/* I/O registers */
67
68/* Reserved [0x00..0x02] */
69
70/* Port B Input Pins Address */
71#define PINB    _SFR_IO8(0x03)
72/* PINB */
73#define PINB7   7
74#define PINB6   6
75#define PINB5   5
76#define PINB4   4
77#define PINB3   3
78#define PINB2   2
79#define PINB1   1
80#define PINB0   0
81
82/* Port B Data Direction Register */
83#define DDRB    _SFR_IO8(0x04)
84/* DDRB */
85#define DDB7    7
86#define DDB6    6
87#define DDB5    5
88#define DDB4    4
89#define DDB3    3
90#define DDB2    2
91#define DDB1    1
92#define DDB0    0
93
94/* Port B Data Register */
95#define PORTB   _SFR_IO8(0x05)
96/* PORTB */
97#define PB7     7
98#define PB6     6
99#define PB5     5
100#define PB4     4
101#define PB3     3
102#define PB2     2
103#define PB1     1
104#define PB0     0
105
106/* Reserved [0x06..0x08] */
107
108/* Port D Input Pins Address */
109#define PIND    _SFR_IO8(0x09)
110/* PIND */
111#define PIND7   7
112#define PIND6   6
113#define PIND5   5
114#define PIND4   4
115#define PIND3   3
116#define PIND2   2
117#define PIND1   1
118#define PIND0   0
119
120/* Port D Data Direction Register */
121#define DDRD    _SFR_IO8(0x0A)
122/* DDRD */
123#define DDD7    7
124#define DDD6    6
125#define DDD5    5
126#define DDD4    4
127#define DDD3    3
128#define DDD2    2
129#define DDD1    1
130#define DDD0    0
131
132/* Port D Data Register */
133#define PORTD   _SFR_IO8(0x0B)
134/* PORTD */
135#define PD7     7
136#define PD6     6
137#define PD5     5
138#define PD4     4
139#define PD3     3
140#define PD2     2
141#define PD1     1
142#define PD0     0
143
144/* Port E Input Pins Address */
145#define PINE    _SFR_IO8(0x0C)
146/* PINE */
147#define PINE2   2
148#define PINE1   1
149#define PINE0   0
150
151/* Port E Data Direction Register */
152#define DDRE    _SFR_IO8(0x0D)
153/* DDRE */
154#define DDE2    2
155#define DDE1    1
156#define DDE0    0
157
158/* Port E Data Register */
159#define PORTE   _SFR_IO8(0x0E)
160/* PORTE */
161#define PE2     2
162#define PE1     1
163#define PE0     0
164
165/* Reserved [0x0F..0x14] */
166
167/* Timer/Counter 0 Interrupt Flag Register */
168#define TIFR0   _SFR_IO8(0x15)
169/* TIFR0 */
170#define OCF0B   2   /* Output Compare Flag 0B */
171#define OCF0A   1   /* Output Compare Flag 0A */
172#define TOV0    0   /* Overflow Flag */
173
174/* Timer/Counter1 Interrupt Flag Register */
175#define TIFR1   _SFR_IO8(0x16)
176/* TIFR1 */
177#define ICF1    5   /* Input Capture Flag 1 */
178#define OCF1B   2   /* Output Compare Flag 1B*/
179#define OCF1A   1   /* Output Compare Flag 1A*/
180#define TOV1    0   /* Overflow Flag */
181
182/* Reserved [0x17..0x18] */
183
184/* General Purpose I/O Register 1 */
185#define GPIOR1  _SFR_IO8(0x19)
186/* GPIOR1 */
187#define GPIOR17 7
188#define GPIOR16 6
189#define GPIOR15 5
190#define GPIOR14 4
191#define GPIOR13 3
192#define GPIOR12 2
193#define GPIOR11 1
194#define GPIOR10 0
195
196/* General Purpose I/O Register 2 */
197#define GPIOR2  _SFR_IO8(0x1A)
198/* GPIOR2 */
199#define GPIOR27 7
200#define GPIOR26 6
201#define GPIOR25 5
202#define GPIOR24 4
203#define GPIOR23 3
204#define GPIOR22 2
205#define GPIOR21 1
206#define GPIOR20 0
207
208/* General Purpose I/O Register 3 */
209#define GPIOR3  _SFR_IO8(0x1B)
210/* GPIOR3 */
211#define GPIOR37 7
212#define GPIOR36 6
213#define GPIOR35 5
214#define GPIOR34 4
215#define GPIOR33 3
216#define GPIOR32 2
217#define GPIOR31 1
218#define GPIOR30 0
219
220/* External Interrupt Flag Register */
221#define EIFR    _SFR_IO8(0x1C)
222/* EIFR */
223#define INTF3   3
224#define INTF2   2
225#define INTF1   1
226#define INTF0   0
227
228/* External Interrupt Mask Register */
229#define EIMSK   _SFR_IO8(0x1D)
230/* EIMSK */
231#define INT3    3   /* External Interrupt Request 3 Enable */
232#define INT2    2   /* External Interrupt Request 2 Enable */
233#define INT1    1   /* External Interrupt Request 1 Enable */
234#define INT0    0   /* External Interrupt Request 0 Enable */
235
236/* General Purpose I/O Register 0 */
237#define GPIOR0  _SFR_IO8(0x1E)
238/* GPIOR0 */
239#define GPIOR07 7
240#define GPIOR06 6
241#define GPIOR05 5
242#define GPIOR04 4
243#define GPIOR03 3
244#define GPIOR02 2
245#define GPIOR01 1
246#define GPIOR00 0
247
248/* EEPROM Control Register */
249#define EECR    _SFR_IO8(0x1F)
250/* EECR */
251#define EERIE   3   /* EEPROM Ready Interrupt Enable */
252#define EEMWE   2   /* EEPROM Master Write Enable */
253#define EEWE    1   /* EEPROM Write Enable */
254#define EERE    0   /* EEPROM Read Enable */
255
256/* EEPROM Data Register */
257#define EEDR    _SFR_IO8(0x20)
258/* EEDR */
259#define EEDR7   7
260#define EEDR6   6
261#define EEDR5   5
262#define EEDR4   4
263#define EEDR3   3
264#define EEDR2   2
265#define EEDR1   1
266#define EEDR0   0
267
268/* The EEPROM Address Registers */
269#define EEAR    _SFR_IO16(0x21)
270#define EEARL   _SFR_IO8(0x21)
271#define EEARH   _SFR_IO8(0x22)
272/* EEARH */
273#define EEAR11  3
274#define EEAR10  2
275#define EEAR9   1
276#define EEAR8   0
277/* EEARL */
278#define EEAR7   7
279#define EEAR6   6
280#define EEAR5   5
281#define EEAR4   4
282#define EEAR3   3
283#define EEAR2   2
284#define EEAR1   1
285#define EEAR0   0
286
287/* 6-char sequence denoting where to find the EEPROM registers in memory space.
288   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
289   subroutines.
290   First two letters:  EECR address.
291   Second two letters: EEDR address.
292   Last two letters:   EEAR address.  */
293#define __EEPROM_REG_LOCATIONS__ 1F2021
294
295/* General Timer/Counter Control Register */
296#define GTCCR   _SFR_IO8(0x23)
297/* GTCCR */
298#define TSM     7   /* Timer/Counter Synchronization Mode */
299#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
300#define PSRSYNC 0
301
302/* Timer/Counter Control Register A */
303#define TCCR0A  _SFR_IO8(0x24)
304/* TCCR0A */
305#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
306#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
307#define COM0B1  5   /* Compare Output Mode, Fast PWm */
308#define COM0B0  4   /* Compare Output Mode, Fast PWm */
309#define WGM01   1   /* Waveform Generation Mode */
310#define WGM00   0   /* Waveform Generation Mode */
311
312/* Timer/Counter Control Register B */
313#define TCCR0B  _SFR_IO8(0x25)
314/* TCCR0B */
315#define FOC0A   7   /* Force Output Compare A */
316#define FOC0B   6   /* Force Output Compare B */
317#define WGM02   3   /* Waveform Generation Mode */
318#define CS02    2   /* Clock Select */
319#define CS01    1   /* Clock Select */
320#define CS00    0   /* Clock Select */
321
322/* Timer/Counter0 Register */
323#define TCNT0   _SFR_IO8(0x26)
324/* TCNT0 */
325#define TCNT07  7
326#define TCNT06  6
327#define TCNT05  5
328#define TCNT04  4
329#define TCNT03  3
330#define TCNT02  2
331#define TCNT01  1
332#define TCNT00  0
333
334/* Timer/Counter0 Output Compare Register A */
335#define OCR0A   _SFR_IO8(0x27)
336/* OCR0A */
337#define OCR0A7  7
338#define OCR0A6  6
339#define OCR0A5  5
340#define OCR0A4  4
341#define OCR0A3  3
342#define OCR0A2  2
343#define OCR0A1  1
344#define OCR0A0  0
345
346/* Timer/Counter0 Output Compare Register B */
347#define OCR0B   _SFR_IO8(0x28)
348/* OCR0B */
349#define OCR0B7  7
350#define OCR0B6  6
351#define OCR0B5  5
352#define OCR0B4  4
353#define OCR0B3  3
354#define OCR0B2  2
355#define OCR0B1  1
356#define OCR0B0  0
357
358/* PLL Control and Status Register */
359#define PLLCSR  _SFR_IO8(0x29)
360/* PLLCSR */
361#define PLLF    2
362#define PLLE    1   /* PLL Enable */
363#define PLOCK   0   /* PLL Lock Detector */
364
365/* Reserved [0x2A..0x2B] */
366
367/* SPI Control Register */
368#define SPCR    _SFR_IO8(0x2C)
369/* SPCR */
370#define SPIE    7   /* SPI Interrupt Enable */
371#define SPE     6   /* SPI Enable */
372#define DORD    5   /* Data Order */
373#define MSTR    4   /* Master/Slave Select */
374#define CPOL    3   /* Clock polarity */
375#define CPHA    2   /* Clock Phase */
376#define SPR1    1   /* SPI Clock Rate Select 1 */
377#define SPR0    0   /* SPI Clock Rate Select 0 */
378
379/* SPI Status Register */
380#define SPSR    _SFR_IO8(0x2D)
381/* SPSR */
382#define SPIF    7   /* SPI Interrupt Flag */
383#define WCOL    6   /* Write Collision Flag */
384#define SPI2X   0   /* Double SPI Speed Bit */
385
386/* SPI Data Register */
387#define SPDR    _SFR_IO8(0x2E)
388/* SPDR */
389#define SPD7    7
390#define SPD6    6
391#define SPD5    5
392#define SPD4    4
393#define SPD3    3
394#define SPD2    2
395#define SPD1    1
396#define SPD0    0
397
398/* Reserved [0x2F] */
399
400/* Analog Comparator Status Register */
401#define ACSR    _SFR_IO8(0x30)
402/* ACSR */
403#define ACCKDIV 7   /* Analog Comparator Clock Divider */
404#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
405#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
406#define AC2O    2   /* Analog Comparator 2 Output Bit */
407#define AC0O    0   /* Analog Comparator 0 Output Bit */
408
409/* Monitor Data Register */
410#define MONDR   _SFR_IO8(0x31)
411
412/* Monitor Stop Mode Control Register */
413#define MSMCR   _SFR_IO8(0x32)
414
415/* Sleep Mode Control Register */
416#define SMCR    _SFR_IO8(0x33)
417/* SMCR */
418#define SM2     3   /* Sleep Mode Select bit2 */
419#define SM1     2   /* Sleep Mode Select bit1 */
420#define SM0     1   /* Sleep Mode Select bit0 */
421#define SE      0   /* Sleep Enable */
422
423/* MCU Status Register */
424#define MCUSR   _SFR_IO8(0x34)
425/* MCUSR */
426#define WDRF    3   /* Watchdog Reset Flag */
427#define BORF    2   /* Brown-out Reset Flag */
428#define EXTRF   1   /* External Reset Flag */
429#define PORF    0   /* Power-on reset flag */
430
431/* MCU Control Register */
432#define MCUCR   _SFR_IO8(0x35)
433/* MCUCR */
434#define SPIPS   7   /* SPI Pin Select */
435#define PUD     4   /* Pull-up disable */
436#define IVSEL   1   /* Interrupt Vector Select */
437#define IVCE    0   /* Interrupt Vector Change Enable */
438
439/* Reserved [0x36] */
440
441/* Store Program Memory Control Register */
442#define SPMCSR  _SFR_IO8(0x37)
443/* SPMCSR */
444#define SPMIE   7   /* SPM Interrupt Enable */
445#define RWWSB   6   /* Read While Write Section Busy */
446#define RWWSRE  4   /* Read While Write section read enable */
447#define BLBSET  3   /* Boot Lock Bit Set */
448#define PGWRT   2   /* Page Write */
449#define PGERS   1   /* Page Erase */
450#define SPMEN   0   /* Store Program Memory Enable */
451
452/* Reserved [0x38..0x3C] */
453
454/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
455/* 0x3F SREG      [defined in <avr/io.h>] */
456
457/* Watchdog Timer Control Register */
458#define WDTCSR  _SFR_MEM8(0x60)
459/* WDTCSR */
460#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
461#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
462#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
463#define WDCE    4   /* Watchdog Change Enable */
464#define WDE     3   /* Watchdog Enable */
465#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
466#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
467#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
468
469/* Clock Prescaler Register */
470#define CLKPR   _SFR_MEM8(0x61)
471/* CLKPR */
472#define CLKPCE  7   /* Clock Prescaler Change Enable */
473#define CLKPS3  3   /* Clock Prescaler Select bit3 */
474#define CLKPS2  2   /* Clock Prescaler Select bit2 */
475#define CLKPS1  1   /* Clock Prescaler Select bit1 */
476#define CLKPS0  0   /* Clock Prescaler Select bit0 */
477
478/* Reserved [0x62..0x63] */
479
480/* Power Reduction Register */
481#define PRR     _SFR_MEM8(0x64)
482/* PRR */
483#define PRPSC2  7   /* Power Reduction PSC2 */
484#define PRPSC1  6   /* Power Reduction PSC1 */
485#define PRPSC0  5   /* Power Reduction PSC0 */
486#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
487#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
488#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
489#define PRADC   0   /* Power Reduction ADC */
490
491/* Reserved [0x65] */
492
493/* Oscillator Calibration Value */
494#define OSCCAL  _SFR_MEM8(0x66)
495/* OSCCAL */
496#define CAL6    6
497#define CAL5    5
498#define CAL4    4
499#define CAL3    3
500#define CAL2    2
501#define CAL1    1
502#define CAL0    0
503
504/* Reserved [0x67..0x68] */
505
506/* External Interrupt Control Register A */
507#define EICRA   _SFR_MEM8(0x69)
508/* EICRA */
509#define ISC31   7
510#define ISC30   6
511#define ISC21   5
512#define ISC20   4
513#define ISC11   3
514#define ISC10   2
515#define ISC01   1
516#define ISC00   0
517
518/* Reserved [0x6A..0x6D] */
519
520/* Timer/Counter0 Interrupt Mask Register */
521#define TIMSK0  _SFR_MEM8(0x6E)
522/* TIMSK0 */
523#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
524#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
525#define TOIE0   0   /* Overflow Interrupt Enable */
526
527/* Timer/Counter1 Interrupt Mask Register */
528#define TIMSK1  _SFR_MEM8(0x6F)
529/* TIMSK1 */
530#define ICIE1   5   /* Input Capture Interrupt Enable */
531#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
532#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
533#define TOIE1   0   /* Overflow Interrupt Enable */
534
535/* Reserved [0x70..0x75] */
536
537/* Amplifier 0 Control and Status register */
538#define AMP0CSR _SFR_MEM8(0x76)
539#define AMP0EN  7
540#define AMP0IS  6
541#define AMP0G1  5
542#define AMP0G0  4
543#define AMP0TS1 1
544#define AMP0TS0 0
545
546/* Reserved [0x77] */
547
548/* ADC Result Data Register */
549#ifndef __ASSEMBLER__
550#define ADC     _SFR_MEM16(0x78)
551#endif
552#define ADCW    _SFR_MEM16(0x78)
553#define ADCL    _SFR_MEM8(0x78)
554#define ADCH    _SFR_MEM8(0x79)
555
556/* ADC Control and Status Register A */
557#define ADCSRA  _SFR_MEM8(0x7A)
558/* ADCSRA */
559#define ADEN    7   /* ADC Enable */
560#define ADSC    6   /* ADC Start Conversion */
561#define ADATE   5   /* ADC Auto Trigger Enable */
562#define ADIF    4   /* ADC Interrupt Flag */
563#define ADIE    3   /* ADC Interrupt Enable */
564#define ADPS2   2   /* ADC Prescaler Select bit2 */
565#define ADPS1   1   /* ADC Prescaler Select bit1 */
566#define ADPS0   0   /* ADC Prescaler Select bit0 */
567
568/* ADC Control and Status Register B */
569#define ADCSRB  _SFR_MEM8(0x7B)
570/* ADCSRB */
571#define ADTS3   3   /* ADC Auto Trigger Source 2 */
572#define ADTS2   2   /* ADC Auto Trigger Source 2 */
573#define ADTS1   1   /* ADC Auto Trigger Source 1 */
574#define ADTS0   0   /* ADC Auto Trigger Source 0 */
575
576/* ADC multiplexer Selection Register */
577#define ADMUX   _SFR_MEM8(0x7C)
578/* ADMUX */
579#define REFS1   7   /* Reference Selection bit1 */
580#define REFS0   6   /* Reference Selection bit0 */
581#define ADLAR   5   /* Left Adjust Result */
582#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
583#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
584#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
585#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
586
587/* Reserved [0x7D] */
588
589/* Digital Input Disable Register 0 */
590#define DIDR0   _SFR_MEM8(0x7E)
591/* DIDR0 */
592#define ADC7D   7   /* ADC7 Digital input Disable */
593#define ADC6D   6   /* ADC6 Digital input Disable */
594#define ADC5D   5   /* ADC5 Digital input Disable */
595#define ADC4D   4   /* ADC4 Digital input Disable */
596#define ADC3D   3   /* ADC3 Digital input Disable */
597#define ADC2D   2   /* ADC2 Digital input Disable */
598#define ADC1D   1   /* ADC1 Digital input Disable */
599#define ADC0D   0   /* ADC0 Digital input Disable */
600
601/* Digital Input Disable Register 1 */
602#define DIDR1   _SFR_MEM8(0x7F)
603/* DIDR1 */
604#define ACMP0D  5
605#define AMP0PD  4
606#define AMP0ND  3
607#define ADC10D  2   /* ADC10 Digital input Disable */
608#define ADC9D   1   /* ADC9 Digital input Disable */
609#define ADC8D   0   /* ADC8 Digital input Disable */
610
611/* Timer/Counter1 Control Register A */
612#define TCCR1A  _SFR_MEM8(0x80)
613/* TCCR1A */
614#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
615#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
616#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
617#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
618#define WGM11   1   /* Waveform Generation Mode */
619#define WGM10   0   /* Waveform Generation Mode */
620
621/* Timer/Counter1 Control Register B */
622#define TCCR1B  _SFR_MEM8(0x81)
623/* TCCR1B */
624#define ICNC1   7   /* Input Capture 1 Noise Canceler */
625#define ICES1   6   /* Input Capture 1 Edge Select */
626#define WGM13   4   /* Waveform Generation Mode */
627#define WGM12   3   /* Waveform Generation Mode */
628#define CS12    2   /* Prescaler source of Timer/Counter 1 */
629#define CS11    1   /* Prescaler source of Timer/Counter 1 */
630#define CS10    0   /* Prescaler source of Timer/Counter 1 */
631
632/* Timer/Counter1 Control Register C */
633#define TCCR1C  _SFR_MEM8(0x82)
634/* TCCR1C */
635#define FOC1A   7   /* Force Output Compare for Channel A */
636#define FOC1B   6   /* Force Output Compare for Channel B */
637
638/* Reserved [0x83] */
639
640/* Timer/Counter1 */
641#define TCNT1   _SFR_MEM16(0x84)
642#define TCNT1L  _SFR_MEM8(0x84)
643#define TCNT1H  _SFR_MEM8(0x85)
644/* TCNT1H */
645#define TCNT115 7
646#define TCNT114 6
647#define TCNT113 5
648#define TCNT112 4
649#define TCNT111 3
650#define TCNT110 2
651#define TCNT19  1
652#define TCNT18  0
653/* TCNT1L */
654#define TCNT17  7
655#define TCNT16  6
656#define TCNT15  5
657#define TCNT14  4
658#define TCNT13  3
659#define TCNT12  2
660#define TCNT11  1
661#define TCNT10  0
662
663/* Input Capture Register 1 */
664#define ICR1    _SFR_MEM16(0x86)
665#define ICR1L   _SFR_MEM8(0x86)
666#define ICR1H   _SFR_MEM8(0x87)
667/* ICR1H */
668#define ICR115  7
669#define ICR114  6
670#define ICR113  5
671#define ICR112  4
672#define ICR111  3
673#define ICR110  2
674#define ICR19   1
675#define ICR18   0
676/* ICR1L */
677#define ICR17   7
678#define ICR16   6
679#define ICR15   5
680#define ICR14   4
681#define ICR13   3
682#define ICR12   2
683#define ICR11   1
684#define ICR10   0
685
686/* Output Compare Register 1 A */
687#define OCR1A   _SFR_MEM16(0x88)
688#define OCR1AL  _SFR_MEM8(0x88)
689#define OCR1AH  _SFR_MEM8(0x89)
690/* OCR1AH */
691#define OCR1A15 7
692#define OCR1A14 6
693#define OCR1A13 5
694#define OCR1A12 4
695#define OCR1A11 3
696#define OCR1A10 2
697#define OCR1A9  1
698#define OCR1A8  0
699/* OCR1AL */
700#define OCR1A7  7
701#define OCR1A6  6
702#define OCR1A5  5
703#define OCR1A4  4
704#define OCR1A3  3
705#define OCR1A2  2
706#define OCR1A1  1
707#define OCR1A0  0
708
709/* Output Compare Register 1 B */
710#define OCR1B   _SFR_MEM16(0x8A)
711#define OCR1BL  _SFR_MEM8(0x8A)
712#define OCR1BH  _SFR_MEM8(0x8B)
713/* OCR1BH */
714#define OCR1B15 7
715#define OCR1B14 6
716#define OCR1B13 5
717#define OCR1B12 4
718#define OCR1B11 3
719#define OCR1B10 2
720#define OCR1B9  1
721#define OCR1B8  0
722/* OCR1BL */
723#define OCR1B7  7
724#define OCR1B6  6
725#define OCR1B5  5
726#define OCR1B4  4
727#define OCR1B3  3
728#define OCR1B2  2
729#define OCR1B1  1
730#define OCR1B0  0
731
732/* Reserved [0x8C..0x9F] */
733
734/* PSC0 Interrupt Flag Register */
735#define PIFR0   _SFR_MEM8(0xA0)
736/* PIFR0 */
737#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
738#define PEV0B   4   /* PSC0 External Event B Interrupt */
739#define PEV0A   3   /* PSC0 External Event A Interrupt */
740#define PRN01   2   /* PSC0 Ramp Number bit1 */
741#define PRN00   1   /* PSC0 Ramp Number bit0 */
742#define PEOP0   0   /* End Of PSC0 Interrupt */
743
744/* PSC0 Interrupt Mask Register */
745#define PIM0    _SFR_MEM8(0xA1)
746/* PIM0 */
747#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
748#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
749#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
750#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
751
752/* Reserved [0xA2..0xA3] */
753
754/* PSC2 Interrupt Flag Register */
755#define PIFR2   _SFR_MEM8(0xA4)
756/* PIFR2 */
757#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
758#define PEV2B   4   /* PSC2 External Event B Interrupt */
759#define PEV2A   3   /* PSC2 External Event A Interrupt */
760#define PRN21   2   /* PSC2 Ramp Number bit1 */
761#define PRN20   1   /* PSC2 Ramp Number bit0 */
762#define PEOP2   0   /* End Of PSC2 Interrupt */
763
764/* PSC2 Interrupt Mask Register */
765#define PIM2    _SFR_MEM8(0xA5)
766/* PIM2 */
767#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
768#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
769#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
770#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
771
772/* Reserved [0xA6..0xAC] */
773
774/* Analog Comparator 0 Control Register */
775#define AC0CON  _SFR_MEM8(0xAD)
776/* AC0CON */
777#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
778#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
779#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
780#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
781#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
782#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
783#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
784
785/* Reserved [0xB0..0xAE] */
786
787/* Analog Comparator 2 Control Register */
788#define AC2CON  _SFR_MEM8(0xAF)
789/* AC2CON */
790#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
791#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
792#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
793#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
794#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
795#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
796#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
797
798/* Reserved [0xB0..0xCF] */
799
800/* PSC 0 Synchro and Output Configuration */
801#define PSOC0   _SFR_MEM8(0xD0)
802/* PSOC0 */
803#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
804#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
805#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
806#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
807
808/* Reserved [0xD1] */
809
810/* Output Compare SA Registers */
811#define OCR0SA  _SFR_MEM16(0xD2)
812#define OCR0SAL _SFR_MEM8(0xD2)
813#define OCR0SAH _SFR_MEM8(0xD3)
814
815/* Output Compare RA Registers */
816#define OCR0RA  _SFR_MEM16(0xD4)
817#define OCR0RAL _SFR_MEM8(0xD4)
818#define OCR0RAH _SFR_MEM8(0xD5)
819
820/* Output Compare SB Registers */
821#define OCR0SB  _SFR_MEM16(0xD6)
822#define OCR0SBL _SFR_MEM8(0xD6)
823#define OCR0SBH _SFR_MEM8(0xD7)
824
825/* Output Compare RB Registers */
826#define OCR0RB  _SFR_MEM16(0xD8)
827#define OCR0RBL _SFR_MEM8(0xD8)
828#define OCR0RBH _SFR_MEM8(0xD9)
829
830/* PSC 0 Configuration Register */
831#define PCNF0   _SFR_MEM8(0xDA)
832/* PCNF0 */
833#define PFIFTY0  7  /* PSC 0 Fifty */
834#define PALOCK0  6  /* PSC 0 Autolock */
835#define PLOCK0   5  /* PSC 0 Lock */
836#define PMODE01  4  /* PSC 0 Mode bit1 */
837#define PMODE00  3  /* PSC 0 Mode bit0 */
838#define POP0     2  /* PSC 0 Output Polarity */
839#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
840
841/* PSC 0 Control Register */
842#define PCTL0   _SFR_MEM8(0xDB)
843/* PCTL0 */
844#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
845#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
846#define PBFM0   5   /* Balance Flank Width Modulation */
847#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
848#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
849#define PARUN0  2   /* PSC 0 Autorun */
850#define PCCYC0  1   /* PSC 0 Complete Cycle */
851#define PRUN0   0   /* PSC 0 Run */
852
853/* PSC 0 Input A Control Register */
854#define PFRC0A  _SFR_MEM8(0xDC)
855/* PFRC0A */
856#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
857#define PISEL0A 6   /* PSC 0 Input Select for Part A */
858#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
859#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
860#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
861#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
862#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
863#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
864
865/* PSC 0 Input B Control Register */
866#define PFRC0B  _SFR_MEM8(0xDD)
867/* PFRC0B */
868#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
869#define PISEL0B 6   /* PSC 0 Input Select for Part B */
870#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
871#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
872#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
873#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
874#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
875#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
876
877/* PSC 0 Input Capture Registers */
878#define PICR0   _SFR_MEM16(0xDE)
879
880#define PICR0L  _SFR_MEM8(0xDE)
881
882#define PICR0H  _SFR_MEM8(0xDF)
883#define PCST0   7   /* PSC Capture Software Trig bit */
884
885/* Reserved [0xE0..0xEF] */
886
887/* PSC 2 Synchro and Output Configuration */
888#define PSOC2   _SFR_MEM8(0xF0)
889/* PSOC2 */
890#define POS23   7   /* PSCOUT23 Selection */
891#define POS22   6   /* PSCOUT22 Selection */
892#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
893#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
894#define POEN2D  3   /* PSCOUT23 Output Enable */
895#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
896#define POEN2C  1   /* PSCOUT22 Output Enable */
897#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
898
899/* PSC 2 Output Matrix */
900#define POM2    _SFR_MEM8(0xF1)
901/* POM2 */
902#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
903#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
904#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
905#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
906#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
907#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
908#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
909#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
910
911/* Output Compare SA Registers */
912#define OCR2SA  _SFR_MEM16(0xF2)
913#define OCR2SAL _SFR_MEM8(0xF2)
914#define OCR2SAH _SFR_MEM8(0xF3)
915
916/* Output Compare RA Registers */
917#define OCR2RA  _SFR_MEM16(0xF4)
918#define OCR2RAL _SFR_MEM8(0xF4)
919#define OCR2RAH _SFR_MEM8(0xF5)
920
921/* Output Compare SB Registers */
922#define OCR2SB  _SFR_MEM16(0xF6)
923#define OCR2SBL _SFR_MEM8(0xF6)
924#define OCR2SBH _SFR_MEM8(0xF7)
925
926/* Output Compare RB Registers */
927#define OCR2RB  _SFR_MEM16(0xF8)
928#define OCR2RBL _SFR_MEM8(0xF8)
929#define OCR2RBH _SFR_MEM8(0xF9)
930
931/* PSC 2 Configuration Register */
932#define PCNF2   _SFR_MEM8(0xFA)
933/* PCNF2 */
934#define PFIFTY2  7  /* PSC 2 Fifty */
935#define PALOCK2  6  /* PSC 2 Autolock */
936#define PLOCK2   5  /* PSC 2 Lock */
937#define PMODE21  4  /* PSC 2 Mode bit1 */
938#define PMODE20  3  /* PSC 2 Mode bit0 */
939#define POP2     2  /* PSC 2 Output Polarity */
940#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
941#define POME2    0  /* PSC 2 Output Matrix Enable */
942
943/* PSC 2 Control Register */
944#define PCTL2   _SFR_MEM8(0xFB)
945/* PCTL2 */
946#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
947#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
948#define PBFM2   5   /* Balance Flank Width Modulation */
949#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
950#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
951#define PARUN2  2   /* PSC 2 Autorun */
952#define PCCYC2  1   /* PSC 2 Complete Cycle */
953#define PRUN2   0   /* PSC 2 Run */
954
955/* PSC 2 Input A Control Register */
956#define PFRC2A  _SFR_MEM8(0xFC)
957/* PFRC2A */
958#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
959#define PISEL2A 6   /* PSC 2 Input Select for Part A */
960#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
961#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
962#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
963#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
964#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
965#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
966
967/* PSC 2 Input B Control Register */
968#define PFRC2B  _SFR_MEM8(0xFD)
969/* PFRC2B */
970#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
971#define PISEL2B 6   /* PSC 2 Input Select for Part B */
972#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
973#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
974#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
975#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
976#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
977#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
978
979/* PSC 2 Input Capture Registers */
980#define PICR2   _SFR_MEM16(0xFE)
981
982#define PICR2L  _SFR_MEM8(0xFE)
983
984#define PICR2H  _SFR_MEM8(0xFF)
985#define PCST2   7   /* PSC Capture Software Trig bit */
986                    /* not implemented on AT90PWM2/AT90PWM3 */
987
988
989/* Interrupt vectors */
990/* PSC2 Capture Event */
991#define PSC2_CAPT_vect                  _VECTOR(1)
992#define SIG_PSC2_CAPTURE                _VECTOR(1)
993
994/* PSC2 End Cycle */
995#define PSC2_EC_vect                    _VECTOR(2)
996#define SIG_PSC2_END_CYCLE              _VECTOR(2)
997
998/* PSC0 Capture Event */
999#define PSC0_CAPT_vect                  _VECTOR(5)
1000#define SIG_PSC0_CAPTURE                _VECTOR(5)
1001
1002/* PSC0 End Cycle */
1003#define PSC0_EC_vect                    _VECTOR(6)
1004#define SIG_PSC0_END_CYCLE              _VECTOR(6)
1005
1006/* Analog Comparator 0 */
1007#define ANALOG_COMP_0_vect              _VECTOR(7)
1008#define SIG_COMPARATOR0                 _VECTOR(7)
1009
1010/* Analog Comparator 2 */
1011#define ANALOG_COMP_2_vect              _VECTOR(9)
1012#define SIG_COMPARATOR2                 _VECTOR(9)
1013
1014/* External Interrupt Request 0 */
1015#define INT0_vect                       _VECTOR(10)
1016#define SIG_INTERRUPT0                  _VECTOR(10)
1017
1018/* Timer/Counter1 Capture Event */
1019#define TIMER1_CAPT_vect                _VECTOR(11)
1020#define SIG_INPUT_CAPTURE1              _VECTOR(11)
1021
1022/* Timer/Counter1 Compare Match A */
1023#define TIMER1_COMPA_vect               _VECTOR(12)
1024#define SIG_OUTPUT_COMPARE1A            _VECTOR(12)
1025#define SIG_OUTPUT_COMPARE1_A           _VECTOR(12)
1026
1027/* Timer/Counter Compare Match B */
1028#define TIMER1_COMPB_vect               _VECTOR(13)
1029#define SIG_OUTPUT_COMPARE1B            _VECTOR(13)
1030#define SIG_OUTPUT_COMPARE1_B           _VECTOR(13)
1031
1032/* Timer/Counter1 Overflow */
1033#define TIMER1_OVF_vect                 _VECTOR(15)
1034#define SIG_OVERFLOW1                   _VECTOR(15)
1035
1036/* Timer/Counter0 Compare Match A */
1037#define TIMER0_COMP_A_vect              _VECTOR(16)
1038#define SIG_OUTPUT_COMPARE0A            _VECTOR(16)
1039#define SIG_OUTPUT_COMPARE0_A           _VECTOR(16)
1040
1041/* Timer/Counter0 Overflow */
1042#define TIMER0_OVF_vect                 _VECTOR(17)
1043#define SIG_OVERFLOW0                   _VECTOR(17)
1044
1045/* ADC Conversion Complete */
1046#define ADC_vect                        _VECTOR(18)
1047#define SIG_ADC                         _VECTOR(18)
1048
1049/* External Interrupt Request 1 */
1050#define INT1_vect                       _VECTOR(19)
1051#define SIG_INTERRUPT1                  _VECTOR(19)
1052
1053/* SPI Serial Transfer Complete */
1054#define SPI_STC_vect                    _VECTOR(20)
1055#define SIG_SPI                         _VECTOR(20)
1056
1057/* External Interrupt Request 2 */
1058#define INT2_vect                       _VECTOR(24)
1059#define SIG_INTERRUPT2                  _VECTOR(24)
1060
1061/* Watchdog Timeout Interrupt */
1062#define WDT_vect                        _VECTOR(25)
1063#define SIG_WDT                         _VECTOR(25)
1064#define SIG_WATCHDOG_TIMEOUT            _VECTOR(25)
1065
1066/* EEPROM Ready */
1067#define EE_READY_vect                   _VECTOR(26)
1068#define SIG_EEPROM_READY                _VECTOR(26)
1069
1070/* Timer Counter 0 Compare Match B */
1071#define TIMER0_COMPB_vect               _VECTOR(27)
1072#define SIG_OUTPUT_COMPARE0B            _VECTOR(27)
1073#define SIG_OUTPUT_COMPARE0_B           _VECTOR(27)
1074
1075/* External Interrupt Request 3 */
1076#define INT3_vect                       _VECTOR(28)
1077#define SIG_INTERRUPT3                  _VECTOR(28)
1078
1079/* Store Program Memory Read */
1080#define SPM_READY_vect                  _VECTOR(31)
1081#define SIG_SPM_READY                   _VECTOR(31)
1082
1083#define _VECTORS_SIZE   64
1084
1085/* Constants */
1086#define SPM_PAGESIZE    64
1087
1088#define RAMEND      0x02FF
1089#define XRAMEND     RAMEND
1090#define E2END       0x01FF
1091#define FLASHEND    0x0FFF
1092
1093
1094/* Fuse Information */
1095
1096#define FUSE_MEMORY_SIZE 3
1097
1098/* Low Fuse Byte */
1099#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
1100#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
1101#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
1102#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
1103#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
1104#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
1105#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
1106#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
1107#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
1108
1109/* High Fuse Byte */
1110#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)
1111#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)
1112#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)
1113#define FUSE_EESAVE     (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1114#define FUSE_WDTON      (unsigned char)~_BV(4)  /* Watchdog timer always on */
1115#define FUSE_SPIEN      (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1116#define FUSE_DWEN       (unsigned char)~_BV(6)  /* debugWIRE Enable */
1117#define FUSE_RSTDISBL   (unsigned char)~_BV(7)  /* External Reset Diasble */
1118#define HFUSE_DEFAULT (FUSE_SPIEN)
1119
1120/* Extended Fuse Byte */
1121#define FUSE_BOOTRST     (unsigned char)~_BV(0)
1122#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
1123#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
1124#define FUSE_PSCRV       (unsigned char)~_BV(4)
1125#define FUSE_PSC0RB      (unsigned char)~_BV(5)
1126#define FUSE_PSC2RB      (unsigned char)~_BV(7)
1127#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
1128
1129
1130/* Lock Bits */
1131#define __LOCK_BITS_EXIST
1132#define __BOOT_LOCK_BITS_0_EXIST
1133#define __BOOT_LOCK_BITS_1_EXIST
1134
1135/** @} */
1136
1137#endif /* _AVR_IOPWM1_H_ */
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