source: rtems/cpukit/score/cpu/avr/avr/io86r401.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/* Copyright (c) 2002, Colin O'Flynn
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* avr/io86r401.h - definitions for AT86RF401 */
32
33#ifndef _AVR_IO86RF401_H_
34#define _AVR_IO86RF401_H_ 1
35
36/* This file should only be included from <avr/io.h>, never directly. */
37
38#ifndef _AVR_IO_H_
39#  error "Include <avr/io.h> instead of this file."
40#endif
41
42#ifndef _AVR_IOXXX_H_
43#  define _AVR_IOXXX_H_ "io86r401.h"
44#else
45#  error "Attempt to include more than one <avr/ioXXX.h> file."
46#endif
47
48#include <avr/sfr_defs.h>
49
50/* Status REGister */
51#define SREG    _SFR_IO8(0x3F)
52
53/* Stack Pointer */
54#define SP      _SFR_IO16(0x3D)
55#define SPH     _SFR_IO8(0x3E)
56#define SPL     _SFR_IO8(0x3D)
57
58/*Battery low configeration register */
59#define BL_CONFIG       _SFR_IO8(0x35)
60
61/*Button detect register*/
62#define B_DET           _SFR_IO8(0x34)
63
64/*AVR Configeration register*/
65#define AVR_CONFIG      _SFR_IO8(0x33)
66
67/* I/O registers */
68
69/*Data in register */
70#define IO_DATIN        _SFR_IO8(0x32)
71
72/*Data out register */
73#define IO_DATOUT       _SFR_IO8(0x31)
74
75/*IO Enable register */
76#define IO_ENAB         _SFR_IO8(0x30)
77
78/* Watchdog Timer Control Register */
79#define WDTCR           _SFR_IO8(0x22)
80
81/* Bit Timer Control Register */
82#define BTCR            _SFR_IO8(0x21)
83
84#define BTCNT           _SFR_IO8(0x20)
85
86/*
87NOTE: EEPROM name's changed to have D in front on them, per datasheet, but
88you may want to remove the leading D.
89*/
90/* EEPROM Control Register */
91
92/* EEPROM Address Register */
93#define DEEAR           _SFR_IO8(0x1E)
94#define DEEARL          _SFR_IO8(0x1E)
95
96/* EEPROM Data Register */
97#define DEEDR           _SFR_IO8(0x1D)
98/* EEPROM Control Register */
99#define DEECR           _SFR_IO8(0x1C)
100
101/* Lock Detector Configuration Register 2 */
102#define LOCKDET2        _SFR_IO8(0x17)
103
104/* VCO Tuning Register*/
105#define VCOTUNE         _SFR_IO8(0x16)
106
107/* Power Attenuation Control Register */
108#define PWR_ATTEN       _SFR_IO8(0x14)
109
110/* Transmitter Control Register */
111#define TX_CNTL         _SFR_IO8(0x12)
112
113/* Lock Detector Configuration Register 1 */
114#define LOCKDET1        _SFR_IO8(0x10)
115
116
117/* Interrupt vectors */
118
119/* Transmission Done, Bit Timer Flag 2 Interrupt */
120#define TXDONE_vect                     _VECTOR(1)
121#define SIG_TXDONE                      _VECTOR(1)
122
123/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */
124#define TXEMPTY_vect                    _VECTOR(2)
125#define SIG_TXBE                        _VECTOR(2)
126
127#define _VECTORS_SIZE 12
128
129/*
130 *  The Register Bit names are represented by their bit number (0-7).
131 */
132
133/* Lock Detector Configuration Register 1 - LOCKDET1 */
134#define UPOK    4
135#define ENKO    3
136#define BOD     2
137#define CS1     1
138#define CS0     0
139
140/* Transmit Control Register - TX_CNTL */
141#define TXE     5
142#define TXK     4
143#define LOC     2
144
145/* Power Attenuation Control Register - PWR_ATTEN */
146#define PCC2        5
147#define PCC1        4
148#define PCC0        3
149#define PCF2        2
150#define PCF1        1
151#define PCF0        0
152
153/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/
154#define VCOVDET1        7
155#define VCOVDET0        6
156#define VCOTUNE4        4
157#define VCOTUNE3        3
158#define VCOTUNE2        2
159#define VCOTUNE1        1
160#define VCOTUNE0        0
161
162/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/
163#define EUD         7
164#define LAT         6
165#define ULC2        5
166#define ULC1        4
167#define ULC0        3
168#define LC2         2
169#define LC1         1
170#define LC0         0
171
172/* Data EEPROM Control Register - DEECR */
173#define BSY         3
174#define EEU         2
175#define EEL         1
176#define EER         0
177
178/* Data EEPROM Data Register - DEEDR */
179#define ED7         7
180#define ED6         6
181#define ED5         5
182#define ED4         4
183#define ED3         3
184#define ED2         2
185#define ED1         1
186#define ED0         0
187
188/* Data EEPROM Address Register - DEEAR */
189#define PA6     6
190#define PA5     5
191#define PA4     4
192#define PA3     3
193#define BA2     2  /* B is not a typo! */
194#define BA1     1
195#define BA0     0
196
197/* Bit Timer Count Register - BTCNT */
198#define C7      7
199#define C6      6
200#define C5      5
201#define C4      4
202#define C3      3
203#define C2      2
204#define C1      1
205#define C0      0
206
207/* Bit Timer Control Register - BTCR */
208#define C9      7
209#define C8      6
210#define M1      5
211#define M0      4
212#define IE      3
213#define F2      2
214#define DATA    1
215#define F0      0
216
217/* Watchdog Timer Control Register - WDTCR */
218#define WDTOE       4
219#define WDE         3
220#define WDP2        2
221#define WDP1        1
222#define WDP0        0
223
224/* I/O Enable Register - IO_ENAB */
225#define BOHYST      6
226#define IOE5        5
227#define IOE4        4
228#define IOE3        3
229#define IOE2        2
230#define IOE1        1
231#define IOE0        0
232
233/* Note: No PORTB or whatever, this is the equivalent. */
234/* I/O Data Out Register - IO_DATOUT */
235#define IOO5     5
236#define IOO4     4
237#define IOO3     3
238#define IOO2     2
239#define IOO1     1
240#define IOO0     0
241
242/* Note: No PINB or whatever, this is the equivalent. */
243/* I/O Data In Register - IO_DATIN */
244#define IOI5     5
245#define IOI4     4
246#define IOI3     3
247#define IOI2     2
248#define IOI1     1
249#define IOI0     0
250
251/* AVR Configuration Register - AVR_CONFIG */
252#define ACS1    6
253#define ACS0    5
254#define TM      4
255#define BD      3
256#define BLI     2
257#define SLEEP   1
258#define BBM     0
259
260/* Button Detect Register - B_DET */
261#define BD5     5
262#define BD4     4
263#define BD3     3
264#define BD2     2
265#define BD1     1
266#define BD0     0
267
268/* Battery Low Configuration Register - BL_CONFIG */
269#define BL      7
270#define BLV     6
271#define BL5     5
272#define BL4     4
273#define BL3     3
274#define BL2     2
275#define BL1     1
276#define BL0     0
277
278/* Pointer definition   */
279#define XL      r26
280#define XH      r27
281#define YL      r28
282#define YH      r29
283#define ZL      r30
284#define ZH      r31
285
286/* Constants */
287#define RAMEND      0xDF
288#define XRAMEND     RAMEND
289#define E2END       0x7F
290#define E2PAGESIZE  0
291#define FLASHEND    0x07FF
292
293
294/* Fuses */
295#define FUSE_MEMORY_SIZE 0
296
297
298/* Lock Bits */
299#define __LOCK_BITS_EXIST
300
301
302/* Signature */
303#define SIGNATURE_0 0x1E
304#define SIGNATURE_1 0x91
305#define SIGNATURE_2 0x81
306
307
308#endif  /* _AVR_IO86RF401_H_ */
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