1 | /** |
---|
2 | * @file avr/io8535.h |
---|
3 | * |
---|
4 | * @brief Definitions for AT90S8535 |
---|
5 | * |
---|
6 | * This file should only be included from <avr/io.h>, never directly. |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * Copyright (c) 2002, Marek Michalkiewicz |
---|
11 | * All rights reserved. |
---|
12 | * |
---|
13 | * Redistribution and use in source and binary forms, with or without |
---|
14 | * modification, are permitted provided that the following conditions are met: |
---|
15 | * |
---|
16 | * * Redistributions of source code must retain the above copyright |
---|
17 | * notice, this list of conditions and the following disclaimer. |
---|
18 | * |
---|
19 | * * Redistributions in binary form must reproduce the above copyright |
---|
20 | * notice, this list of conditions and the following disclaimer in |
---|
21 | * the documentation and/or other materials provided with the |
---|
22 | * distribution. |
---|
23 | * |
---|
24 | * * Neither the name of the copyright holders nor the names of |
---|
25 | * contributors may be used to endorse or promote products derived |
---|
26 | * from this software without specific prior written permission. |
---|
27 | * |
---|
28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
---|
29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
---|
30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
---|
31 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
---|
32 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
---|
33 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
---|
34 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
---|
35 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
---|
36 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
---|
37 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
---|
38 | * POSSIBILITY OF SUCH DAMAGE. |
---|
39 | */ |
---|
40 | |
---|
41 | #ifndef _AVR_IO8535_H_ |
---|
42 | #define _AVR_IO8535_H_ 1 |
---|
43 | |
---|
44 | #ifndef _AVR_IO_H_ |
---|
45 | # error "Include <avr/io.h> instead of this file." |
---|
46 | #endif |
---|
47 | |
---|
48 | #ifndef _AVR_IOXXX_H_ |
---|
49 | # define _AVR_IOXXX_H_ "io8535.h" |
---|
50 | #else |
---|
51 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
---|
52 | #endif |
---|
53 | |
---|
54 | /** |
---|
55 | * @defgroup AvrDef_io8535 AT90S8535 Definitions |
---|
56 | * |
---|
57 | * @ingroup avr |
---|
58 | * |
---|
59 | */ |
---|
60 | /**@{**/ |
---|
61 | |
---|
62 | /* I/O registers */ |
---|
63 | |
---|
64 | /* ADC Data register */ |
---|
65 | #ifndef __ASSEMBLER__ |
---|
66 | #define ADC _SFR_IO16(0x04) |
---|
67 | #endif |
---|
68 | #define ADCW _SFR_IO16(0x04) |
---|
69 | #define ADCL _SFR_IO8(0x04) |
---|
70 | #define ADCH _SFR_IO8(0x05) |
---|
71 | |
---|
72 | /* ADC Control and Status Register */ |
---|
73 | #define ADCSR _SFR_IO8(0x06) |
---|
74 | |
---|
75 | /* ADC MUX */ |
---|
76 | #define ADMUX _SFR_IO8(0x07) |
---|
77 | |
---|
78 | /* Analog Comparator Control and Status Register */ |
---|
79 | #define ACSR _SFR_IO8(0x08) |
---|
80 | |
---|
81 | /* UART Baud Rate Register */ |
---|
82 | #define UBRR _SFR_IO8(0x09) |
---|
83 | |
---|
84 | /* UART Control Register */ |
---|
85 | #define UCR _SFR_IO8(0x0A) |
---|
86 | |
---|
87 | /* UART Status Register */ |
---|
88 | #define USR _SFR_IO8(0x0B) |
---|
89 | |
---|
90 | /* UART I/O Data Register */ |
---|
91 | #define UDR _SFR_IO8(0x0C) |
---|
92 | |
---|
93 | /* SPI Control Register */ |
---|
94 | #define SPCR _SFR_IO8(0x0D) |
---|
95 | |
---|
96 | /* SPI Status Register */ |
---|
97 | #define SPSR _SFR_IO8(0x0E) |
---|
98 | |
---|
99 | /* SPI I/O Data Register */ |
---|
100 | #define SPDR _SFR_IO8(0x0F) |
---|
101 | |
---|
102 | /* Input Pins, Port D */ |
---|
103 | #define PIND _SFR_IO8(0x10) |
---|
104 | |
---|
105 | /* Data Direction Register, Port D */ |
---|
106 | #define DDRD _SFR_IO8(0x11) |
---|
107 | |
---|
108 | /* Data Register, Port D */ |
---|
109 | #define PORTD _SFR_IO8(0x12) |
---|
110 | |
---|
111 | /* Input Pins, Port C */ |
---|
112 | #define PINC _SFR_IO8(0x13) |
---|
113 | |
---|
114 | /* Data Direction Register, Port C */ |
---|
115 | #define DDRC _SFR_IO8(0x14) |
---|
116 | |
---|
117 | /* Data Register, Port C */ |
---|
118 | #define PORTC _SFR_IO8(0x15) |
---|
119 | |
---|
120 | /* Input Pins, Port B */ |
---|
121 | #define PINB _SFR_IO8(0x16) |
---|
122 | |
---|
123 | /* Data Direction Register, Port B */ |
---|
124 | #define DDRB _SFR_IO8(0x17) |
---|
125 | |
---|
126 | /* Data Register, Port B */ |
---|
127 | #define PORTB _SFR_IO8(0x18) |
---|
128 | |
---|
129 | /* Input Pins, Port A */ |
---|
130 | #define PINA _SFR_IO8(0x19) |
---|
131 | |
---|
132 | /* Data Direction Register, Port A */ |
---|
133 | #define DDRA _SFR_IO8(0x1A) |
---|
134 | |
---|
135 | /* Data Register, Port A */ |
---|
136 | #define PORTA _SFR_IO8(0x1B) |
---|
137 | |
---|
138 | /* EEPROM Control Register */ |
---|
139 | #define EECR _SFR_IO8(0x1C) |
---|
140 | |
---|
141 | /* EEPROM Data Register */ |
---|
142 | #define EEDR _SFR_IO8(0x1D) |
---|
143 | |
---|
144 | /* EEPROM Address Register */ |
---|
145 | #define EEAR _SFR_IO16(0x1E) |
---|
146 | #define EEARL _SFR_IO8(0x1E) |
---|
147 | #define EEARH _SFR_IO8(0x1F) |
---|
148 | |
---|
149 | /* Watchdog Timer Control Register */ |
---|
150 | #define WDTCR _SFR_IO8(0x21) |
---|
151 | |
---|
152 | /* Asynchronous mode Status Register */ |
---|
153 | #define ASSR _SFR_IO8(0x22) |
---|
154 | |
---|
155 | /* Timer/Counter2 Output Compare Register */ |
---|
156 | #define OCR2 _SFR_IO8(0x23) |
---|
157 | |
---|
158 | /* Timer/Counter 2 */ |
---|
159 | #define TCNT2 _SFR_IO8(0x24) |
---|
160 | |
---|
161 | /* Timer/Counter 2 Control Register */ |
---|
162 | #define TCCR2 _SFR_IO8(0x25) |
---|
163 | |
---|
164 | /* T/C 1 Input Capture Register */ |
---|
165 | #define ICR1 _SFR_IO16(0x26) |
---|
166 | #define ICR1L _SFR_IO8(0x26) |
---|
167 | #define ICR1H _SFR_IO8(0x27) |
---|
168 | |
---|
169 | /* Timer/Counter1 Output Compare Register B */ |
---|
170 | #define OCR1B _SFR_IO16(0x28) |
---|
171 | #define OCR1BL _SFR_IO8(0x28) |
---|
172 | #define OCR1BH _SFR_IO8(0x29) |
---|
173 | |
---|
174 | /* Timer/Counter1 Output Compare Register A */ |
---|
175 | #define OCR1A _SFR_IO16(0x2A) |
---|
176 | #define OCR1AL _SFR_IO8(0x2A) |
---|
177 | #define OCR1AH _SFR_IO8(0x2B) |
---|
178 | |
---|
179 | /* Timer/Counter 1 */ |
---|
180 | #define TCNT1 _SFR_IO16(0x2C) |
---|
181 | #define TCNT1L _SFR_IO8(0x2C) |
---|
182 | #define TCNT1H _SFR_IO8(0x2D) |
---|
183 | |
---|
184 | /* Timer/Counter 1 Control and Status Register */ |
---|
185 | #define TCCR1B _SFR_IO8(0x2E) |
---|
186 | |
---|
187 | /* Timer/Counter 1 Control Register */ |
---|
188 | #define TCCR1A _SFR_IO8(0x2F) |
---|
189 | |
---|
190 | /* Timer/Counter 0 */ |
---|
191 | #define TCNT0 _SFR_IO8(0x32) |
---|
192 | |
---|
193 | /* Timer/Counter 0 Control Register */ |
---|
194 | #define TCCR0 _SFR_IO8(0x33) |
---|
195 | |
---|
196 | /* MCU general Status Register */ |
---|
197 | #define MCUSR _SFR_IO8(0x34) |
---|
198 | |
---|
199 | /* MCU general Control Register */ |
---|
200 | #define MCUCR _SFR_IO8(0x35) |
---|
201 | |
---|
202 | /* Timer/Counter Interrupt Flag register */ |
---|
203 | #define TIFR _SFR_IO8(0x38) |
---|
204 | |
---|
205 | /* Timer/Counter Interrupt MaSK register */ |
---|
206 | #define TIMSK _SFR_IO8(0x39) |
---|
207 | |
---|
208 | /* General Interrupt Flag Register */ |
---|
209 | #define GIFR _SFR_IO8(0x3A) |
---|
210 | |
---|
211 | /* General Interrupt MaSK register */ |
---|
212 | #define GIMSK _SFR_IO8(0x3B) |
---|
213 | |
---|
214 | /* 0x3D..0x3E SP */ |
---|
215 | |
---|
216 | /* 0x3F SREG */ |
---|
217 | |
---|
218 | /* Interrupt vectors */ |
---|
219 | |
---|
220 | /* External Interrupt 0 */ |
---|
221 | #define INT0_vect _VECTOR(1) |
---|
222 | #define SIG_INTERRUPT0 _VECTOR(1) |
---|
223 | |
---|
224 | /* External Interrupt 1 */ |
---|
225 | #define INT1_vect _VECTOR(2) |
---|
226 | #define SIG_INTERRUPT1 _VECTOR(2) |
---|
227 | |
---|
228 | /* Timer/Counter2 Compare Match */ |
---|
229 | #define TIMER2_COMP_vect _VECTOR(3) |
---|
230 | #define SIG_OUTPUT_COMPARE2 _VECTOR(3) |
---|
231 | |
---|
232 | /* Timer/Counter2 Overflow */ |
---|
233 | #define TIMER2_OVF_vect _VECTOR(4) |
---|
234 | #define SIG_OVERFLOW2 _VECTOR(4) |
---|
235 | |
---|
236 | /* Timer/Counter1 Capture Event */ |
---|
237 | #define TIMER1_CAPT_vect _VECTOR(5) |
---|
238 | #define SIG_INPUT_CAPTURE1 _VECTOR(5) |
---|
239 | |
---|
240 | /* Timer/Counter1 Compare Match A */ |
---|
241 | #define TIMER1_COMPA_vect _VECTOR(6) |
---|
242 | #define SIG_OUTPUT_COMPARE1A _VECTOR(6) |
---|
243 | |
---|
244 | /* Timer/Counter1 Compare Match B */ |
---|
245 | #define TIMER1_COMPB_vect _VECTOR(7) |
---|
246 | #define SIG_OUTPUT_COMPARE1B _VECTOR(7) |
---|
247 | |
---|
248 | /* Timer/Counter1 Overflow */ |
---|
249 | #define TIMER1_OVF_vect _VECTOR(8) |
---|
250 | #define SIG_OVERFLOW1 _VECTOR(8) |
---|
251 | |
---|
252 | /* Timer/Counter0 Overflow */ |
---|
253 | #define TIMER0_OVF_vect _VECTOR(9) |
---|
254 | #define SIG_OVERFLOW0 _VECTOR(9) |
---|
255 | |
---|
256 | /* SPI Serial Transfer Complete */ |
---|
257 | #define SPI_STC_vect _VECTOR(10) |
---|
258 | #define SIG_SPI _VECTOR(10) |
---|
259 | |
---|
260 | /* UART, RX Complete */ |
---|
261 | #define UART_RX_vect _VECTOR(11) |
---|
262 | #define SIG_UART_RECV _VECTOR(11) |
---|
263 | |
---|
264 | /* UART Data Register Empty */ |
---|
265 | #define UART_UDRE_vect _VECTOR(12) |
---|
266 | #define SIG_UART_DATA _VECTOR(12) |
---|
267 | |
---|
268 | /* UART, TX Complete */ |
---|
269 | #define UART_TX_vect _VECTOR(13) |
---|
270 | #define SIG_UART_TRANS _VECTOR(13) |
---|
271 | |
---|
272 | /* ADC Conversion Complete */ |
---|
273 | #define ADC_vect _VECTOR(14) |
---|
274 | #define SIG_ADC _VECTOR(14) |
---|
275 | |
---|
276 | /* EEPROM Ready */ |
---|
277 | #define EE_RDY_vect _VECTOR(15) |
---|
278 | #define SIG_EEPROM_READY _VECTOR(15) |
---|
279 | |
---|
280 | /* Analog Comparator */ |
---|
281 | #define ANA_COMP_vect _VECTOR(16) |
---|
282 | #define SIG_COMPARATOR _VECTOR(16) |
---|
283 | |
---|
284 | #define _VECTORS_SIZE 34 |
---|
285 | |
---|
286 | /* |
---|
287 | The Register Bit names are represented by their bit number (0-7). |
---|
288 | */ |
---|
289 | |
---|
290 | /* MCU general Status Register */ |
---|
291 | #define EXTRF 1 |
---|
292 | #define PORF 0 |
---|
293 | |
---|
294 | /* General Interrupt MaSK register */ |
---|
295 | #define INT1 7 |
---|
296 | #define INT0 6 |
---|
297 | |
---|
298 | /* General Interrupt Flag Register */ |
---|
299 | #define INTF1 7 |
---|
300 | #define INTF0 6 |
---|
301 | |
---|
302 | /* Timer/Counter Interrupt MaSK register */ |
---|
303 | #define OCIE2 7 |
---|
304 | #define TOIE2 6 |
---|
305 | #define TICIE1 5 |
---|
306 | #define OCIE1A 4 |
---|
307 | #define OCIE1B 3 |
---|
308 | #define TOIE1 2 |
---|
309 | #define TOIE0 0 |
---|
310 | |
---|
311 | /* Timer/Counter Interrupt Flag register */ |
---|
312 | #define OCF2 7 |
---|
313 | #define TOV2 6 |
---|
314 | #define ICF1 5 |
---|
315 | #define OCF1A 4 |
---|
316 | #define OCF1B 3 |
---|
317 | #define TOV1 2 |
---|
318 | #define TOV0 0 |
---|
319 | |
---|
320 | /* MCU general Control Register */ |
---|
321 | #define SE 6 |
---|
322 | #define SM1 5 |
---|
323 | #define SM0 4 |
---|
324 | #define ISC11 3 |
---|
325 | #define ISC10 2 |
---|
326 | #define ISC01 1 |
---|
327 | #define ISC00 0 |
---|
328 | |
---|
329 | /* Timer/Counter 0 Control Register */ |
---|
330 | #define CS02 2 |
---|
331 | #define CS01 1 |
---|
332 | #define CS00 0 |
---|
333 | |
---|
334 | /* Timer/Counter 1 Control Register */ |
---|
335 | #define COM1A1 7 |
---|
336 | #define COM1A0 6 |
---|
337 | #define COM1B1 5 |
---|
338 | #define COM1B0 4 |
---|
339 | #define PWM11 1 |
---|
340 | #define PWM10 0 |
---|
341 | |
---|
342 | /* Timer/Counter 1 Control and Status Register */ |
---|
343 | #define ICNC1 7 |
---|
344 | #define ICES1 6 |
---|
345 | #define CTC1 3 |
---|
346 | #define CS12 2 |
---|
347 | #define CS11 1 |
---|
348 | #define CS10 0 |
---|
349 | |
---|
350 | /* Timer/Counter 2 Control Register */ |
---|
351 | #define PWM2 6 |
---|
352 | #define COM21 5 |
---|
353 | #define COM20 4 |
---|
354 | #define CTC2 3 |
---|
355 | #define CS22 2 |
---|
356 | #define CS21 1 |
---|
357 | #define CS20 0 |
---|
358 | |
---|
359 | /* Asynchronous mode Status Register */ |
---|
360 | #define AS2 3 |
---|
361 | #define TCN2UB 2 |
---|
362 | #define OCR2UB 1 |
---|
363 | #define TCR2UB 0 |
---|
364 | |
---|
365 | /* Watchdog Timer Control Register */ |
---|
366 | #define WDTOE 4 |
---|
367 | #define WDE 3 |
---|
368 | #define WDP2 2 |
---|
369 | #define WDP1 1 |
---|
370 | #define WDP0 0 |
---|
371 | |
---|
372 | /* Data Register, Port A */ |
---|
373 | #define PA7 7 |
---|
374 | #define PA6 6 |
---|
375 | #define PA5 5 |
---|
376 | #define PA4 4 |
---|
377 | #define PA3 3 |
---|
378 | #define PA2 2 |
---|
379 | #define PA1 1 |
---|
380 | #define PA0 0 |
---|
381 | |
---|
382 | /* Data Direction Register, Port A */ |
---|
383 | #define DDA7 7 |
---|
384 | #define DDA6 6 |
---|
385 | #define DDA5 5 |
---|
386 | #define DDA4 4 |
---|
387 | #define DDA3 3 |
---|
388 | #define DDA2 2 |
---|
389 | #define DDA1 1 |
---|
390 | #define DDA0 0 |
---|
391 | |
---|
392 | /* Input Pins, Port A */ |
---|
393 | #define PINA7 7 |
---|
394 | #define PINA6 6 |
---|
395 | #define PINA5 5 |
---|
396 | #define PINA4 4 |
---|
397 | #define PINA3 3 |
---|
398 | #define PINA2 2 |
---|
399 | #define PINA1 1 |
---|
400 | #define PINA0 0 |
---|
401 | |
---|
402 | /* Data Register, Port B */ |
---|
403 | #define PB7 7 |
---|
404 | #define PB6 6 |
---|
405 | #define PB5 5 |
---|
406 | #define PB4 4 |
---|
407 | #define PB3 3 |
---|
408 | #define PB2 2 |
---|
409 | #define PB1 1 |
---|
410 | #define PB0 0 |
---|
411 | |
---|
412 | /* Data Direction Register, Port B */ |
---|
413 | #define DDB7 7 |
---|
414 | #define DDB6 6 |
---|
415 | #define DDB5 5 |
---|
416 | #define DDB4 4 |
---|
417 | #define DDB3 3 |
---|
418 | #define DDB2 2 |
---|
419 | #define DDB1 1 |
---|
420 | #define DDB0 0 |
---|
421 | |
---|
422 | /* Input Pins, Port B */ |
---|
423 | #define PINB7 7 |
---|
424 | #define PINB6 6 |
---|
425 | #define PINB5 5 |
---|
426 | #define PINB4 4 |
---|
427 | #define PINB3 3 |
---|
428 | #define PINB2 2 |
---|
429 | #define PINB1 1 |
---|
430 | #define PINB0 0 |
---|
431 | |
---|
432 | /* Data Register, Port C */ |
---|
433 | #define PC7 7 |
---|
434 | #define PC6 6 |
---|
435 | #define PC5 5 |
---|
436 | #define PC4 4 |
---|
437 | #define PC3 3 |
---|
438 | #define PC2 2 |
---|
439 | #define PC1 1 |
---|
440 | #define PC0 0 |
---|
441 | |
---|
442 | /* Data Direction Register, Port C */ |
---|
443 | #define DDC7 7 |
---|
444 | #define DDC6 6 |
---|
445 | #define DDC5 5 |
---|
446 | #define DDC4 4 |
---|
447 | #define DDC3 3 |
---|
448 | #define DDC2 2 |
---|
449 | #define DDC1 1 |
---|
450 | #define DDC0 0 |
---|
451 | |
---|
452 | /* Input Pins, Port C */ |
---|
453 | #define PINC7 7 |
---|
454 | #define PINC6 6 |
---|
455 | #define PINC5 5 |
---|
456 | #define PINC4 4 |
---|
457 | #define PINC3 3 |
---|
458 | #define PINC2 2 |
---|
459 | #define PINC1 1 |
---|
460 | #define PINC0 0 |
---|
461 | |
---|
462 | /* Data Register, Port D */ |
---|
463 | #define PD7 7 |
---|
464 | #define PD6 6 |
---|
465 | #define PD5 5 |
---|
466 | #define PD4 4 |
---|
467 | #define PD3 3 |
---|
468 | #define PD2 2 |
---|
469 | #define PD1 1 |
---|
470 | #define PD0 0 |
---|
471 | |
---|
472 | /* Data Direction Register, Port D */ |
---|
473 | #define DDD7 7 |
---|
474 | #define DDD6 6 |
---|
475 | #define DDD5 5 |
---|
476 | #define DDD4 4 |
---|
477 | #define DDD3 3 |
---|
478 | #define DDD2 2 |
---|
479 | #define DDD1 1 |
---|
480 | #define DDD0 0 |
---|
481 | |
---|
482 | /* Input Pins, Port D */ |
---|
483 | #define PIND7 7 |
---|
484 | #define PIND6 6 |
---|
485 | #define PIND5 5 |
---|
486 | #define PIND4 4 |
---|
487 | #define PIND3 3 |
---|
488 | #define PIND2 2 |
---|
489 | #define PIND1 1 |
---|
490 | #define PIND0 0 |
---|
491 | |
---|
492 | /* SPI Control Register */ |
---|
493 | #define SPIE 7 |
---|
494 | #define SPE 6 |
---|
495 | #define DORD 5 |
---|
496 | #define MSTR 4 |
---|
497 | #define CPOL 3 |
---|
498 | #define CPHA 2 |
---|
499 | #define SPR1 1 |
---|
500 | #define SPR0 0 |
---|
501 | |
---|
502 | /* SPI Status Register */ |
---|
503 | #define SPIF 7 |
---|
504 | #define WCOL 6 |
---|
505 | |
---|
506 | /* UART Status Register */ |
---|
507 | #define RXC 7 |
---|
508 | #define TXC 6 |
---|
509 | #define UDRE 5 |
---|
510 | #define FE 4 |
---|
511 | #define DOR 3 |
---|
512 | |
---|
513 | /* UART Control Register */ |
---|
514 | #define RXCIE 7 |
---|
515 | #define TXCIE 6 |
---|
516 | #define UDRIE 5 |
---|
517 | #define RXEN 4 |
---|
518 | #define TXEN 3 |
---|
519 | #define CHR9 2 |
---|
520 | #define RXB8 1 |
---|
521 | #define TXB8 0 |
---|
522 | |
---|
523 | /* Analog Comparator Control and Status Register */ |
---|
524 | #define ACD 7 |
---|
525 | #define ACO 5 |
---|
526 | #define ACI 4 |
---|
527 | #define ACIE 3 |
---|
528 | #define ACIC 2 |
---|
529 | #define ACIS1 1 |
---|
530 | #define ACIS0 0 |
---|
531 | |
---|
532 | /* ADC MUX */ |
---|
533 | #define MUX2 2 |
---|
534 | #define MUX1 1 |
---|
535 | #define MUX0 0 |
---|
536 | |
---|
537 | /* ADC Control and Status Register */ |
---|
538 | #define ADEN 7 |
---|
539 | #define ADSC 6 |
---|
540 | #define ADFR 5 |
---|
541 | #define ADIF 4 |
---|
542 | #define ADIE 3 |
---|
543 | #define ADPS2 2 |
---|
544 | #define ADPS1 1 |
---|
545 | #define ADPS0 0 |
---|
546 | |
---|
547 | /* EEPROM Control Register */ |
---|
548 | #define EERIE 3 |
---|
549 | #define EEMWE 2 |
---|
550 | #define EEWE 1 |
---|
551 | #define EERE 0 |
---|
552 | |
---|
553 | /* Constants */ |
---|
554 | #define RAMEND 0x25F /*Last On-Chip SRAM location*/ |
---|
555 | #define XRAMEND RAMEND |
---|
556 | #define E2END 0x1FF |
---|
557 | #define E2PAGESIZE 0 |
---|
558 | #define FLASHEND 0x1FFF |
---|
559 | |
---|
560 | |
---|
561 | /* Fuses */ |
---|
562 | #define FUSE_MEMORY_SIZE 1 |
---|
563 | |
---|
564 | /* Low Fuse Byte */ |
---|
565 | #define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ |
---|
566 | #define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ |
---|
567 | #define LFUSE_DEFAULT (0xFF) |
---|
568 | |
---|
569 | |
---|
570 | /* Lock Bits */ |
---|
571 | #define __LOCK_BITS_EXIST |
---|
572 | |
---|
573 | |
---|
574 | /* Signature */ |
---|
575 | #define SIGNATURE_0 0x1E |
---|
576 | #define SIGNATURE_1 0x93 |
---|
577 | #define SIGNATURE_2 0x03 |
---|
578 | |
---|
579 | /** @} */ |
---|
580 | #endif /* _AVR_IO8535_H_ */ |
---|