source: rtems/cpukit/score/cpu/avr/avr/io8534.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 4.7 KB
Line 
1/* Copyright (c) 2002, Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/io8534.h - definitions for AT90C8534 */
34
35#ifndef _AVR_IO8534_
36#define _AVR_IO8534_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "io8534.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* 0x00..0x03 reserved */
53
54/* ADC Data Register */
55#ifndef __ASSEMBLER__
56#define ADC     _SFR_IO16(0x04)
57#endif
58#define ADCW    _SFR_IO16(0x04)
59#define ADCL    _SFR_IO8(0x04)
60#define ADCH    _SFR_IO8(0x05)
61
62/* ADC Control and Status Register */
63#define ADCSR   _SFR_IO8(0x06)
64
65/* ADC Multiplexer Select Register */
66#define ADMUX   _SFR_IO8(0x07)
67
68/* 0x08..0x0F reserved */
69
70/* General Interrupt Pin Register */
71#define GIPR    _SFR_IO8(0x10)
72
73/* 0x11..0x19 reserved */
74
75/* Data Direction Register, Port A */
76#define DDRA    _SFR_IO8(0x1A)
77
78/* Data Register, Port A */
79#define PORTA   _SFR_IO8(0x1B)
80
81/* EEPROM Control Register */
82#define EECR    _SFR_IO8(0x1C)
83
84/* EEPROM Data Register */
85#define EEDR    _SFR_IO8(0x1D)
86
87/* EEPROM Address Register */
88#define EEAR    _SFR_IO16(0x1E)
89#define EEARL   _SFR_IO8(0x1E)
90#define EEARH   _SFR_IO8(0x1F)
91
92/* 0x20..0x2B reserved */
93
94/* Timer/Counter1 */
95#define TCNT1   _SFR_IO16(0x2C)
96#define TCNT1L  _SFR_IO8(0x2C)
97#define TCNT1H  _SFR_IO8(0x2D)
98
99/* Timer/Counter1 Control Register */
100#define TCCR1   _SFR_IO8(0x2E)
101
102/* 0x2F..0x31 reserved */
103
104/* Timer/Counter0 (8-bit) */
105#define TCNT0   _SFR_IO8(0x32)
106
107/* Timer/Counter0 Control Register */
108#define TCCR0   _SFR_IO8(0x33)
109
110/* 0x34 reserved */
111
112/* MCU general Control Register */
113#define MCUCR   _SFR_IO8(0x35)
114
115/* 0x36..0x37 reserved */
116
117/* Timer/Counter Interrupt Flag Register */
118#define TIFR    _SFR_IO8(0x38)
119
120/* Timer/Counter Interrupt MaSK Register */
121#define TIMSK   _SFR_IO8(0x39)
122
123/* General Interrupt Flag Register */
124#define GIFR    _SFR_IO8(0x3A)
125
126/* General Interrupt MaSK register */
127#define GIMSK   _SFR_IO8(0x3B)
128
129/* 0x3C reserved */
130
131/* 0x3D..0x3E SP */
132
133/* 0x3F SREG */
134
135/* Interrupt vectors */
136
137#define SIG_INTERRUPT0          _VECTOR(1)
138#define SIG_INTERRUPT1          _VECTOR(2)
139#define SIG_OVERFLOW1           _VECTOR(3)
140#define SIG_OVERFLOW0           _VECTOR(4)
141#define SIG_ADC                 _VECTOR(5)
142#define SIG_EEPROM_READY        _VECTOR(6)
143
144#define _VECTORS_SIZE 14
145
146/* Bit numbers */
147
148/* GIMSK */
149#define INT1    7
150#define INT0    6
151
152/* GIFR */
153#define INTF1   7
154#define INTF0   6
155
156/* GIPR */
157#define IPIN1   3
158#define IPIN0   2
159
160/* TIMSK */
161#define TOIE1   2
162#define TOIE0   0
163
164/* TIFR */
165#define TOV1    2
166#define TOV0    0
167
168/* MCUCR */
169#define SE      6
170#define SM      5
171#define ISC1    2
172#define ISC0    0
173
174/* TCCR0 */
175#define CS02    2
176#define CS01    1
177#define CS00    0
178
179/* TCCR1 */
180#define CS12    2
181#define CS11    1
182#define CS10    0
183
184/* PORTA */
185#define PA7     7
186#define PA6     6
187#define PA5     5
188#define PA4     4
189#define PA3     3
190#define PA2     2
191#define PA1     1
192#define PA0     0
193
194/* DDRA */
195#define DDA7    7
196#define DDA6    6
197#define DDA5    5
198#define DDA4    4
199#define DDA3    3
200#define DDA2    2
201#define DDA1    1
202#define DDA0    0
203
204/* EEPROM Control Register */
205#define EERIE   3
206#define EEMWE   2
207#define EEWE    1
208#define EERE    0
209
210/* Last memory addresses */
211#define RAMEND          0x15F
212#define XRAMEND         RAMEND
213#define E2END           0x1FF
214#define FLASHEND        0x1FFF
215
216#endif /* _AVR_IO8534_H_ */
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