[04a62dce] | 1 | /* Copyright (c) 2002, Marek Michalkiewicz |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/io76c711.h - definitions for AT76C711 */ |
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| 34 | |
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| 35 | #ifndef _AVR_IO76C711_H_ |
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| 36 | #define _AVR_IO76C711_H_ 1 |
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| 37 | |
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| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 39 | |
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| 40 | #ifndef _AVR_IO_H_ |
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| 41 | # error "Include <avr/io.h> instead of this file." |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifndef _AVR_IOXXX_H_ |
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| 45 | # define _AVR_IOXXX_H_ "io76c711.h" |
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| 46 | #else |
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| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 48 | #endif |
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| 49 | |
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| 50 | /* I/O registers */ |
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| 51 | |
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| 52 | /* 0x00-0x0C reserved */ |
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| 53 | |
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| 54 | /* SPI */ |
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| 55 | #define SPCR _SFR_IO8(0x0D) |
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| 56 | #define SPSR _SFR_IO8(0x0E) |
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| 57 | #define SPDR _SFR_IO8(0x0F) |
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| 58 | |
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| 59 | /* Port D */ |
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| 60 | #define PIND _SFR_IO8(0x10) |
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| 61 | #define DDRD _SFR_IO8(0x11) |
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| 62 | #define PORTD _SFR_IO8(0x12) |
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| 63 | |
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| 64 | /* Peripheral Enable Register */ |
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| 65 | #define PERIPHEN _SFR_IO8(0x13) |
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| 66 | |
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| 67 | /* Clock Control Register */ |
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| 68 | #define CLK_CNTR _SFR_IO8(0x14) |
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| 69 | |
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| 70 | /* Data Register, Port C */ |
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| 71 | #define PORTC _SFR_IO8(0x15) |
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| 72 | |
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| 73 | /* Port B */ |
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| 74 | #define PINB _SFR_IO8(0x16) |
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| 75 | #define DDRB _SFR_IO8(0x17) |
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| 76 | #define PORTB _SFR_IO8(0x18) |
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| 77 | |
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| 78 | /* Port A */ |
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| 79 | #define PINA _SFR_IO8(0x19) |
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| 80 | #define DDRA _SFR_IO8(0x1A) |
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| 81 | #define PORTA _SFR_IO8(0x1B) |
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| 82 | |
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| 83 | /* 0x1C-0x1F reserved */ |
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| 84 | |
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| 85 | #define IRDAMOD _SFR_IO8(0x20) |
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| 86 | |
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| 87 | #define WDTCR _SFR_IO8(0x21) |
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| 88 | |
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| 89 | /* 0x22-0x25 reserved */ |
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| 90 | /* Timer 1 */ |
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| 91 | #define ICR1 _SFR_IO16(0x26) |
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| 92 | #define ICR1L _SFR_IO8(0x26) |
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| 93 | #define ICR1H _SFR_IO8(0x27) |
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| 94 | #define OCR1B _SFR_IO16(0x28) |
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| 95 | #define OCR1BL _SFR_IO8(0x28) |
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| 96 | #define OCR1BH _SFR_IO8(0x29) |
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| 97 | #define OCR1A _SFR_IO16(0x2A) |
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| 98 | #define OCR1AL _SFR_IO8(0x2A) |
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| 99 | #define OCR1AH _SFR_IO8(0x2B) |
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| 100 | #define TCNT1 _SFR_IO16(0x2C) |
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| 101 | #define TCNT1L _SFR_IO8(0x2C) |
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| 102 | #define TCNT1H _SFR_IO8(0x2D) |
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| 103 | #define TCCR1B _SFR_IO8(0x2E) |
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| 104 | #define TCCR1A _SFR_IO8(0x2F) |
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| 105 | |
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| 106 | /* 0x30 reserved */ |
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| 107 | |
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| 108 | /* Timer 0 */ |
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| 109 | #define PRELD _SFR_IO8(0x31) |
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| 110 | #define TCNT0 _SFR_IO8(0x32) |
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| 111 | #define TCCR0 _SFR_IO8(0x33) |
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| 112 | |
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| 113 | #define MCUSR _SFR_IO8(0x34) |
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| 114 | #define MCUCR _SFR_IO8(0x35) |
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| 115 | |
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| 116 | #define TIFR _SFR_IO8(0x36) |
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| 117 | #define TIMSK _SFR_IO8(0x37) |
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| 118 | |
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| 119 | /* 0x38 reserved */ |
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| 120 | |
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| 121 | #define EIMSK _SFR_IO8(0x39) |
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| 122 | |
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| 123 | /* 0x3A-0x3C reserved */ |
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| 124 | |
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| 125 | /* 0x3D..0x3E SP */ |
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| 126 | |
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| 127 | /* 0x3F SREG */ |
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| 128 | |
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| 129 | /* Interrupt vectors */ |
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| 130 | |
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| 131 | #define SIG_SUSPEND_RESUME _VECTOR(1) |
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| 132 | #define SIG_INTERRUPT0 _VECTOR(2) |
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| 133 | #define SIG_INPUT_CAPTURE1 _VECTOR(3) |
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| 134 | #define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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| 135 | #define SIG_OUTPUT_COMPARE1B _VECTOR(5) |
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| 136 | #define SIG_OVERFLOW1 _VECTOR(6) |
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| 137 | #define SIG_OVERFLOW0 _VECTOR(7) |
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| 138 | #define SIG_SPI _VECTOR(8) |
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| 139 | #define SIG_TDMAC _VECTOR(9) |
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| 140 | #define SIG_UART0 _VECTOR(10) |
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| 141 | #define SIG_RDMAC _VECTOR(11) |
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| 142 | #define SIG_USB_HW _VECTOR(12) |
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| 143 | #define SIG_UART1 _VECTOR(13) |
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| 144 | #define SIG_INTERRUPT1 _VECTOR(14) |
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| 145 | |
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| 146 | #define _VECTORS_SIZE 60 |
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| 147 | |
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| 148 | /* Bit numbers */ |
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| 149 | |
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| 150 | /* EIMSK */ |
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| 151 | /* bits 7-4 reserved */ |
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| 152 | #define POL1 3 |
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| 153 | #define POL0 2 |
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| 154 | #define INT1 1 |
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| 155 | #define INT0 0 |
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| 156 | |
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| 157 | /* TIMSK */ |
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| 158 | #define TOIE1 7 |
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| 159 | #define OCIE1A 6 |
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| 160 | #define OCIE1B 5 |
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| 161 | /* bit 4 reserved */ |
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| 162 | #define TICIE1 3 |
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| 163 | /* bit 2 reserved */ |
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| 164 | #define TOIE0 1 |
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| 165 | /* bit 0 reserved */ |
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| 166 | |
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| 167 | /* TIFR */ |
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| 168 | #define TOV1 7 |
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| 169 | #define OCF1A 6 |
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| 170 | #define OCF1B 5 |
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| 171 | /* bit 4 reserved */ |
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| 172 | #define ICF1 3 |
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| 173 | /* bit 2 reserved */ |
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| 174 | #define TOV0 1 |
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| 175 | /* bit 0 reserved */ |
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| 176 | |
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| 177 | /* MCUCR */ |
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| 178 | /* bits 7-6 reserved */ |
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| 179 | #define SE 5 |
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| 180 | #define SM1 4 |
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| 181 | #define SM0 3 |
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| 182 | /* bits 2-0 reserved */ |
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| 183 | |
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| 184 | /* MCUSR */ |
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| 185 | /* bits 7-2 reserved */ |
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| 186 | #define EXTRF 1 |
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| 187 | #define PORF 0 |
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| 188 | |
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| 189 | /* TCCR0 */ |
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| 190 | /* bits 7-6 reserved */ |
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| 191 | #define COM01 5 |
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| 192 | #define COM00 4 |
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| 193 | #define CTC0 3 |
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| 194 | #define CS02 2 |
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| 195 | #define CS01 1 |
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| 196 | #define CS00 0 |
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| 197 | |
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| 198 | /* TCCR1A */ |
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| 199 | #define COM1A1 7 |
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| 200 | #define COM1A0 6 |
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| 201 | #define COM1B1 5 |
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| 202 | #define COM1B0 4 |
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| 203 | /* bits 3-0 reserved */ |
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| 204 | |
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| 205 | /* TCCR1B */ |
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| 206 | #define ICNC1 7 |
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| 207 | #define ICES1 6 |
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| 208 | /* bits 5-4 reserved */ |
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| 209 | #define CTC1 3 |
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| 210 | #define CS12 2 |
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| 211 | #define CS11 1 |
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| 212 | #define CS10 0 |
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| 213 | |
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| 214 | /* WDTCR */ |
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| 215 | /* bits 7-5 reserved */ |
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| 216 | #define WDTOE 4 |
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| 217 | #define WDE 3 |
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| 218 | #define WDP2 2 |
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| 219 | #define WDP1 1 |
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| 220 | #define WDP0 0 |
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| 221 | |
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| 222 | /* IRDAMOD */ |
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| 223 | /* bits 7-3 reserved */ |
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| 224 | #define POL 2 |
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| 225 | #define MODE 1 |
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| 226 | #define EN 0 |
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| 227 | |
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| 228 | /* PORTA */ |
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| 229 | #define PA7 7 |
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| 230 | #define PA6 6 |
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| 231 | #define PA5 5 |
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| 232 | #define PA4 4 |
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| 233 | #define PA3 3 |
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| 234 | #define PA2 2 |
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| 235 | #define PA1 1 |
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| 236 | #define PA0 0 |
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| 237 | |
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| 238 | /* DDRA */ |
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| 239 | #define DDA7 7 |
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| 240 | #define DDA6 6 |
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| 241 | #define DDA5 5 |
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| 242 | #define DDA4 4 |
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| 243 | #define DDA3 3 |
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| 244 | #define DDA2 2 |
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| 245 | #define DDA1 1 |
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| 246 | #define DDA0 0 |
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| 247 | |
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| 248 | /* PINA */ |
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| 249 | #define PINA7 7 |
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| 250 | #define PINA6 6 |
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| 251 | #define PINA5 5 |
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| 252 | #define PINA4 4 |
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| 253 | #define PINA3 3 |
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| 254 | #define PINA2 2 |
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| 255 | #define PINA1 1 |
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| 256 | #define PINA0 0 |
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| 257 | |
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| 258 | /* |
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| 259 | PB7 = SCK |
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| 260 | PB6 = MISO |
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| 261 | PB5 = MOSI |
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| 262 | PB4 = SS# |
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| 263 | PB2 = ICP |
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| 264 | PB1 = T1 |
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| 265 | PB0 = T0 |
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| 266 | */ |
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| 267 | |
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| 268 | /* PORTB */ |
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| 269 | #define PB7 7 |
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| 270 | #define PB6 6 |
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| 271 | #define PB5 5 |
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| 272 | #define PB4 4 |
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| 273 | #define PB3 3 |
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| 274 | #define PB2 2 |
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| 275 | #define PB1 1 |
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| 276 | #define PB0 0 |
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| 277 | |
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| 278 | /* DDRB */ |
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| 279 | #define DDB7 7 |
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| 280 | #define DDB6 6 |
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| 281 | #define DDB5 5 |
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| 282 | #define DDB4 4 |
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| 283 | #define DDB3 3 |
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| 284 | #define DDB2 2 |
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| 285 | #define DDB1 1 |
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| 286 | #define DDB0 0 |
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| 287 | |
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| 288 | /* PINB */ |
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| 289 | #define PINB7 7 |
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| 290 | #define PINB6 6 |
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| 291 | #define PINB5 5 |
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| 292 | #define PINB4 4 |
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| 293 | #define PINB3 3 |
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| 294 | #define PINB2 2 |
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| 295 | #define PINB1 1 |
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| 296 | #define PINB0 0 |
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| 297 | |
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| 298 | /* PORTC */ |
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| 299 | /* bits 7-4 reserved */ |
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| 300 | #define PC3 3 |
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| 301 | #define PC2 2 |
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| 302 | #define PC1 1 |
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| 303 | #define PC0 0 |
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| 304 | |
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| 305 | /* |
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| 306 | PD7 = INT1 / OC1B |
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| 307 | PD6 = INT0 / OC1A |
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| 308 | PD1 = TXD |
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| 309 | PD0 = RXD |
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| 310 | */ |
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| 311 | |
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| 312 | /* PORTD */ |
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| 313 | #define PD7 7 |
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| 314 | #define PD6 6 |
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| 315 | #define PD5 5 |
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| 316 | #define PD4 4 |
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| 317 | #define PD3 3 |
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| 318 | #define PD2 2 |
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| 319 | #define PD1 1 |
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| 320 | #define PD0 0 |
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| 321 | |
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| 322 | /* DDRD */ |
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| 323 | #define DDD7 7 |
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| 324 | #define DDD6 6 |
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| 325 | #define DDD5 5 |
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| 326 | #define DDD4 4 |
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| 327 | #define DDD3 3 |
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| 328 | #define DDD2 2 |
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| 329 | #define DDD1 1 |
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| 330 | #define DDD0 0 |
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| 331 | |
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| 332 | /* PIND */ |
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| 333 | #define PIND7 7 |
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| 334 | #define PIND6 6 |
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| 335 | #define PIND5 5 |
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| 336 | #define PIND4 4 |
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| 337 | #define PIND3 3 |
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| 338 | #define PIND2 2 |
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| 339 | #define PIND1 1 |
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| 340 | #define PIND0 0 |
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| 341 | |
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| 342 | /* CLK_CNTR */ |
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| 343 | /* bits 7-5 reserved */ |
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| 344 | #define UOSC 4 |
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| 345 | #define UCK 3 |
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| 346 | #define IRCK 2 |
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| 347 | /* bits 1-0 reserved */ |
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| 348 | |
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| 349 | /* PERIPHEN */ |
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| 350 | /* bits 7-3 reserved */ |
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| 351 | #define IRDA 2 |
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| 352 | #define UART 1 |
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| 353 | #define USB 0 |
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| 354 | |
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| 355 | /* SPSR */ |
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| 356 | #define SPIF 7 |
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| 357 | #define WCOL 6 |
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| 358 | /* bits 5-0 reserved */ |
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| 359 | |
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| 360 | /* SPCR */ |
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| 361 | #define SPIE 7 |
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| 362 | #define SPE 6 |
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| 363 | #define DORD 5 |
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| 364 | #define MSTR 4 |
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| 365 | #define CPOL 3 |
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| 366 | #define CPHA 2 |
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| 367 | #define SPR1 1 |
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| 368 | #define SPR0 0 |
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| 369 | |
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| 370 | /* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */ |
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| 371 | |
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| 372 | /* UART */ |
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| 373 | #define UART0_BASE 0x2020 |
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| 374 | #define UART1_BASE 0x2030 |
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| 375 | /* offsets from the base address */ |
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| 376 | #define US_RHR 0x00 |
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| 377 | #define US_THR 0x00 |
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| 378 | #define US_IER 0x01 |
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| 379 | #define US_FCR 0x02 |
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| 380 | #define US_PMR 0x03 |
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| 381 | #define US_MR 0x04 |
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| 382 | #define US_CSR 0x05 |
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| 383 | #define US_CR 0x06 |
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| 384 | #define US_BL 0x07 |
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| 385 | #define US_BM 0x08 |
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| 386 | #define US_RTO 0x09 |
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| 387 | #define US_TTG 0x0A |
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| 388 | |
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| 389 | /* DMA */ |
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| 390 | #define DMA_BASE 0x2000 |
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| 391 | /* offsets from the base address */ |
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| 392 | #define TXTADL 0x01 |
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| 393 | #define TXPLL 0x03 |
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| 394 | #define TXPLM 0x04 |
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| 395 | #define TXTPLL 0x05 |
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| 396 | #define TXTPLM 0x06 |
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| 397 | #define RXTADL 0x07 |
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| 398 | #define RXTADMEN 0x08 |
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| 399 | #define RSPLL 0x09 |
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| 400 | #define RXPLM 0x0A |
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| 401 | #define RXTPLL 0x0B |
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| 402 | #define RXTPLM 0x0C |
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| 403 | #define INTCST 0x0D |
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| 404 | /* XXX DPORG register mentioned on page 20, but undocumented */ |
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| 405 | |
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| 406 | /* XXX Program Memory Control Bit mentioned on page 20, but undocumented */ |
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| 407 | #define PROGRAM_MEMORY_CONTROL_BIT 0x2040 |
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| 408 | |
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| 409 | /* USB */ |
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| 410 | #define USB_BASE 0x1000 |
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| 411 | /* offsets from the base address */ |
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| 412 | #define FRM_NUM_H 0x0FD |
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| 413 | #define FRM_NUM_L 0x0FC |
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| 414 | #define GLB_STATE 0x0FB |
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| 415 | #define SPRSR 0x0FA |
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| 416 | #define SPRSIE 0x0F9 |
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| 417 | #define UISR 0x0F7 |
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| 418 | #define UIAR 0x0F5 |
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| 419 | #define FADDR 0x0F2 |
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| 420 | #define ENDPPGPG 0x0F1 |
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| 421 | #define ECR0 0x0EF |
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| 422 | #define ECR1 0x0EE |
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| 423 | #define ECR2 0x0ED |
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| 424 | #define ECR3 0x0EC |
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| 425 | #define ECR4 0x0EB |
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| 426 | #define ECR5 0x0EA |
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| 427 | #define ECR6 0x0E9 |
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| 428 | #define ECR7 0x0E8 |
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| 429 | #define CSR0 0x0DF |
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| 430 | #define CSR1 0x0DE |
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| 431 | #define CSR2 0x0DD |
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| 432 | #define CSR3 0x0DC |
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| 433 | #define CSR4 0x0DB |
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| 434 | #define CSR5 0x0DA |
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| 435 | #define CSR6 0x0D9 |
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| 436 | #define CSR7 0x0D8 |
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| 437 | #define FDR0 0x0CF |
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| 438 | #define FDR1 0x0CE |
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| 439 | #define FDR2 0x0CD |
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| 440 | #define FDR3 0x0CC |
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| 441 | #define FDR4 0x0CB |
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| 442 | #define FDR5 0x0CA |
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| 443 | #define FDR6 0x0C9 |
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| 444 | #define FDR7 0x0C8 |
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| 445 | #define FBYTE_CNT0_L 0x0BF |
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| 446 | #define FBYTE_CNT1_L 0x0BE |
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| 447 | #define FBYTE_CNT2_L 0x0BD |
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| 448 | #define FBYTE_CNT3_L 0x0BC |
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| 449 | #define FBYTE_CNT4_L 0x0BB |
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| 450 | #define FBYTE_CNT5_L 0x0BA |
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| 451 | #define FBYTE_CNT6_L 0x0B9 |
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| 452 | #define FBYTE_CNT7_L 0x0B8 |
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| 453 | #define FBYTE_CNT0_H 0x0AF |
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| 454 | #define FBYTE_CNT1_H 0x0AE |
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| 455 | #define FBYTE_CNT2_H 0x0AD |
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| 456 | #define FBYTE_CNT3_H 0x0AC |
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| 457 | #define FBYTE_CNT4_H 0x0AB |
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| 458 | #define FBYTE_CNT5_H 0x0AA |
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| 459 | #define FBYTE_CNT6_H 0x0A9 |
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| 460 | #define FBYTE_CNT7_H 0x0A8 |
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| 461 | #define SLP_MD_EN 0x100 |
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| 462 | #define IRQ_EN 0x101 |
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| 463 | #define IRQ_STAT 0x102 |
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| 464 | #define SUSP_WUP 0x103 |
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| 465 | #define PA_EN 0x104 |
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| 466 | #define USB_DMA_ADL 0x105 |
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| 467 | #define USB_DMA_ADH 0x106 |
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| 468 | #define USB_DMA_PLR 0x107 |
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| 469 | #define USB_DMA_EAD 0x108 |
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| 470 | #define USB_DMA_PLT 0x109 |
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| 471 | #define USB_DMA_EN 0x10A |
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| 472 | |
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| 473 | /* Last memory addresses */ |
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| 474 | #define RAMEND 0x07FF |
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| 475 | #define XRAMEND RAMEND |
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| 476 | #define E2END 0 |
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| 477 | #define FLASHEND 0x3FFF |
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| 478 | |
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| 479 | /* |
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| 480 | AT76C711 data space memory map (ranges not listed are reserved): |
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| 481 | 0x0000 - 0x001F - AVR registers |
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| 482 | 0x0020 - 0x005F - AVR I/O space |
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| 483 | 0x0060 - 0x07FF - AVR data SRAM |
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| 484 | 0x1000 - 0x1FFF - USB (not all locations used) |
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| 485 | 0x2000 - 0x201F - DMA controller |
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| 486 | 0x2020 - 0x202F - UART0 |
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| 487 | 0x2030 - 0x203F - UART1 (IRDA) |
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| 488 | 0x2040 - the mysterious Program Memory Control bit (???) |
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| 489 | 0x3000 - 0x37FF - DPRAM |
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| 490 | 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other |
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| 491 | AVR devices did that as well (no need to use LPM!) |
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| 492 | */ |
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| 493 | #endif /* _AVR_IO76C711_H_ */ |
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