| [04a62dce] | 1 | /* Copyright (c) 2002, Marek Michalkiewicz |
|---|
| 2 | All rights reserved. |
|---|
| 3 | |
|---|
| 4 | Redistribution and use in source and binary forms, with or without |
|---|
| 5 | modification, are permitted provided that the following conditions are met: |
|---|
| 6 | |
|---|
| 7 | * Redistributions of source code must retain the above copyright |
|---|
| 8 | notice, this list of conditions and the following disclaimer. |
|---|
| 9 | |
|---|
| 10 | * Redistributions in binary form must reproduce the above copyright |
|---|
| 11 | notice, this list of conditions and the following disclaimer in |
|---|
| 12 | the documentation and/or other materials provided with the |
|---|
| 13 | distribution. |
|---|
| 14 | |
|---|
| 15 | * Neither the name of the copyright holders nor the names of |
|---|
| 16 | contributors may be used to endorse or promote products derived |
|---|
| 17 | from this software without specific prior written permission. |
|---|
| 18 | |
|---|
| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|---|
| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|---|
| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|---|
| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
|---|
| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
|---|
| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
|---|
| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
|---|
| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
|---|
| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
|---|
| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
|---|
| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
|---|
| 30 | |
|---|
| 31 | /* $Id$ */ |
|---|
| 32 | |
|---|
| 33 | /* avr/io4434.h - definitions for AT90S4434 */ |
|---|
| 34 | |
|---|
| 35 | #ifndef _AVR_IO4434_H_ |
|---|
| 36 | #define _AVR_IO4434_H_ 1 |
|---|
| 37 | |
|---|
| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
|---|
| 39 | |
|---|
| 40 | #ifndef _AVR_IO_H_ |
|---|
| 41 | # error "Include <avr/io.h> instead of this file." |
|---|
| 42 | #endif |
|---|
| 43 | |
|---|
| 44 | #ifndef _AVR_IOXXX_H_ |
|---|
| 45 | # define _AVR_IOXXX_H_ "io4434.h" |
|---|
| 46 | #else |
|---|
| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
|---|
| 48 | #endif |
|---|
| 49 | |
|---|
| 50 | /* I/O registers */ |
|---|
| 51 | |
|---|
| 52 | /* ADC Data register */ |
|---|
| 53 | #ifndef __ASSEMBLER__ |
|---|
| 54 | #define ADC _SFR_IO16(0x04) |
|---|
| 55 | #endif |
|---|
| 56 | #define ADCW _SFR_IO16(0x04) |
|---|
| 57 | #define ADCL _SFR_IO8(0x04) |
|---|
| 58 | #define ADCH _SFR_IO8(0x05) |
|---|
| 59 | |
|---|
| 60 | /* ADC Control and Status Register */ |
|---|
| 61 | #define ADCSR _SFR_IO8(0x06) |
|---|
| 62 | |
|---|
| 63 | /* ADC MUX */ |
|---|
| 64 | #define ADMUX _SFR_IO8(0x07) |
|---|
| 65 | |
|---|
| 66 | /* Analog Comparator Control and Status Register */ |
|---|
| 67 | #define ACSR _SFR_IO8(0x08) |
|---|
| 68 | |
|---|
| 69 | /* UART Baud Rate Register */ |
|---|
| 70 | #define UBRR _SFR_IO8(0x09) |
|---|
| 71 | |
|---|
| 72 | /* UART Control Register */ |
|---|
| 73 | #define UCR _SFR_IO8(0x0A) |
|---|
| 74 | |
|---|
| 75 | /* UART Status Register */ |
|---|
| 76 | #define USR _SFR_IO8(0x0B) |
|---|
| 77 | |
|---|
| 78 | /* UART I/O Data Register */ |
|---|
| 79 | #define UDR _SFR_IO8(0x0C) |
|---|
| 80 | |
|---|
| 81 | /* SPI Control Register */ |
|---|
| 82 | #define SPCR _SFR_IO8(0x0D) |
|---|
| 83 | |
|---|
| 84 | /* SPI Status Register */ |
|---|
| 85 | #define SPSR _SFR_IO8(0x0E) |
|---|
| 86 | |
|---|
| 87 | /* SPI I/O Data Register */ |
|---|
| 88 | #define SPDR _SFR_IO8(0x0F) |
|---|
| 89 | |
|---|
| 90 | /* Input Pins, Port D */ |
|---|
| 91 | #define PIND _SFR_IO8(0x10) |
|---|
| 92 | |
|---|
| 93 | /* Data Direction Register, Port D */ |
|---|
| 94 | #define DDRD _SFR_IO8(0x11) |
|---|
| 95 | |
|---|
| 96 | /* Data Register, Port D */ |
|---|
| 97 | #define PORTD _SFR_IO8(0x12) |
|---|
| 98 | |
|---|
| 99 | /* Input Pins, Port C */ |
|---|
| 100 | #define PINC _SFR_IO8(0x13) |
|---|
| 101 | |
|---|
| 102 | /* Data Direction Register, Port C */ |
|---|
| 103 | #define DDRC _SFR_IO8(0x14) |
|---|
| 104 | |
|---|
| 105 | /* Data Register, Port C */ |
|---|
| 106 | #define PORTC _SFR_IO8(0x15) |
|---|
| 107 | |
|---|
| 108 | /* Input Pins, Port B */ |
|---|
| 109 | #define PINB _SFR_IO8(0x16) |
|---|
| 110 | |
|---|
| 111 | /* Data Direction Register, Port B */ |
|---|
| 112 | #define DDRB _SFR_IO8(0x17) |
|---|
| 113 | |
|---|
| 114 | /* Data Register, Port B */ |
|---|
| 115 | #define PORTB _SFR_IO8(0x18) |
|---|
| 116 | |
|---|
| 117 | /* Input Pins, Port A */ |
|---|
| 118 | #define PINA _SFR_IO8(0x19) |
|---|
| 119 | |
|---|
| 120 | /* Data Direction Register, Port A */ |
|---|
| 121 | #define DDRA _SFR_IO8(0x1A) |
|---|
| 122 | |
|---|
| 123 | /* Data Register, Port A */ |
|---|
| 124 | #define PORTA _SFR_IO8(0x1B) |
|---|
| 125 | |
|---|
| 126 | /* EEPROM Control Register */ |
|---|
| 127 | #define EECR _SFR_IO8(0x1C) |
|---|
| 128 | |
|---|
| 129 | /* EEPROM Data Register */ |
|---|
| 130 | #define EEDR _SFR_IO8(0x1D) |
|---|
| 131 | |
|---|
| 132 | /* EEPROM Address Register */ |
|---|
| 133 | #define EEAR _SFR_IO8(0x1E) |
|---|
| 134 | #define EEARL _SFR_IO8(0x1E) |
|---|
| 135 | |
|---|
| 136 | /* Watchdog Timer Control Register */ |
|---|
| 137 | #define WDTCR _SFR_IO8(0x21) |
|---|
| 138 | |
|---|
| 139 | /* Asynchronous mode Status Register */ |
|---|
| 140 | #define ASSR _SFR_IO8(0x22) |
|---|
| 141 | |
|---|
| 142 | /* Timer/Counter2 Output Compare Register */ |
|---|
| 143 | #define OCR2 _SFR_IO8(0x23) |
|---|
| 144 | |
|---|
| 145 | /* Timer/Counter 2 */ |
|---|
| 146 | #define TCNT2 _SFR_IO8(0x24) |
|---|
| 147 | |
|---|
| 148 | /* Timer/Counter 2 Control Register */ |
|---|
| 149 | #define TCCR2 _SFR_IO8(0x25) |
|---|
| 150 | |
|---|
| 151 | /* T/C 1 Input Capture Register */ |
|---|
| 152 | #define ICR1 _SFR_IO16(0x26) |
|---|
| 153 | #define ICR1L _SFR_IO8(0x26) |
|---|
| 154 | #define ICR1H _SFR_IO8(0x27) |
|---|
| 155 | |
|---|
| 156 | /* Timer/Counter1 Output Compare Register B */ |
|---|
| 157 | #define OCR1B _SFR_IO16(0x28) |
|---|
| 158 | #define OCR1BL _SFR_IO8(0x28) |
|---|
| 159 | #define OCR1BH _SFR_IO8(0x29) |
|---|
| 160 | |
|---|
| 161 | /* Timer/Counter1 Output Compare Register A */ |
|---|
| 162 | #define OCR1A _SFR_IO16(0x2A) |
|---|
| 163 | #define OCR1AL _SFR_IO8(0x2A) |
|---|
| 164 | #define OCR1AH _SFR_IO8(0x2B) |
|---|
| 165 | |
|---|
| 166 | /* Timer/Counter 1 */ |
|---|
| 167 | #define TCNT1 _SFR_IO16(0x2C) |
|---|
| 168 | #define TCNT1L _SFR_IO8(0x2C) |
|---|
| 169 | #define TCNT1H _SFR_IO8(0x2D) |
|---|
| 170 | |
|---|
| 171 | /* Timer/Counter 1 Control and Status Register */ |
|---|
| 172 | #define TCCR1B _SFR_IO8(0x2E) |
|---|
| 173 | |
|---|
| 174 | /* Timer/Counter 1 Control Register */ |
|---|
| 175 | #define TCCR1A _SFR_IO8(0x2F) |
|---|
| 176 | |
|---|
| 177 | /* Timer/Counter 0 */ |
|---|
| 178 | #define TCNT0 _SFR_IO8(0x32) |
|---|
| 179 | |
|---|
| 180 | /* Timer/Counter 0 Control Register */ |
|---|
| 181 | #define TCCR0 _SFR_IO8(0x33) |
|---|
| 182 | |
|---|
| 183 | /* MCU general Status Register */ |
|---|
| 184 | #define MCUSR _SFR_IO8(0x34) |
|---|
| 185 | |
|---|
| 186 | /* MCU general Control Register */ |
|---|
| 187 | #define MCUCR _SFR_IO8(0x35) |
|---|
| 188 | |
|---|
| 189 | /* Timer/Counter Interrupt Flag register */ |
|---|
| 190 | #define TIFR _SFR_IO8(0x38) |
|---|
| 191 | |
|---|
| 192 | /* Timer/Counter Interrupt MaSK register */ |
|---|
| 193 | #define TIMSK _SFR_IO8(0x39) |
|---|
| 194 | |
|---|
| 195 | /* General Interrupt Flag Register */ |
|---|
| 196 | #define GIFR _SFR_IO8(0x3A) |
|---|
| 197 | |
|---|
| 198 | /* General Interrupt MaSK register */ |
|---|
| 199 | #define GIMSK _SFR_IO8(0x3B) |
|---|
| 200 | |
|---|
| 201 | /* 0x3D..0x3E SP */ |
|---|
| 202 | |
|---|
| 203 | /* 0x3F SREG */ |
|---|
| 204 | |
|---|
| 205 | /* Interrupt vectors */ |
|---|
| 206 | |
|---|
| 207 | /* External Interrupt 0 */ |
|---|
| 208 | #define INT0_vect _VECTOR(1) |
|---|
| 209 | #define SIG_INTERRUPT0 _VECTOR(1) |
|---|
| 210 | |
|---|
| 211 | /* External Interrupt 1 */ |
|---|
| 212 | #define INT1_vect _VECTOR(2) |
|---|
| 213 | #define SIG_INTERRUPT1 _VECTOR(2) |
|---|
| 214 | |
|---|
| 215 | /* Timer/Counter2 Compare Match */ |
|---|
| 216 | #define TIMER2_COMP_vect _VECTOR(3) |
|---|
| 217 | #define SIG_OUTPUT_COMPARE2 _VECTOR(3) |
|---|
| 218 | |
|---|
| 219 | /* Timer/Counter2 Overflow */ |
|---|
| 220 | #define TIMER2_OVF_vect _VECTOR(4) |
|---|
| 221 | #define SIG_OVERFLOW2 _VECTOR(4) |
|---|
| 222 | |
|---|
| 223 | /* Timer/Counter1 Capture Event */ |
|---|
| 224 | #define TIMER1_CAPT_vect _VECTOR(5) |
|---|
| 225 | #define SIG_INPUT_CAPTURE1 _VECTOR(5) |
|---|
| 226 | |
|---|
| 227 | /* Timer/Counter1 Compare Match A */ |
|---|
| 228 | #define TIMER1_COMPA_vect _VECTOR(6) |
|---|
| 229 | #define SIG_OUTPUT_COMPARE1A _VECTOR(6) |
|---|
| 230 | |
|---|
| 231 | /* Timer/Counter1 Compare Match B */ |
|---|
| 232 | #define TIMER1_COMPB_vect _VECTOR(7) |
|---|
| 233 | #define SIG_OUTPUT_COMPARE1B _VECTOR(7) |
|---|
| 234 | |
|---|
| 235 | /* Timer/Counter1 Overflow */ |
|---|
| 236 | #define TIMER1_OVF_vect _VECTOR(8) |
|---|
| 237 | #define SIG_OVERFLOW1 _VECTOR(8) |
|---|
| 238 | |
|---|
| 239 | /* Timer/Counter0 Overflow */ |
|---|
| 240 | #define TIMER0_OVF_vect _VECTOR(9) |
|---|
| 241 | #define SIG_OVERFLOW0 _VECTOR(9) |
|---|
| 242 | |
|---|
| 243 | /* SPI Serial Transfer Complete */ |
|---|
| 244 | #define SPI_STC_vect _VECTOR(10) |
|---|
| 245 | #define SIG_SPI _VECTOR(10) |
|---|
| 246 | |
|---|
| 247 | /* UART, RX Complete */ |
|---|
| 248 | #define UART_RX_vect _VECTOR(11) |
|---|
| 249 | #define SIG_UART_RECV _VECTOR(11) |
|---|
| 250 | |
|---|
| 251 | /* UART Data Register Empty */ |
|---|
| 252 | #define UART_UDRE_vect _VECTOR(12) |
|---|
| 253 | #define SIG_UART_DATA _VECTOR(12) |
|---|
| 254 | |
|---|
| 255 | /* UART, TX Complete */ |
|---|
| 256 | #define UART_TX_vect _VECTOR(13) |
|---|
| 257 | #define SIG_UART_TRANS _VECTOR(13) |
|---|
| 258 | |
|---|
| 259 | /* ADC Conversion Complete */ |
|---|
| 260 | #define ADC_vect _VECTOR(14) |
|---|
| 261 | #define SIG_ADC _VECTOR(14) |
|---|
| 262 | |
|---|
| 263 | /* EEPROM Ready */ |
|---|
| 264 | #define EE_RDY_vect _VECTOR(15) |
|---|
| 265 | #define SIG_EEPROM_READY _VECTOR(15) |
|---|
| 266 | |
|---|
| 267 | /* Analog Comparator */ |
|---|
| 268 | #define ANA_COMP_vect _VECTOR(16) |
|---|
| 269 | #define SIG_COMPARATOR _VECTOR(16) |
|---|
| 270 | |
|---|
| 271 | #define _VECTORS_SIZE 34 |
|---|
| 272 | |
|---|
| 273 | /* |
|---|
| 274 | The Register Bit names are represented by their bit number (0-7). |
|---|
| 275 | */ |
|---|
| 276 | |
|---|
| 277 | /* MCU general Status Register */ |
|---|
| 278 | #define EXTRF 1 |
|---|
| 279 | #define PORF 0 |
|---|
| 280 | |
|---|
| 281 | /* General Interrupt MaSK register */ |
|---|
| 282 | #define INT1 7 |
|---|
| 283 | #define INT0 6 |
|---|
| 284 | |
|---|
| 285 | /* General Interrupt Flag Register */ |
|---|
| 286 | #define INTF1 7 |
|---|
| 287 | #define INTF0 6 |
|---|
| 288 | |
|---|
| 289 | /* Timer/Counter Interrupt MaSK register */ |
|---|
| 290 | #define OCIE2 7 |
|---|
| 291 | #define TOIE2 6 |
|---|
| 292 | #define TICIE1 5 |
|---|
| 293 | #define OCIE1A 4 |
|---|
| 294 | #define OCIE1B 3 |
|---|
| 295 | #define TOIE1 2 |
|---|
| 296 | #define TOIE0 0 |
|---|
| 297 | |
|---|
| 298 | /* Timer/Counter Interrupt Flag register */ |
|---|
| 299 | #define OCF2 7 |
|---|
| 300 | #define TOV2 6 |
|---|
| 301 | #define ICF1 5 |
|---|
| 302 | #define OCF1A 4 |
|---|
| 303 | #define OCF1B 3 |
|---|
| 304 | #define TOV1 2 |
|---|
| 305 | #define TOV0 0 |
|---|
| 306 | |
|---|
| 307 | /* MCU general Control Register */ |
|---|
| 308 | #define SE 6 |
|---|
| 309 | #define SM1 5 |
|---|
| 310 | #define SM0 4 |
|---|
| 311 | #define ISC11 3 |
|---|
| 312 | #define ISC10 2 |
|---|
| 313 | #define ISC01 1 |
|---|
| 314 | #define ISC00 0 |
|---|
| 315 | |
|---|
| 316 | /* Timer/Counter 0 Control Register */ |
|---|
| 317 | #define CS02 2 |
|---|
| 318 | #define CS01 1 |
|---|
| 319 | #define CS00 0 |
|---|
| 320 | |
|---|
| 321 | /* Timer/Counter 1 Control Register */ |
|---|
| 322 | #define COM1A1 7 |
|---|
| 323 | #define COM1A0 6 |
|---|
| 324 | #define COM1B1 5 |
|---|
| 325 | #define COM1B0 4 |
|---|
| 326 | #define PWM11 1 |
|---|
| 327 | #define PWM10 0 |
|---|
| 328 | |
|---|
| 329 | /* Timer/Counter 1 Control and Status Register */ |
|---|
| 330 | #define ICNC1 7 |
|---|
| 331 | #define ICES1 6 |
|---|
| 332 | #define CTC1 3 |
|---|
| 333 | #define CS12 2 |
|---|
| 334 | #define CS11 1 |
|---|
| 335 | #define CS10 0 |
|---|
| 336 | |
|---|
| 337 | /* Timer/Counter 2 Control Register */ |
|---|
| 338 | #define PWM2 6 |
|---|
| 339 | #define COM21 5 |
|---|
| 340 | #define COM20 4 |
|---|
| 341 | #define CTC2 3 |
|---|
| 342 | #define CS22 2 |
|---|
| 343 | #define CS21 1 |
|---|
| 344 | #define CS20 0 |
|---|
| 345 | |
|---|
| 346 | /* Asynchronous mode Status Register */ |
|---|
| 347 | #define AS2 3 |
|---|
| 348 | #define TCN2UB 2 |
|---|
| 349 | #define OCR2UB 1 |
|---|
| 350 | #define TCR2UB 0 |
|---|
| 351 | |
|---|
| 352 | /* Watchdog Timer Control Register */ |
|---|
| 353 | #define WDTOE 4 |
|---|
| 354 | #define WDE 3 |
|---|
| 355 | #define WDP2 2 |
|---|
| 356 | #define WDP1 1 |
|---|
| 357 | #define WDP0 0 |
|---|
| 358 | |
|---|
| 359 | /* Data Register, Port A */ |
|---|
| 360 | #define PA7 7 |
|---|
| 361 | #define PA6 6 |
|---|
| 362 | #define PA5 5 |
|---|
| 363 | #define PA4 4 |
|---|
| 364 | #define PA3 3 |
|---|
| 365 | #define PA2 2 |
|---|
| 366 | #define PA1 1 |
|---|
| 367 | #define PA0 0 |
|---|
| 368 | |
|---|
| 369 | /* Data Direction Register, Port A */ |
|---|
| 370 | #define DDA7 7 |
|---|
| 371 | #define DDA6 6 |
|---|
| 372 | #define DDA5 5 |
|---|
| 373 | #define DDA4 4 |
|---|
| 374 | #define DDA3 3 |
|---|
| 375 | #define DDA2 2 |
|---|
| 376 | #define DDA1 1 |
|---|
| 377 | #define DDA0 0 |
|---|
| 378 | |
|---|
| 379 | /* Input Pins, Port A */ |
|---|
| 380 | #define PINA7 7 |
|---|
| 381 | #define PINA6 6 |
|---|
| 382 | #define PINA5 5 |
|---|
| 383 | #define PINA4 4 |
|---|
| 384 | #define PINA3 3 |
|---|
| 385 | #define PINA2 2 |
|---|
| 386 | #define PINA1 1 |
|---|
| 387 | #define PINA0 0 |
|---|
| 388 | |
|---|
| 389 | /* Data Register, Port B */ |
|---|
| 390 | #define PB7 7 |
|---|
| 391 | #define PB6 6 |
|---|
| 392 | #define PB5 5 |
|---|
| 393 | #define PB4 4 |
|---|
| 394 | #define PB3 3 |
|---|
| 395 | #define PB2 2 |
|---|
| 396 | #define PB1 1 |
|---|
| 397 | #define PB0 0 |
|---|
| 398 | |
|---|
| 399 | /* Data Direction Register, Port B */ |
|---|
| 400 | #define DDB7 7 |
|---|
| 401 | #define DDB6 6 |
|---|
| 402 | #define DDB5 5 |
|---|
| 403 | #define DDB4 4 |
|---|
| 404 | #define DDB3 3 |
|---|
| 405 | #define DDB2 2 |
|---|
| 406 | #define DDB1 1 |
|---|
| 407 | #define DDB0 0 |
|---|
| 408 | |
|---|
| 409 | /* Input Pins, Port B */ |
|---|
| 410 | #define PINB7 7 |
|---|
| 411 | #define PINB6 6 |
|---|
| 412 | #define PINB5 5 |
|---|
| 413 | #define PINB4 4 |
|---|
| 414 | #define PINB3 3 |
|---|
| 415 | #define PINB2 2 |
|---|
| 416 | #define PINB1 1 |
|---|
| 417 | #define PINB0 0 |
|---|
| 418 | |
|---|
| 419 | /* Data Register, Port C */ |
|---|
| 420 | #define PC7 7 |
|---|
| 421 | #define PC6 6 |
|---|
| 422 | #define PC5 5 |
|---|
| 423 | #define PC4 4 |
|---|
| 424 | #define PC3 3 |
|---|
| 425 | #define PC2 2 |
|---|
| 426 | #define PC1 1 |
|---|
| 427 | #define PC0 0 |
|---|
| 428 | |
|---|
| 429 | /* Data Direction Register, Port C */ |
|---|
| 430 | #define DDC7 7 |
|---|
| 431 | #define DDC6 6 |
|---|
| 432 | #define DDC5 5 |
|---|
| 433 | #define DDC4 4 |
|---|
| 434 | #define DDC3 3 |
|---|
| 435 | #define DDC2 2 |
|---|
| 436 | #define DDC1 1 |
|---|
| 437 | #define DDC0 0 |
|---|
| 438 | |
|---|
| 439 | /* Input Pins, Port C */ |
|---|
| 440 | #define PINC7 7 |
|---|
| 441 | #define PINC6 6 |
|---|
| 442 | #define PINC5 5 |
|---|
| 443 | #define PINC4 4 |
|---|
| 444 | #define PINC3 3 |
|---|
| 445 | #define PINC2 2 |
|---|
| 446 | #define PINC1 1 |
|---|
| 447 | #define PINC0 0 |
|---|
| 448 | |
|---|
| 449 | /* Data Register, Port D */ |
|---|
| 450 | #define PD7 7 |
|---|
| 451 | #define PD6 6 |
|---|
| 452 | #define PD5 5 |
|---|
| 453 | #define PD4 4 |
|---|
| 454 | #define PD3 3 |
|---|
| 455 | #define PD2 2 |
|---|
| 456 | #define PD1 1 |
|---|
| 457 | #define PD0 0 |
|---|
| 458 | |
|---|
| 459 | /* Data Direction Register, Port D */ |
|---|
| 460 | #define DDD7 7 |
|---|
| 461 | #define DDD6 6 |
|---|
| 462 | #define DDD5 5 |
|---|
| 463 | #define DDD4 4 |
|---|
| 464 | #define DDD3 3 |
|---|
| 465 | #define DDD2 2 |
|---|
| 466 | #define DDD1 1 |
|---|
| 467 | #define DDD0 0 |
|---|
| 468 | |
|---|
| 469 | /* Input Pins, Port D */ |
|---|
| 470 | #define PIND7 7 |
|---|
| 471 | #define PIND6 6 |
|---|
| 472 | #define PIND5 5 |
|---|
| 473 | #define PIND4 4 |
|---|
| 474 | #define PIND3 3 |
|---|
| 475 | #define PIND2 2 |
|---|
| 476 | #define PIND1 1 |
|---|
| 477 | #define PIND0 0 |
|---|
| 478 | |
|---|
| 479 | /* SPI Control Register */ |
|---|
| 480 | #define SPIE 7 |
|---|
| 481 | #define SPE 6 |
|---|
| 482 | #define DORD 5 |
|---|
| 483 | #define MSTR 4 |
|---|
| 484 | #define CPOL 3 |
|---|
| 485 | #define CPHA 2 |
|---|
| 486 | #define SPR1 1 |
|---|
| 487 | #define SPR0 0 |
|---|
| 488 | |
|---|
| 489 | /* SPI Status Register */ |
|---|
| 490 | #define SPIF 7 |
|---|
| 491 | #define WCOL 6 |
|---|
| 492 | |
|---|
| 493 | /* UART Status Register */ |
|---|
| 494 | #define RXC 7 |
|---|
| 495 | #define TXC 6 |
|---|
| 496 | #define UDRE 5 |
|---|
| 497 | #define FE 4 |
|---|
| 498 | #define DOR 3 |
|---|
| 499 | |
|---|
| 500 | /* UART Control Register */ |
|---|
| 501 | #define RXCIE 7 |
|---|
| 502 | #define TXCIE 6 |
|---|
| 503 | #define UDRIE 5 |
|---|
| 504 | #define RXEN 4 |
|---|
| 505 | #define TXEN 3 |
|---|
| 506 | #define CHR9 2 |
|---|
| 507 | #define RXB8 1 |
|---|
| 508 | #define TXB8 0 |
|---|
| 509 | |
|---|
| 510 | /* Analog Comparator Control and Status Register */ |
|---|
| 511 | #define ACD 7 |
|---|
| 512 | #define ACO 5 |
|---|
| 513 | #define ACI 4 |
|---|
| 514 | #define ACIE 3 |
|---|
| 515 | #define ACIC 2 |
|---|
| 516 | #define ACIS1 1 |
|---|
| 517 | #define ACIS0 0 |
|---|
| 518 | |
|---|
| 519 | /* ADC MUX */ |
|---|
| 520 | #define MUX2 2 |
|---|
| 521 | #define MUX1 1 |
|---|
| 522 | #define MUX0 0 |
|---|
| 523 | |
|---|
| 524 | /* ADC Control and Status Register */ |
|---|
| 525 | #define ADEN 7 |
|---|
| 526 | #define ADSC 6 |
|---|
| 527 | #define ADFR 5 |
|---|
| 528 | #define ADIF 4 |
|---|
| 529 | #define ADIE 3 |
|---|
| 530 | #define ADPS2 2 |
|---|
| 531 | #define ADPS1 1 |
|---|
| 532 | #define ADPS0 0 |
|---|
| 533 | |
|---|
| 534 | /* EEPROM Control Register */ |
|---|
| 535 | #define EERIE 3 |
|---|
| 536 | #define EEMWE 2 |
|---|
| 537 | #define EEWE 1 |
|---|
| 538 | #define EERE 0 |
|---|
| 539 | |
|---|
| 540 | /* Constants */ |
|---|
| 541 | #define RAMEND 0x15F /*Last On-Chip SRAM location*/ |
|---|
| 542 | #define XRAMEND RAMEND |
|---|
| 543 | #define E2END 0xFF |
|---|
| 544 | #define E2PAGESIZE 0 |
|---|
| 545 | #define FLASHEND 0xFFF |
|---|
| 546 | |
|---|
| 547 | |
|---|
| 548 | /* Fuses */ |
|---|
| 549 | #define FUSE_MEMORY_SIZE 1 |
|---|
| 550 | |
|---|
| 551 | /* Low Fuse Byte */ |
|---|
| 552 | #define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ |
|---|
| 553 | #define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ |
|---|
| 554 | #define LFUSE_DEFAULT (0xFF) |
|---|
| 555 | |
|---|
| 556 | |
|---|
| 557 | /* Lock Bits */ |
|---|
| 558 | #define __LOCK_BITS_EXIST |
|---|
| 559 | |
|---|
| 560 | |
|---|
| 561 | /* Signature */ |
|---|
| 562 | #define SIGNATURE_0 0x1E |
|---|
| 563 | #define SIGNATURE_1 0x93 |
|---|
| 564 | #define SIGNATURE_2 0x03 |
|---|
| 565 | |
|---|
| 566 | |
|---|
| 567 | #endif /* _AVR_IO4434_H_ */ |
|---|
![[RTEMS Logo]](/images/logo.png){kind=logo}
