1 | /* Copyright (c) 2003,2005 Keith Gudger |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* avr/io43u32x.h - definitions for AT43USB32x */ |
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34 | |
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35 | #ifndef _AVR_IO43U32X_H_ |
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36 | #define _AVR_IO43U32X_H_ 1 |
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37 | |
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38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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39 | |
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40 | #ifndef _AVR_IO_H_ |
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41 | # error "Include <avr/io.h> instead of this file." |
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42 | #endif |
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43 | |
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44 | #ifndef _AVR_IOXXX_H_ |
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45 | # define _AVR_IOXXX_H_ "io43u32x.h" |
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46 | #else |
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47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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48 | #endif |
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49 | |
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50 | /* I/O registers */ |
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51 | |
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52 | /* Analog Comparator Control and Status Register */ |
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53 | #define ACSR _SFR_IO8(0x08) |
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54 | |
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55 | /* UART Baud Rate Register */ |
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56 | #define UBRR _SFR_IO8(0x09) |
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57 | |
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58 | /* UART Control Register */ |
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59 | #define UCR _SFR_IO8(0x0A) |
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60 | |
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61 | /* UART Status Register */ |
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62 | #define USR _SFR_IO8(0x0B) |
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63 | |
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64 | /* UART I/O Data Register */ |
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65 | #define UDR _SFR_IO8(0x0C) |
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66 | |
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67 | /* Input Pins, Port E */ // new port for 43324/6 |
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68 | #define PINE _SFR_IO8(0x01) |
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69 | |
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70 | /* Data Direction Register, Port E */ |
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71 | #define DDRE _SFR_IO8(0x02) |
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72 | |
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73 | /* Data Register, Port E */ |
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74 | #define PORTE _SFR_IO8(0x03) |
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75 | |
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76 | /* SPI Control Register */ |
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77 | #define SPCR _SFR_IO8(0x0D) |
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78 | |
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79 | /* SPI Status Register */ |
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80 | #define SPSR _SFR_IO8(0x0E) |
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81 | |
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82 | /* SPI I/O Data Register */ |
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83 | #define SPDR _SFR_IO8(0x0F) |
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84 | |
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85 | /* Input Pins, Port D */ |
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86 | #define PIND _SFR_IO8(0x10) |
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87 | |
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88 | /* Data Direction Register, Port D */ |
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89 | #define DDRD _SFR_IO8(0x11) |
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90 | |
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91 | /* Data Register, Port D */ |
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92 | #define PORTD _SFR_IO8(0x12) |
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93 | |
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94 | /* Input Pins, Port C */ |
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95 | #define PINC _SFR_IO8(0x13) |
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96 | |
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97 | /* Data Direction Register, Port C */ |
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98 | #define DDRC _SFR_IO8(0x14) |
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99 | |
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100 | /* Data Register, Port C */ |
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101 | #define PORTC _SFR_IO8(0x15) |
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102 | |
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103 | /* Input Pins, Port B */ |
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104 | #define PINB _SFR_IO8(0x16) |
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105 | |
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106 | /* Data Direction Register, Port B */ |
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107 | #define DDRB _SFR_IO8(0x17) |
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108 | |
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109 | /* Data Register, Port B */ |
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110 | #define PORTB _SFR_IO8(0x18) |
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111 | |
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112 | /* Input Pins, Port A */ |
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113 | #define PINA _SFR_IO8(0x19) |
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114 | |
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115 | /* Data Direction Register, Port A */ |
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116 | #define DDRA _SFR_IO8(0x1A) |
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117 | |
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118 | /* Data Register, Port A */ |
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119 | #define PORTA _SFR_IO8(0x1B) |
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120 | |
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121 | /* 0x1C..0x1F reserved */ |
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122 | |
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123 | /* Watchdog Timer Control Register */ |
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124 | #define WDTCR _SFR_IO8(0x21) |
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125 | |
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126 | /* T/C 1 Input Capture Register */ |
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127 | #define ICR1 _SFR_IO16(0x24) |
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128 | #define ICR1L _SFR_IO8(0x24) |
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129 | #define ICR1H _SFR_IO8(0x25) |
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130 | |
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131 | /* Timer/Counter1 Output Compare Register B */ |
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132 | #define OCR1B _SFR_IO16(0x28) |
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133 | #define OCR1BL _SFR_IO8(0x28) |
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134 | #define OCR1BH _SFR_IO8(0x29) |
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135 | |
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136 | /* Timer/Counter1 Output Compare Register A */ |
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137 | #define OCR1A _SFR_IO16(0x2A) |
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138 | #define OCR1AL _SFR_IO8(0x2A) |
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139 | #define OCR1AH _SFR_IO8(0x2B) |
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140 | |
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141 | /* Timer/Counter 1 */ |
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142 | #define TCNT1 _SFR_IO16(0x2C) |
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143 | #define TCNT1L _SFR_IO8(0x2C) |
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144 | #define TCNT1H _SFR_IO8(0x2D) |
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145 | |
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146 | /* Timer/Counter 1 Control and Status Register */ |
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147 | #define TCCR1B _SFR_IO8(0x2E) |
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148 | |
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149 | /* Timer/Counter 1 Control Register */ |
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150 | #define TCCR1A _SFR_IO8(0x2F) |
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151 | |
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152 | /* Timer/Counter 0 */ |
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153 | #define TCNT0 _SFR_IO8(0x32) |
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154 | |
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155 | /* Timer/Counter 0 Control Register */ |
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156 | #define TCCR0 _SFR_IO8(0x33) |
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157 | |
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158 | /* MCU general Control Register */ |
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159 | #define MCUCR _SFR_IO8(0x35) |
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160 | |
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161 | /* Timer/Counter Interrupt Flag Register */ |
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162 | #define TIFR _SFR_IO8(0x38) |
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163 | |
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164 | /* Timer/Counter Interrupt MaSK register */ |
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165 | #define TIMSK _SFR_IO8(0x39) |
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166 | |
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167 | /* General Interrupt Control Register */ |
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168 | #define GIFR _SFR_IO8(0x3A) |
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169 | |
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170 | /* General Interrupt Mask register */ |
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171 | #define GIMSK _SFR_IO8(0x3B) |
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172 | |
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173 | /* Interrupt vectors */ |
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174 | |
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175 | #define SIG_INTERRUPT0 _VECTOR(1) |
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176 | #define SIG_INTERRUPT1 _VECTOR(2) |
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177 | #define SIG_TIMER1_CAPT1 _VECTOR(3) |
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178 | #define SIG_INPUT_CAPTURE1 _VECTOR(3) |
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179 | #define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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180 | #define SIG_OUTPUT_COMPARE1B _VECTOR(5) |
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181 | #define SIG_OVERFLOW1 _VECTOR(6) |
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182 | #define SIG_OVERFLOW0 _VECTOR(7) |
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183 | #define SIG_SPI _VECTOR(8) |
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184 | #define SIG_UART_RECV _VECTOR(9) |
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185 | #define SIG_UART_DATA _VECTOR(10) |
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186 | #define SIG_UART_TRANS _VECTOR(11) |
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187 | #define SIG_USB_INT _VECTOR(12) |
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188 | |
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189 | #define _VECTORS_SIZE 52 |
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190 | |
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191 | /* |
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192 | The Register Bit names are represented by their bit number (0-7). |
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193 | */ |
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194 | |
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195 | /* Timer/Counter Interrupt MaSK register */ |
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196 | #define TICIE1 3 |
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197 | #define OCIE1A 6 |
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198 | #define OCIE1B 5 |
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199 | #define TOIE1 7 |
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200 | #define TOIE0 1 |
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201 | |
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202 | /* Timer/Counter Interrupt Flag Register */ |
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203 | #define ICF1 3 |
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204 | #define OCF1A 6 |
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205 | #define OCF1B 5 |
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206 | #define TOV1 7 |
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207 | #define TOV0 1 |
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208 | |
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209 | /* MCU general Control Register */ |
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210 | #define SE 5 |
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211 | #define SM 4 |
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212 | #define ISC11 3 |
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213 | #define ISC10 2 |
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214 | #define ISC01 1 |
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215 | #define ISC00 0 |
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216 | |
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217 | /* Timer/Counter 0 Control Register */ |
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218 | #define CS02 2 |
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219 | #define CS01 1 |
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220 | #define CS00 0 |
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221 | |
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222 | |
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223 | /* Timer/Counter 1 Control Register */ |
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224 | #define COM1A1 7 |
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225 | #define COM1A0 6 |
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226 | #define COM1B1 5 |
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227 | #define COM1B0 4 |
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228 | #define PWM11 1 |
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229 | #define PWM10 0 |
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230 | |
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231 | /* Timer/Counter 1 Control and Status Register */ |
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232 | #define ICNC1 7 |
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233 | #define ICES1 6 |
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234 | #define CTC1 3 |
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235 | #define CS12 2 |
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236 | #define CS11 1 |
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237 | #define CS10 0 |
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238 | |
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239 | /* Watchdog Timer Control Register */ |
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240 | #define WDTOE 4 |
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241 | #define WDE 3 |
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242 | #define WDP2 2 |
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243 | #define WDP1 1 |
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244 | #define WDP0 0 |
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245 | |
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246 | /* Data Register, Port A */ |
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247 | #define PA7 7 |
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248 | #define PA6 6 |
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249 | #define PA5 5 |
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250 | #define PA4 4 |
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251 | #define PA3 3 |
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252 | #define PA2 2 |
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253 | #define PA1 1 |
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254 | #define PA0 0 |
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255 | |
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256 | /* Data Direction Register, Port A */ |
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257 | #define DDA7 7 |
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258 | #define DDA6 6 |
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259 | #define DDA5 5 |
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260 | #define DDA4 4 |
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261 | #define DDA3 3 |
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262 | #define DDA2 2 |
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263 | #define DDA1 1 |
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264 | #define DDA0 0 |
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265 | |
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266 | /* Input Pins, Port A */ |
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267 | #define PINA7 7 |
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268 | #define PINA6 6 |
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269 | #define PINA5 5 |
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270 | #define PINA4 4 |
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271 | #define PINA3 3 |
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272 | #define PINA2 2 |
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273 | #define PINA1 1 |
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274 | #define PINA0 0 |
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275 | |
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276 | /* Data Register, Port B */ |
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277 | #define PB7 7 |
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278 | #define PB6 6 |
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279 | #define PB5 5 |
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280 | #define PB4 4 |
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281 | #define PB3 3 |
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282 | #define PB2 2 |
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283 | #define PB1 1 |
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284 | #define PB0 0 |
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285 | |
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286 | /* Data Direction Register, Port B */ |
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287 | #define DDB7 7 |
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288 | #define DDB6 6 |
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289 | #define DDB5 5 |
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290 | #define DDB4 4 |
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291 | #define DDB3 3 |
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292 | #define DDB2 2 |
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293 | #define DDB1 1 |
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294 | #define DDB0 0 |
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295 | |
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296 | /* Input Pins, Port B */ |
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297 | #define PINB7 7 |
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298 | #define PINB6 6 |
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299 | #define PINB5 5 |
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300 | #define PINB4 4 |
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301 | #define PINB3 3 |
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302 | #define PINB2 2 |
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303 | #define PINB1 1 |
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304 | #define PINB0 0 |
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305 | |
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306 | /* Data Direction Register, Port C */ |
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307 | #define DDC7 7 |
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308 | #define DDC6 6 |
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309 | #define DDC5 5 |
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310 | #define DDC4 4 |
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311 | #define DDC3 3 |
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312 | #define DDC2 2 |
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313 | #define DDC1 1 |
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314 | #define DDC0 0 |
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315 | |
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316 | /* Input Pins, Port C */ |
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317 | #define PINC7 7 |
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318 | #define PINC6 6 |
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319 | #define PINC5 5 |
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320 | #define PINC4 4 |
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321 | #define PINC3 3 |
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322 | #define PINC2 2 |
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323 | #define PINC1 1 |
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324 | #define PINC0 0 |
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325 | |
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326 | /* Data Register, Port C */ |
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327 | #define PC7 7 |
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328 | #define PC6 6 |
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329 | #define PC5 5 |
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330 | #define PC4 4 |
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331 | #define PC3 3 |
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332 | #define PC2 2 |
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333 | #define PC1 1 |
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334 | #define PC0 0 |
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335 | |
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336 | /* Data Register, Port D */ |
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337 | #define PD7 7 |
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338 | #define PD6 6 |
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339 | #define PD5 5 |
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340 | #define PD4 4 |
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341 | #define PD3 3 |
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342 | #define PD2 2 |
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343 | #define PD1 1 |
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344 | #define PD0 0 |
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345 | |
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346 | /* Data Direction Register, Port D */ |
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347 | #define DDD7 7 |
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348 | #define DDD6 6 |
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349 | #define DDD5 5 |
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350 | #define DDD4 4 |
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351 | #define DDD3 3 |
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352 | #define DDD2 2 |
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353 | #define DDD1 1 |
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354 | #define DDD0 0 |
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355 | |
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356 | /* Input Pins, Port D */ |
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357 | #define PIND7 7 |
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358 | #define PIND6 6 |
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359 | #define PIND5 5 |
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360 | #define PIND4 4 |
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361 | #define PIND3 3 |
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362 | #define PIND2 2 |
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363 | #define PIND1 1 |
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364 | #define PIND0 0 |
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365 | |
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366 | /* Data Register, Port E */ |
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367 | #define PE7 7 |
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368 | #define PE6 6 |
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369 | #define PE5 5 |
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370 | #define PE4 4 |
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371 | #define PE3 3 |
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372 | #define PE2 2 |
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373 | #define PE1 1 |
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374 | #define PE0 0 |
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375 | |
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376 | /* Data Direction Register, Port E */ |
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377 | #define DDE7 7 |
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378 | #define DDE6 6 |
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379 | #define DDE5 5 |
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380 | #define DDE4 4 |
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381 | #define DDE3 3 |
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382 | #define DDE2 2 |
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383 | #define DDE1 1 |
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384 | #define DDE0 0 |
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385 | |
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386 | /* Input Pins, Port E */ |
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387 | #define PINE7 7 |
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388 | #define PINE6 6 |
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389 | #define PINE5 5 |
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390 | #define PINE4 4 |
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391 | #define PINE3 3 |
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392 | #define PINE2 2 |
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393 | #define PINE1 1 |
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394 | #define PINE0 0 |
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395 | |
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396 | /* SPI Status Register */ |
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397 | #define SPIF 7 |
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398 | #define WCOL 6 |
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399 | |
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400 | /* SPI Control Register */ |
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401 | #define SPIE 7 |
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402 | #define SPE 6 |
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403 | #define DORD 5 |
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404 | #define MSTR 4 |
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405 | #define CPOL 3 |
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406 | #define CPHA 2 |
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407 | #define SPR1 1 |
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408 | #define SPR0 0 |
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409 | |
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410 | /* UART Status Register */ |
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411 | #define RXC 7 |
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412 | #define TXC 6 |
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413 | #define UDRE 5 |
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414 | #define FE 4 |
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415 | #define DOR 3 |
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416 | |
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417 | /* UART Control Register */ |
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418 | #define RXCIE 7 |
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419 | #define TXCIE 6 |
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420 | #define UDRIE 5 |
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421 | #define RXEN 4 |
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422 | #define TXEN 3 |
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423 | #define CHR9 2 |
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424 | #define RXB8 1 |
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425 | #define TXB8 0 |
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426 | |
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427 | /* Constants */ |
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428 | #define RAMEND 0x025F /*Last On-Chip SRAM Location*/ |
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429 | #define XRAMEND RAMEND |
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430 | #define E2END 0x0000 |
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431 | |
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432 | /* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory, |
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433 | but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */ |
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434 | #define FLASHEND 0x0FFFF |
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435 | |
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436 | #endif /* _AVR_43USB32X_H_ */ |
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