| 1 | /* Copyright (c) 2002, Marek Michalkiewicz |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/io2333.h - definitions for AT90S2333 */ |
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| 34 | |
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| 35 | #ifndef _AVR_IO2333_H_ |
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| 36 | #define _AVR_IO2333_H_ 1 |
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| 37 | |
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| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 39 | |
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| 40 | #ifndef _AVR_IO_H_ |
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| 41 | # error "Include <avr/io.h> instead of this file." |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifndef _AVR_IOXXX_H_ |
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| 45 | # define _AVR_IOXXX_H_ "io2333.h" |
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| 46 | #else |
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| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 48 | #endif |
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| 49 | |
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| 50 | /* I/O registers */ |
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| 51 | |
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| 52 | /* UART Baud Rate Register high */ |
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| 53 | #define UBRRH _SFR_IO8(0x03) |
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| 54 | |
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| 55 | /* ADC Data register */ |
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| 56 | #ifndef __ASSEMBLER__ |
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| 57 | #define ADC _SFR_IO16(0x04) |
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| 58 | #endif |
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| 59 | #define ADCW _SFR_IO16(0x04) |
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| 60 | #define ADCL _SFR_IO8(0x04) |
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| 61 | #define ADCH _SFR_IO8(0x05) |
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| 62 | |
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| 63 | /* ADC Control and Status Register */ |
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| 64 | #define ADCSR _SFR_IO8(0x06) |
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| 65 | |
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| 66 | /* ADC MUX */ |
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| 67 | #define ADMUX _SFR_IO8(0x07) |
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| 68 | |
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| 69 | /* Analog Comparator Control and Status Register */ |
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| 70 | #define ACSR _SFR_IO8(0x08) |
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| 71 | |
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| 72 | /* UART Baud Rate Register */ |
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| 73 | #define UBRR _SFR_IO8(0x09) |
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| 74 | |
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| 75 | /* UART Control/Status Registers */ |
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| 76 | #define UCSRB _SFR_IO8(0x0A) |
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| 77 | #define UCSRA _SFR_IO8(0x0B) |
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| 78 | |
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| 79 | /* UART I/O Data Register */ |
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| 80 | #define UDR _SFR_IO8(0x0C) |
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| 81 | |
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| 82 | /* SPI Control Register */ |
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| 83 | #define SPCR _SFR_IO8(0x0D) |
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| 84 | |
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| 85 | /* SPI Status Register */ |
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| 86 | #define SPSR _SFR_IO8(0x0E) |
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| 87 | |
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| 88 | /* SPI I/O Data Register */ |
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| 89 | #define SPDR _SFR_IO8(0x0F) |
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| 90 | |
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| 91 | /* Input Pins, Port D */ |
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| 92 | #define PIND _SFR_IO8(0x10) |
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| 93 | |
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| 94 | /* Data Direction Register, Port D */ |
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| 95 | #define DDRD _SFR_IO8(0x11) |
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| 96 | |
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| 97 | /* Data Register, Port D */ |
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| 98 | #define PORTD _SFR_IO8(0x12) |
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| 99 | |
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| 100 | /* Input Pins, Port C */ |
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| 101 | #define PINC _SFR_IO8(0x13) |
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| 102 | |
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| 103 | /* Data Direction Register, Port C */ |
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| 104 | #define DDRC _SFR_IO8(0x14) |
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| 105 | |
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| 106 | /* Data Register, Port C */ |
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| 107 | #define PORTC _SFR_IO8(0x15) |
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| 108 | |
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| 109 | /* Input Pins, Port B */ |
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| 110 | #define PINB _SFR_IO8(0x16) |
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| 111 | |
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| 112 | /* Data Direction Register, Port B */ |
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| 113 | #define DDRB _SFR_IO8(0x17) |
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| 114 | |
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| 115 | /* Data Register, Port B */ |
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| 116 | #define PORTB _SFR_IO8(0x18) |
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| 117 | |
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| 118 | /* EEPROM Control Register */ |
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| 119 | #define EECR _SFR_IO8(0x1C) |
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| 120 | |
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| 121 | /* EEPROM Data Register */ |
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| 122 | #define EEDR _SFR_IO8(0x1D) |
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| 123 | |
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| 124 | /* EEPROM Address Register */ |
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| 125 | #define EEAR _SFR_IO8(0x1E) |
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| 126 | #define EEARL _SFR_IO8(0x1E) |
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| 127 | |
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| 128 | /* Watchdog Timer Control Register */ |
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| 129 | #define WDTCR _SFR_IO8(0x21) |
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| 130 | |
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| 131 | /* T/C 1 Input Capture Register */ |
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| 132 | #define ICR1 _SFR_IO16(0x26) |
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| 133 | #define ICR1L _SFR_IO8(0x26) |
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| 134 | #define ICR1H _SFR_IO8(0x27) |
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| 135 | |
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| 136 | /* Timer/Counter1 Output Compare Register A */ |
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| 137 | #define OCR1 _SFR_IO16(0x2A) |
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| 138 | #define OCR1L _SFR_IO8(0x2A) |
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| 139 | #define OCR1H _SFR_IO8(0x2B) |
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| 140 | |
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| 141 | /* Timer/Counter 1 */ |
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| 142 | #define TCNT1 _SFR_IO16(0x2C) |
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| 143 | #define TCNT1L _SFR_IO8(0x2C) |
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| 144 | #define TCNT1H _SFR_IO8(0x2D) |
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| 145 | |
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| 146 | /* Timer/Counter 1 Control and Status Register */ |
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| 147 | #define TCCR1B _SFR_IO8(0x2E) |
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| 148 | |
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| 149 | /* Timer/Counter 1 Control Register */ |
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| 150 | #define TCCR1A _SFR_IO8(0x2F) |
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| 151 | |
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| 152 | /* Timer/Counter 0 */ |
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| 153 | #define TCNT0 _SFR_IO8(0x32) |
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| 154 | |
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| 155 | /* Timer/Counter 0 Control Register */ |
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| 156 | #define TCCR0 _SFR_IO8(0x33) |
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| 157 | |
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| 158 | /* MCU general Status Register */ |
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| 159 | #define MCUSR _SFR_IO8(0x34) |
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| 160 | |
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| 161 | /* MCU general Control Register */ |
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| 162 | #define MCUCR _SFR_IO8(0x35) |
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| 163 | |
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| 164 | /* Timer/Counter Interrupt Flag register */ |
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| 165 | #define TIFR _SFR_IO8(0x38) |
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| 166 | |
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| 167 | /* Timer/Counter Interrupt MaSK register */ |
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| 168 | #define TIMSK _SFR_IO8(0x39) |
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| 169 | |
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| 170 | /* General Interrupt Flag Register */ |
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| 171 | #define GIFR _SFR_IO8(0x3A) |
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| 172 | |
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| 173 | /* General Interrupt MaSK register */ |
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| 174 | #define GIMSK _SFR_IO8(0x3B) |
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| 175 | |
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| 176 | /* Interrupt vectors */ |
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| 177 | |
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| 178 | /* External Interrupt 0 */ |
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| 179 | #define INT0_vect _VECTOR(1) |
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| 180 | #define SIG_INTERRUPT0 _VECTOR(1) |
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| 181 | |
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| 182 | /* External Interrupt 1 */ |
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| 183 | #define INT1_vect _VECTOR(2) |
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| 184 | #define SIG_INTERRUPT1 _VECTOR(2) |
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| 185 | |
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| 186 | /* Timer/Counter Capture Event */ |
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| 187 | #define TIMER1_CAPT_vect _VECTOR(3) |
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| 188 | #define SIG_INPUT_CAPTURE1 _VECTOR(3) |
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| 189 | |
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| 190 | /* Timer/Counter1 Compare Match */ |
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| 191 | #define TIMER1_COMP_vect _VECTOR(4) |
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| 192 | #define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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| 193 | |
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| 194 | /* Timer/Counter1 Overflow */ |
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| 195 | #define TIMER1_OVF_vect _VECTOR(5) |
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| 196 | #define SIG_OVERFLOW1 _VECTOR(5) |
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| 197 | |
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| 198 | /* Timer/Counter0 Overflow */ |
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| 199 | #define TIMER0_OVF_vect _VECTOR(6) |
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| 200 | #define SIG_OVERFLOW0 _VECTOR(6) |
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| 201 | |
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| 202 | /* Serial Transfer Complete */ |
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| 203 | #define SPI_STC_vect _VECTOR(7) |
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| 204 | #define SIG_SPI _VECTOR(7) |
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| 205 | |
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| 206 | /* UART, Rx Complete */ |
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| 207 | #define UART_RX_vect _VECTOR(8) |
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| 208 | #define SIG_UART_RECV _VECTOR(8) |
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| 209 | |
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| 210 | /* UART Data Register Empty */ |
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| 211 | #define UART_UDRE_vect _VECTOR(9) |
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| 212 | #define SIG_UART_DATA _VECTOR(9) |
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| 213 | |
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| 214 | /* UART, Tx Complete */ |
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| 215 | #define UART_TX_vect _VECTOR(10) |
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| 216 | #define SIG_UART_TRANS _VECTOR(10) |
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| 217 | |
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| 218 | /* ADC Conversion Complete */ |
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| 219 | #define ADC_vect _VECTOR(11) |
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| 220 | #define SIG_ADC _VECTOR(11) |
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| 221 | |
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| 222 | /* EEPROM Ready */ |
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| 223 | #define EE_RDY_vect _VECTOR(12) |
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| 224 | #define SIG_EEPROM_READY _VECTOR(12) |
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| 225 | |
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| 226 | /* Analog Comparator */ |
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| 227 | #define ANA_COMP_vect _VECTOR(13) |
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| 228 | #define SIG_COMPARATOR _VECTOR(13) |
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| 229 | |
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| 230 | #define _VECTORS_SIZE 28 |
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| 231 | |
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| 232 | /* |
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| 233 | The Register Bit names are represented by their bit number (0-7). |
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| 234 | */ |
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| 235 | |
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| 236 | /* MCU general Status Register */ |
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| 237 | #define WDRF 3 |
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| 238 | #define BORF 2 |
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| 239 | #define EXTRF 1 |
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| 240 | #define PORF 0 |
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| 241 | |
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| 242 | /* General Interrupt MaSK register */ |
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| 243 | #define INT1 7 |
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| 244 | #define INT0 6 |
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| 245 | |
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| 246 | /* General Interrupt Flag Register */ |
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| 247 | #define INTF1 7 |
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| 248 | #define INTF0 6 |
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| 249 | |
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| 250 | /* Timer/Counter Interrupt MaSK register */ |
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| 251 | #define TOIE1 7 |
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| 252 | #define OCIE1 6 |
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| 253 | #define TICIE1 3 |
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| 254 | #define TOIE0 1 |
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| 255 | |
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| 256 | /* Timer/Counter Interrupt Flag register */ |
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| 257 | #define TOV1 7 |
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| 258 | #define OCF1 6 |
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| 259 | #define ICF1 3 |
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| 260 | #define TOV0 1 |
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| 261 | |
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| 262 | /* MCU general Control Register */ |
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| 263 | #define SE 5 |
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| 264 | #define SM 4 |
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| 265 | #define ISC11 3 |
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| 266 | #define ISC10 2 |
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| 267 | #define ISC01 1 |
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| 268 | #define ISC00 0 |
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| 269 | |
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| 270 | /* Timer/Counter 0 Control Register */ |
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| 271 | #define CS02 2 |
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| 272 | #define CS01 1 |
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| 273 | #define CS00 0 |
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| 274 | |
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| 275 | /* Timer/Counter 1 Control Register */ |
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| 276 | #define COM11 7 |
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| 277 | #define COM10 6 |
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| 278 | #define PWM11 1 |
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| 279 | #define PWM10 0 |
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| 280 | |
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| 281 | /* Timer/Counter 1 Control and Status Register */ |
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| 282 | #define ICNC1 7 |
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| 283 | #define ICES1 6 |
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| 284 | #define CTC1 3 |
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| 285 | #define CS12 2 |
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| 286 | #define CS11 1 |
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| 287 | #define CS10 0 |
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| 288 | |
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| 289 | /* Watchdog Timer Control Register */ |
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| 290 | #define WDTOE 4 |
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| 291 | #define WDE 3 |
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| 292 | #define WDP2 2 |
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| 293 | #define WDP1 1 |
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| 294 | #define WDP0 0 |
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| 295 | |
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| 296 | /* SPI Control Register */ |
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| 297 | #define SPIE 7 |
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| 298 | #define SPE 6 |
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| 299 | #define DORD 5 |
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| 300 | #define MSTR 4 |
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| 301 | #define CPOL 3 |
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| 302 | #define CPHA 2 |
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| 303 | #define SPR1 1 |
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| 304 | #define SPR0 0 |
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| 305 | |
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| 306 | /* SPI Status Register */ |
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| 307 | #define SPIF 7 |
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| 308 | #define WCOL 6 |
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| 309 | |
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| 310 | /* UART Status Register */ |
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| 311 | #define RXC 7 |
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| 312 | #define TXC 6 |
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| 313 | #define UDRE 5 |
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| 314 | #define FE 4 |
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| 315 | #define DOR 3 |
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| 316 | #define MPCM 0 |
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| 317 | |
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| 318 | /* UART Control Register */ |
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| 319 | #define RXCIE 7 |
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| 320 | #define TXCIE 6 |
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| 321 | #define UDRIE 5 |
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| 322 | #define RXEN 4 |
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| 323 | #define TXEN 3 |
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| 324 | #define CHR9 2 |
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| 325 | #define RXB8 1 |
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| 326 | #define TXB8 0 |
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| 327 | |
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| 328 | /* Analog Comparator Control and Status Register */ |
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| 329 | #define ACD 7 |
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| 330 | #define AINBG 6 |
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| 331 | #define ACO 5 |
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| 332 | #define ACI 4 |
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| 333 | #define ACIE 3 |
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| 334 | #define ACIC 2 |
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| 335 | #define ACIS1 1 |
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| 336 | #define ACIS0 0 |
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| 337 | |
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| 338 | /* ADC MUX */ |
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| 339 | #define ACDBG 6 |
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| 340 | #define MUX2 2 |
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| 341 | #define MUX1 1 |
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| 342 | #define MUX0 0 |
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| 343 | |
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| 344 | /* ADC Control and Status Register */ |
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| 345 | #define ADEN 7 |
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| 346 | #define ADSC 6 |
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| 347 | #define ADFR 5 |
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| 348 | #define ADIF 4 |
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| 349 | #define ADIE 3 |
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| 350 | #define ADPS2 2 |
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| 351 | #define ADPS1 1 |
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| 352 | #define ADPS0 0 |
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| 353 | |
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| 354 | /* Data Register, Port B */ |
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| 355 | #define PB5 5 |
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| 356 | #define PB4 4 |
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| 357 | #define PB3 3 |
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| 358 | #define PB2 2 |
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| 359 | #define PB1 1 |
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| 360 | #define PB0 0 |
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| 361 | |
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| 362 | /* Data Direction Register, Port B */ |
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| 363 | #define DDB5 5 |
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| 364 | #define DDB4 4 |
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| 365 | #define DDB3 3 |
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| 366 | #define DDB2 2 |
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| 367 | #define DDB1 1 |
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| 368 | #define DDB0 0 |
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| 369 | |
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| 370 | /* Input Pins, Port B */ |
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| 371 | #define PINB5 5 |
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| 372 | #define PINB4 4 |
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| 373 | #define PINB3 3 |
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| 374 | #define PINB2 2 |
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| 375 | #define PINB1 1 |
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| 376 | #define PINB0 0 |
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| 377 | |
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| 378 | /* Data Register, Port C */ |
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| 379 | #define PC5 5 |
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| 380 | #define PC4 4 |
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| 381 | #define PC3 3 |
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| 382 | #define PC2 2 |
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| 383 | #define PC1 1 |
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| 384 | #define PC0 0 |
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| 385 | |
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| 386 | /* Data Direction Register, Port C */ |
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| 387 | #define DDC5 5 |
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| 388 | #define DDC4 4 |
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| 389 | #define DDC3 3 |
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| 390 | #define DDC2 2 |
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| 391 | #define DDC1 1 |
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| 392 | #define DDC0 0 |
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| 393 | |
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| 394 | /* Input Pins, Port C */ |
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| 395 | #define PINC5 5 |
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| 396 | #define PINC4 4 |
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| 397 | #define PINC3 3 |
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| 398 | #define PINC2 2 |
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| 399 | #define PINC1 1 |
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| 400 | #define PINC0 0 |
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| 401 | |
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| 402 | /* Data Register, Port D */ |
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| 403 | #define PD7 7 |
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| 404 | #define PD6 6 |
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| 405 | #define PD5 5 |
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| 406 | #define PD4 4 |
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| 407 | #define PD3 3 |
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| 408 | #define PD2 2 |
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| 409 | #define PD1 1 |
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| 410 | #define PD0 0 |
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| 411 | |
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| 412 | /* Data Direction Register, Port D */ |
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| 413 | #define DDD7 7 |
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| 414 | #define DDD6 6 |
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| 415 | #define DDD5 5 |
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| 416 | #define DDD4 4 |
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| 417 | #define DDD3 3 |
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| 418 | #define DDD2 2 |
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| 419 | #define DDD1 1 |
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| 420 | #define DDD0 0 |
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| 421 | |
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| 422 | /* Input Pins, Port D */ |
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| 423 | #define PIND7 7 |
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| 424 | #define PIND6 6 |
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| 425 | #define PIND5 5 |
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| 426 | #define PIND4 4 |
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| 427 | #define PIND3 3 |
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| 428 | #define PIND2 2 |
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| 429 | #define PIND1 1 |
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| 430 | #define PIND0 0 |
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| 431 | |
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| 432 | /* EEPROM Control Register */ |
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| 433 | #define EERIE 3 |
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| 434 | #define EEMWE 2 |
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| 435 | #define EEWE 1 |
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| 436 | #define EERE 0 |
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| 437 | |
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| 438 | /* Constants */ |
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| 439 | #define RAMEND 0xDF /*Last On-Chip SRAM location*/ |
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| 440 | #define XRAMEND RAMEND |
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| 441 | #define E2END 0x7F |
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| 442 | #define FLASHEND 0x7FF |
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| 443 | |
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| 444 | #endif /* _AVR_IO2333_H_ */ |
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