1 | /* Copyright (c) 2002, Marek Michalkiewicz |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* avr/io2323.h - definitions for AT90S2323 */ |
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34 | |
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35 | #ifndef _AVR_IO2323_H_ |
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36 | #define _AVR_IO2323_H_ 1 |
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37 | |
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38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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39 | |
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40 | #ifndef _AVR_IO_H_ |
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41 | # error "Include <avr/io.h> instead of this file." |
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42 | #endif |
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43 | |
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44 | #ifndef _AVR_IOXXX_H_ |
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45 | # define _AVR_IOXXX_H_ "io2323.h" |
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46 | #else |
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47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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48 | #endif |
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49 | |
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50 | /* I/O registers */ |
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51 | |
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52 | /* Input Pins, Port B */ |
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53 | #define PINB _SFR_IO8(0x16) |
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54 | |
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55 | /* Data Direction Register, Port B */ |
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56 | #define DDRB _SFR_IO8(0x17) |
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57 | |
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58 | /* Data Register, Port B */ |
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59 | #define PORTB _SFR_IO8(0x18) |
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60 | |
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61 | /* EEPROM Control Register */ |
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62 | #define EECR _SFR_IO8(0x1C) |
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63 | |
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64 | /* EEPROM Data Register */ |
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65 | #define EEDR _SFR_IO8(0x1D) |
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66 | |
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67 | /* EEPROM Address Register */ |
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68 | #define EEAR _SFR_IO8(0x1E) |
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69 | #define EEARL _SFR_IO8(0x1E) |
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70 | |
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71 | /* Watchdog Timer Control Register */ |
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72 | #define WDTCR _SFR_IO8(0x21) |
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73 | |
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74 | /* Timer/Counter 0 */ |
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75 | #define TCNT0 _SFR_IO8(0x32) |
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76 | |
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77 | /* Timer/Counter 0 Control Register */ |
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78 | #define TCCR0 _SFR_IO8(0x33) |
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79 | |
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80 | /* MCU Status Register */ |
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81 | #define MCUSR _SFR_IO8(0x34) |
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82 | |
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83 | /* MCU general Control Register */ |
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84 | #define MCUCR _SFR_IO8(0x35) |
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85 | |
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86 | /* Timer/Counter Interrupt Flag register */ |
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87 | #define TIFR _SFR_IO8(0x38) |
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88 | |
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89 | /* Timer/Counter Interrupt MaSK register */ |
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90 | #define TIMSK _SFR_IO8(0x39) |
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91 | |
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92 | /* General Interrupt Flag register */ |
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93 | #define GIFR _SFR_IO8(0x3A) |
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94 | |
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95 | /* General Interrupt MaSK register */ |
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96 | #define GIMSK _SFR_IO8(0x3B) |
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97 | |
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98 | /* 0x3D..0x3E SP */ |
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99 | |
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100 | /* 0x3F SREG */ |
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101 | |
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102 | /* Interrupt vectors */ |
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103 | |
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104 | /* External Interrupt 0 */ |
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105 | #define INT0_vect _VECTOR(1) |
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106 | #define SIG_INTERRUPT0 _VECTOR(1) |
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107 | |
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108 | /* Timer/Counter0 Overflow */ |
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109 | #define TIMER0_OVF0_vect _VECTOR(2) |
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110 | #define SIG_OVERFLOW0 _VECTOR(2) |
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111 | |
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112 | #define _VECTORS_SIZE 6 |
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113 | |
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114 | /* |
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115 | The Register Bit names are represented by their bit number (0-7). |
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116 | */ |
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117 | |
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118 | /* General Interrupt MaSK register */ |
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119 | #define INT0 6 |
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120 | #define INTF0 6 |
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121 | |
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122 | /* General Interrupt Flag Register */ |
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123 | #define TOIE0 1 |
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124 | #define TOV0 1 |
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125 | |
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126 | /* MCU general Control Register */ |
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127 | #define SE 5 |
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128 | #define SM 4 |
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129 | #define ISC01 1 |
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130 | #define ISC00 0 |
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131 | |
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132 | /* Timer/Counter 0 Control Register */ |
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133 | #define CS02 2 |
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134 | #define CS01 1 |
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135 | #define CS00 0 |
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136 | |
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137 | /* Watchdog Timer Control Register */ |
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138 | #define WDTOE 4 |
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139 | #define WDE 3 |
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140 | #define WDP2 2 |
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141 | #define WDP1 1 |
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142 | #define WDP0 0 |
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143 | |
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144 | /* |
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145 | PB2 = SCK/T0 |
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146 | PB1 = MISO/INT0 |
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147 | PB0 = MOSI |
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148 | */ |
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149 | |
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150 | /* Data Register, Port B */ |
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151 | #define PB2 2 |
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152 | #define PB1 1 |
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153 | #define PB0 0 |
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154 | |
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155 | /* Data Direction Register, Port B */ |
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156 | #define DDB2 2 |
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157 | #define DDB1 1 |
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158 | #define DDB0 0 |
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159 | |
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160 | /* Input Pins, Port B */ |
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161 | #define PINB2 2 |
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162 | #define PINB1 1 |
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163 | #define PINB0 0 |
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164 | |
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165 | /* EEPROM Control Register */ |
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166 | #define EERIE 3 |
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167 | #define EEMWE 2 |
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168 | #define EEWE 1 |
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169 | #define EERE 0 |
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170 | |
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171 | /* Constants */ |
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172 | #define RAMEND 0xDF |
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173 | #define XRAMEND RAMEND |
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174 | #define E2END 0x7F |
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175 | #define E2PAGESIZE 0 |
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176 | #define FLASHEND 0x07FF |
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177 | |
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178 | |
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179 | /* Fuses */ |
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180 | #define FUSE_MEMORY_SIZE 1 |
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181 | |
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182 | /* Low Fuse Byte */ |
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183 | #define FUSE_FSTRT (unsigned char)~_BV(0) |
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184 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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185 | #define LFUSE_DEFAULT (0xFF) |
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186 | |
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187 | |
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188 | /* Lock Bits */ |
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189 | #define __LOCK_BITS_EXIST |
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190 | |
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191 | |
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192 | /* Signature */ |
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193 | #define SIGNATURE_0 0x1E |
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194 | #define SIGNATURE_1 0x91 |
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195 | #define SIGNATURE_2 0x02 |
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196 | |
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197 | |
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198 | #endif /* _AVR_IO2323_H_ */ |
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199 | |
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200 | /* Signature */ |
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201 | #define SIGNATURE_0 0x1E |
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202 | #define SIGNATURE_1 0x91 |
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203 | #define SIGNATURE_2 0x02 |
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204 | |
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