source: rtems/cpukit/score/cpu/avr/avr/boot.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 25.2 KB
Line 
1/* Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007  Eric B. Weddington
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9   * Redistributions in binary form must reproduce the above copyright
10     notice, this list of conditions and the following disclaimer in
11     the documentation and/or other materials provided with the
12     distribution.
13   * Neither the name of the copyright holders nor the names of
14     contributors may be used to endorse or promote products derived
15     from this software without specific prior written permission.
16
17  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27  POSSIBILITY OF SUCH DAMAGE. */
28
29/* $Id$ */
30
31#ifndef _AVR_BOOT_H_
32#define _AVR_BOOT_H_    1
33
34/** \file */
35/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
36    \code
37    #include <avr/io.h>
38    #include <avr/boot.h>
39    \endcode
40
41    The macros in this module provide a C language interface to the
42    bootloader support functionality of certain AVR processors. These
43    macros are designed to work with all sizes of flash memory.
44
45    Global interrupts are not automatically disabled for these macros. It
46    is left up to the programmer to do this. See the code example below.
47    Also see the processor datasheet for caveats on having global interrupts
48    enabled during writing of the Flash.
49
50    \note Not all AVR processors provide bootloader support. See your
51    processor datasheet to see if it provides bootloader support.
52
53    \todo From email with Marek: On smaller devices (all except ATmega64/128),
54    __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
55    instructions - since the boot loader has a limited size, this could be an
56    important optimization.
57
58    \par API Usage Example
59    The following code shows typical usage of the boot API.
60
61    \code
62    #include <inttypes.h>
63    #include <avr/interrupt.h>
64    #include <avr/pgmspace.h>
65   
66    void boot_program_page (uint32_t page, uint8_t *buf)
67    {
68        uint16_t i;
69        uint8_t sreg;
70
71        // Disable interrupts.
72
73        sreg = SREG;
74        cli();
75   
76        eeprom_busy_wait ();
77
78        boot_page_erase (page);
79        boot_spm_busy_wait ();      // Wait until the memory is erased.
80
81        for (i=0; i<SPM_PAGESIZE; i+=2)
82        {
83            // Set up little-endian word.
84
85            uint16_t w = *buf++;
86            w += (*buf++) << 8;
87       
88            boot_page_fill (page + i, w);
89        }
90
91        boot_page_write (page);     // Store buffer in flash page.
92        boot_spm_busy_wait();       // Wait until the memory is written.
93
94        // Reenable RWW-section again. We need this if we want to jump back
95        // to the application after bootloading.
96
97        boot_rww_enable ();
98
99        // Re-enable interrupts (if they were ever enabled).
100
101        SREG = sreg;
102    }\endcode */
103
104#include <avr/eeprom.h>
105#include <avr/io.h>
106#include <inttypes.h>
107#include <limits.h>
108
109/* Check for SPM Control Register in processor. */
110#if defined (SPMCSR)
111#  define __SPM_REG    SPMCSR
112#elif defined (SPMCR)
113#  define __SPM_REG    SPMCR
114#else
115#  error AVR processor does not provide bootloader support!
116#endif
117
118
119/* Check for SPM Enable bit. */
120#if defined(SPMEN)
121#  define __SPM_ENABLE  SPMEN
122#elif defined(SELFPRGEN)
123#  define __SPM_ENABLE  SELFPRGEN
124#else
125#  error Cannot find SPM Enable bit definition!
126#endif
127
128/** \ingroup avr_boot
129    \def BOOTLOADER_SECTION
130
131    Used to declare a function or variable to be placed into a
132    new section called .bootloader. This section and its contents
133    can then be relocated to any address (such as the bootloader
134    NRWW area) at link-time. */
135
136#define BOOTLOADER_SECTION    __attribute__ ((section (".bootloader")))
137
138/* Create common bit definitions. */
139#ifdef ASB
140#define __COMMON_ASB    ASB
141#else
142#define __COMMON_ASB    RWWSB
143#endif
144
145#ifdef ASRE
146#define __COMMON_ASRE   ASRE
147#else
148#define __COMMON_ASRE   RWWSRE
149#endif
150
151/* Define the bit positions of the Boot Lock Bits. */
152
153#define BLB12           5
154#define BLB11           4
155#define BLB02           3
156#define BLB01           2
157
158/** \ingroup avr_boot
159    \def boot_spm_interrupt_enable()
160    Enable the SPM interrupt. */
161
162#define boot_spm_interrupt_enable()   (__SPM_REG |= (uint8_t)_BV(SPMIE))
163
164/** \ingroup avr_boot
165    \def boot_spm_interrupt_disable()
166    Disable the SPM interrupt. */
167
168#define boot_spm_interrupt_disable()  (__SPM_REG &= (uint8_t)~_BV(SPMIE))
169
170/** \ingroup avr_boot
171    \def boot_is_spm_interrupt()
172    Check if the SPM interrupt is enabled. */
173
174#define boot_is_spm_interrupt()       (__SPM_REG & (uint8_t)_BV(SPMIE))
175
176/** \ingroup avr_boot
177    \def boot_rww_busy()
178    Check if the RWW section is busy. */
179
180#define boot_rww_busy()          (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
181
182/** \ingroup avr_boot
183    \def boot_spm_busy()
184    Check if the SPM instruction is busy. */
185
186#define boot_spm_busy()               (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
187
188/** \ingroup avr_boot
189    \def boot_spm_busy_wait()
190    Wait while the SPM instruction is busy. */
191
192#define boot_spm_busy_wait()          do{}while(boot_spm_busy())
193
194#define __BOOT_PAGE_ERASE         (_BV(__SPM_ENABLE) | _BV(PGERS))
195#define __BOOT_PAGE_WRITE         (_BV(__SPM_ENABLE) | _BV(PGWRT))
196#define __BOOT_PAGE_FILL          _BV(__SPM_ENABLE)
197#define __BOOT_RWW_ENABLE         (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
198#define __BOOT_LOCK_BITS_SET      (_BV(__SPM_ENABLE) | _BV(BLBSET))
199
200#define __boot_page_fill_normal(address, data)   \
201(__extension__({                                 \
202    __asm__ __volatile__                         \
203    (                                            \
204        "movw  r0, %3\n\t"                       \
205        "sts %0, %1\n\t"                         \
206        "spm\n\t"                                \
207        "clr  r1\n\t"                            \
208        :                                        \
209        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
210          "r" ((uint8_t)__BOOT_PAGE_FILL),       \
211          "z" ((uint16_t)address),               \
212          "r" ((uint16_t)data)                   \
213        : "r0"                                   \
214    );                                           \
215}))
216
217#define __boot_page_fill_alternate(address, data)\
218(__extension__({                                 \
219    __asm__ __volatile__                         \
220    (                                            \
221        "movw  r0, %3\n\t"                       \
222        "sts %0, %1\n\t"                         \
223        "spm\n\t"                                \
224        ".word 0xffff\n\t"                       \
225        "nop\n\t"                                \
226        "clr  r1\n\t"                            \
227        :                                        \
228        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
229          "r" ((uint8_t)__BOOT_PAGE_FILL),       \
230          "z" ((uint16_t)address),               \
231          "r" ((uint16_t)data)                   \
232        : "r0"                                   \
233    );                                           \
234}))
235
236#define __boot_page_fill_extended(address, data) \
237(__extension__({                                 \
238    __asm__ __volatile__                         \
239    (                                            \
240        "movw  r0, %4\n\t"                       \
241        "movw r30, %A3\n\t"                      \
242        "sts %1, %C3\n\t"                        \
243        "sts %0, %2\n\t"                         \
244        "spm\n\t"                                \
245        "clr  r1\n\t"                            \
246        :                                        \
247        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
248          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
249          "r" ((uint8_t)__BOOT_PAGE_FILL),       \
250          "r" ((uint32_t)address),               \
251          "r" ((uint16_t)data)                   \
252        : "r0", "r30", "r31"                     \
253    );                                           \
254}))
255
256#define __boot_page_erase_normal(address)        \
257(__extension__({                                 \
258    __asm__ __volatile__                         \
259    (                                            \
260        "sts %0, %1\n\t"                         \
261        "spm\n\t"                                \
262        :                                        \
263        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
264          "r" ((uint8_t)__BOOT_PAGE_ERASE),      \
265          "z" ((uint16_t)address)                \
266    );                                           \
267}))
268
269#define __boot_page_erase_alternate(address)     \
270(__extension__({                                 \
271    __asm__ __volatile__                         \
272    (                                            \
273        "sts %0, %1\n\t"                         \
274        "spm\n\t"                                \
275        ".word 0xffff\n\t"                       \
276        "nop\n\t"                                \
277        :                                        \
278        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
279          "r" ((uint8_t)__BOOT_PAGE_ERASE),      \
280          "z" ((uint16_t)address)                \
281    );                                           \
282}))
283
284#define __boot_page_erase_extended(address)      \
285(__extension__({                                 \
286    __asm__ __volatile__                         \
287    (                                            \
288        "movw r30, %A3\n\t"                      \
289        "sts  %1, %C3\n\t"                       \
290        "sts %0, %2\n\t"                         \
291        "spm\n\t"                                \
292        :                                        \
293        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
294          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
295          "r" ((uint8_t)__BOOT_PAGE_ERASE),      \
296          "r" ((uint32_t)address)                \
297        : "r30", "r31"                           \
298    );                                           \
299}))
300
301#define __boot_page_write_normal(address)        \
302(__extension__({                                 \
303    __asm__ __volatile__                         \
304    (                                            \
305        "sts %0, %1\n\t"                         \
306        "spm\n\t"                                \
307        :                                        \
308        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
309          "r" ((uint8_t)__BOOT_PAGE_WRITE),      \
310          "z" ((uint16_t)address)                \
311    );                                           \
312}))
313
314#define __boot_page_write_alternate(address)     \
315(__extension__({                                 \
316    __asm__ __volatile__                         \
317    (                                            \
318        "sts %0, %1\n\t"                         \
319        "spm\n\t"                                \
320        ".word 0xffff\n\t"                       \
321        "nop\n\t"                                \
322        :                                        \
323        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
324          "r" ((uint8_t)__BOOT_PAGE_WRITE),      \
325          "z" ((uint16_t)address)                \
326    );                                           \
327}))
328
329#define __boot_page_write_extended(address)      \
330(__extension__({                                 \
331    __asm__ __volatile__                         \
332    (                                            \
333        "movw r30, %A3\n\t"                      \
334        "sts %1, %C3\n\t"                        \
335        "sts %0, %2\n\t"                         \
336        "spm\n\t"                                \
337        :                                        \
338        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
339          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
340          "r" ((uint8_t)__BOOT_PAGE_WRITE),      \
341          "r" ((uint32_t)address)                \
342        : "r30", "r31"                           \
343    );                                           \
344}))
345
346#define __boot_rww_enable()                      \
347(__extension__({                                 \
348    __asm__ __volatile__                         \
349    (                                            \
350        "sts %0, %1\n\t"                         \
351        "spm\n\t"                                \
352        :                                        \
353        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
354          "r" ((uint8_t)__BOOT_RWW_ENABLE)       \
355    );                                           \
356}))
357
358#define __boot_rww_enable_alternate()            \
359(__extension__({                                 \
360    __asm__ __volatile__                         \
361    (                                            \
362        "sts %0, %1\n\t"                         \
363        "spm\n\t"                                \
364        ".word 0xffff\n\t"                       \
365        "nop\n\t"                                \
366        :                                        \
367        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
368          "r" ((uint8_t)__BOOT_RWW_ENABLE)       \
369    );                                           \
370}))
371
372/* From the mega16/mega128 data sheets (maybe others):
373
374     Bits by SPM To set the Boot Loader Lock bits, write the desired data to
375     R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
376     after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
377     that may prevent the Application and Boot Loader section from any
378     software update by the MCU.
379
380     If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
381     will be programmed if an SPM instruction is executed within four cycles
382     after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
383     don't care during this operation, but for future compatibility it is
384     recommended to load the Z-pointer with $0001 (same as used for reading the
385     Lock bits). For future compatibility It is also recommended to set bits 7,
386     6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
387     Lock bits the entire Flash can be read during the operation. */
388
389#define __boot_lock_bits_set(lock_bits)                    \
390(__extension__({                                           \
391    uint8_t value = (uint8_t)(~(lock_bits));               \
392    __asm__ __volatile__                                   \
393    (                                                      \
394        "ldi r30, 1\n\t"                                   \
395        "ldi r31, 0\n\t"                                   \
396        "mov r0, %2\n\t"                                   \
397        "sts %0, %1\n\t"                                   \
398        "spm\n\t"                                          \
399        :                                                  \
400        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
401          "r" ((uint8_t)__BOOT_LOCK_BITS_SET),             \
402          "r" (value)                                      \
403        : "r0", "r30", "r31"                               \
404    );                                                     \
405}))
406
407#define __boot_lock_bits_set_alternate(lock_bits)          \
408(__extension__({                                           \
409    uint8_t value = (uint8_t)(~(lock_bits));               \
410    __asm__ __volatile__                                   \
411    (                                                      \
412        "ldi r30, 1\n\t"                                   \
413        "ldi r31, 0\n\t"                                   \
414        "mov r0, %2\n\t"                                   \
415        "sts %0, %1\n\t"                                   \
416        "spm\n\t"                                          \
417        ".word 0xffff\n\t"                                 \
418        "nop\n\t"                                          \
419        :                                                  \
420        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
421          "r" ((uint8_t)__BOOT_LOCK_BITS_SET),             \
422          "r" (value)                                      \
423        : "r0", "r30", "r31"                               \
424    );                                                     \
425}))
426
427/*
428   Reading lock and fuse bits:
429
430     Similarly to writing the lock bits above, set BLBSET and SPMEN (or
431     SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
432     LPM instruction.
433
434     Z address:       contents:
435     0x0000           low fuse bits
436     0x0001           lock bits
437     0x0002           extended fuse bits
438     0x0003           high fuse bits
439
440     Sounds confusing, doesn't it?
441
442     Unlike the macros in pgmspace.h, no need to care for non-enhanced
443     cores here as these old cores do not provide SPM support anyway.
444 */
445
446/** \ingroup avr_boot
447    \def GET_LOW_FUSE_BITS
448    address to read the low fuse bits, using boot_lock_fuse_bits_get
449 */
450#define GET_LOW_FUSE_BITS           (0x0000)
451/** \ingroup avr_boot
452    \def GET_LOCK_BITS
453    address to read the lock bits, using boot_lock_fuse_bits_get
454 */
455#define GET_LOCK_BITS               (0x0001)
456/** \ingroup avr_boot
457    \def GET_EXTENDED_FUSE_BITS
458    address to read the extended fuse bits, using boot_lock_fuse_bits_get
459 */
460#define GET_EXTENDED_FUSE_BITS      (0x0002)
461/** \ingroup avr_boot
462    \def GET_HIGH_FUSE_BITS
463    address to read the high fuse bits, using boot_lock_fuse_bits_get
464 */
465#define GET_HIGH_FUSE_BITS          (0x0003)
466
467/** \ingroup avr_boot
468    \def boot_lock_fuse_bits_get(address)
469
470    Read the lock or fuse bits at \c address.
471
472    Parameter \c address can be any of GET_LOW_FUSE_BITS,
473    GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
474
475    \note The lock and fuse bits returned are the physical values,
476    i.e. a bit returned as 0 means the corresponding fuse or lock bit
477    is programmed.
478 */
479#define boot_lock_fuse_bits_get(address)                   \
480(__extension__({                                           \
481    uint8_t __result;                                      \
482    __asm__ __volatile__                                   \
483    (                                                      \
484        "ldi r30, %3\n\t"                                  \
485        "ldi r31, 0\n\t"                                   \
486        "sts %1, %2\n\t"                                   \
487        "lpm %0, Z\n\t"                                    \
488        : "=r" (__result)                                  \
489        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
490          "r" ((uint8_t)__BOOT_LOCK_BITS_SET),             \
491          "M" (address)                                    \
492        : "r0", "r30", "r31"                               \
493    );                                                     \
494    __result;                                              \
495}))
496
497/** \ingroup avr_boot
498    \def boot_signature_byte_get(address)
499
500    Read the Signature Row byte at \c address.  For some MCU types,
501    this function can also retrieve the factory-stored oscillator
502    calibration bytes.
503
504    Parameter \c address can be 0-0x1f as documented by the datasheet.
505    \note The values are MCU type dependent.
506*/
507
508#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
509
510#define boot_signature_byte_get(addr) \
511(__extension__({                      \
512      uint16_t __addr16 = (uint16_t)(addr);     \
513      uint8_t __result;                         \
514      __asm__ __volatile__                      \
515      (                                         \
516        "sts %1, %2\n\t"                        \
517        "lpm %0, Z" "\n\t"                      \
518        : "=r" (__result)                       \
519        : "i" (_SFR_MEM_ADDR(__SPM_REG)),       \
520          "r" ((uint8_t) __BOOT_SIGROW_READ),   \
521          "z" (__addr16)                        \
522      );                                        \
523      __result;                                 \
524}))
525
526/** \ingroup avr_boot
527    \def boot_page_fill(address, data)
528
529    Fill the bootloader temporary page buffer for flash
530    address with data word.
531
532    \note The address is a byte address. The data is a word. The AVR
533    writes data to the buffer a word at a time, but addresses the buffer
534    per byte! So, increment your address by 2 between calls, and send 2
535    data bytes in a word format! The LSB of the data is written to the lower
536    address; the MSB of the data is written to the higher address.*/
537
538/** \ingroup avr_boot
539    \def boot_page_erase(address)
540
541    Erase the flash page that contains address.
542
543    \note address is a byte address in flash, not a word address. */
544
545/** \ingroup avr_boot
546    \def boot_page_write(address)
547
548    Write the bootloader temporary page buffer
549    to flash page that contains address.
550   
551    \note address is a byte address in flash, not a word address. */
552
553/** \ingroup avr_boot
554    \def boot_rww_enable()
555
556    Enable the Read-While-Write memory section. */
557
558/** \ingroup avr_boot
559    \def boot_lock_bits_set(lock_bits)
560
561    Set the bootloader lock bits.
562
563    \param lock_bits A mask of which Boot Loader Lock Bits to set.
564
565    \note In this context, a 'set bit' will be written to a zero value.
566    Note also that only BLBxx bits can be programmed by this command.
567
568    For example, to disallow the SPM instruction from writing to the Boot
569    Loader memory section of flash, you would use this macro as such:
570
571    \code
572    boot_lock_bits_set (_BV (BLB11));
573    \endcode
574
575    \note Like any lock bits, the Boot Loader Lock Bits, once set,
576    cannot be cleared again except by a chip erase which will in turn
577    also erase the boot loader itself. */
578
579/* Normal versions of the macros use 16-bit addresses.
580   Extended versions of the macros use 32-bit addresses.
581   Alternate versions of the macros use 16-bit addresses and require special
582   instruction sequences after LPM.
583
584   FLASHEND is defined in the ioXXXX.h file.
585   USHRT_MAX is defined in <limits.h>. */ 
586
587#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
588    || defined(__AVR_ATmega323__)
589
590/* Alternate: ATmega161/163/323 and 16 bit address */
591#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
592#define boot_page_erase(address)      __boot_page_erase_alternate(address)
593#define boot_page_write(address)      __boot_page_write_alternate(address)
594#define boot_rww_enable()             __boot_rww_enable_alternate()
595#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
596
597#elif (FLASHEND > USHRT_MAX)
598
599/* Extended: >16 bit address */
600#define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
601#define boot_page_erase(address)      __boot_page_erase_extended(address)
602#define boot_page_write(address)      __boot_page_write_extended(address)
603#define boot_rww_enable()             __boot_rww_enable()
604#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
605
606#else
607
608/* Normal: 16 bit address */
609#define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
610#define boot_page_erase(address)      __boot_page_erase_normal(address)
611#define boot_page_write(address)      __boot_page_write_normal(address)
612#define boot_rww_enable()             __boot_rww_enable()
613#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
614
615#endif
616
617/** \ingroup avr_boot
618
619    Same as boot_page_fill() except it waits for eeprom and spm operations to
620    complete before filling the page. */
621
622#define boot_page_fill_safe(address, data) \
623do { \
624    boot_spm_busy_wait();                       \
625    eeprom_busy_wait();                         \
626    boot_page_fill(address, data);              \
627} while (0)
628
629/** \ingroup avr_boot
630
631    Same as boot_page_erase() except it waits for eeprom and spm operations to
632    complete before erasing the page. */
633
634#define boot_page_erase_safe(address) \
635do { \
636    boot_spm_busy_wait();                       \
637    eeprom_busy_wait();                         \
638    boot_page_erase (address);                  \
639} while (0)
640
641/** \ingroup avr_boot
642
643    Same as boot_page_write() except it waits for eeprom and spm operations to
644    complete before writing the page. */
645
646#define boot_page_write_safe(address) \
647do { \
648    boot_spm_busy_wait();                       \
649    eeprom_busy_wait();                         \
650    boot_page_write (address);                  \
651} while (0)
652
653/** \ingroup avr_boot
654
655    Same as boot_rww_enable() except waits for eeprom and spm operations to
656    complete before enabling the RWW mameory. */
657
658#define boot_rww_enable_safe() \
659do { \
660    boot_spm_busy_wait();                       \
661    eeprom_busy_wait();                         \
662    boot_rww_enable();                          \
663} while (0)
664
665/** \ingroup avr_boot
666
667    Same as boot_lock_bits_set() except waits for eeprom and spm operations to
668    complete before setting the lock bits. */
669
670#define boot_lock_bits_set_safe(lock_bits) \
671do { \
672    boot_spm_busy_wait();                       \
673    eeprom_busy_wait();                         \
674    boot_lock_bits_set (lock_bits);             \
675} while (0)
676
677#endif /* _AVR_BOOT_H_ */
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