[04a62dce] | 1 | /* Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007 Eric B. Weddington |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | * Redistributions in binary form must reproduce the above copyright |
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| 10 | notice, this list of conditions and the following disclaimer in |
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| 11 | the documentation and/or other materials provided with the |
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| 12 | distribution. |
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| 13 | * Neither the name of the copyright holders nor the names of |
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| 14 | contributors may be used to endorse or promote products derived |
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| 15 | from this software without specific prior written permission. |
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| 16 | |
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| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 27 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 28 | |
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| 29 | /* $Id$ */ |
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| 30 | |
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| 31 | #ifndef _AVR_BOOT_H_ |
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| 32 | #define _AVR_BOOT_H_ 1 |
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| 33 | |
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| 34 | /** \file */ |
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| 35 | /** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities |
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| 36 | \code |
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| 37 | #include <avr/io.h> |
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| 38 | #include <avr/boot.h> |
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| 39 | \endcode |
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| 40 | |
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| 41 | The macros in this module provide a C language interface to the |
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| 42 | bootloader support functionality of certain AVR processors. These |
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| 43 | macros are designed to work with all sizes of flash memory. |
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| 44 | |
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| 45 | Global interrupts are not automatically disabled for these macros. It |
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| 46 | is left up to the programmer to do this. See the code example below. |
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| 47 | Also see the processor datasheet for caveats on having global interrupts |
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| 48 | enabled during writing of the Flash. |
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| 49 | |
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| 50 | \note Not all AVR processors provide bootloader support. See your |
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| 51 | processor datasheet to see if it provides bootloader support. |
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| 52 | |
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| 53 | \todo From email with Marek: On smaller devices (all except ATmega64/128), |
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| 54 | __SPM_REG is in the I/O space, accessible with the shorter "in" and "out" |
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| 55 | instructions - since the boot loader has a limited size, this could be an |
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| 56 | important optimization. |
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| 57 | |
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| 58 | \par API Usage Example |
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| 59 | The following code shows typical usage of the boot API. |
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| 60 | |
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| 61 | \code |
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| 62 | #include <inttypes.h> |
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| 63 | #include <avr/interrupt.h> |
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| 64 | #include <avr/pgmspace.h> |
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| 65 | |
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| 66 | void boot_program_page (uint32_t page, uint8_t *buf) |
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| 67 | { |
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| 68 | uint16_t i; |
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| 69 | uint8_t sreg; |
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| 70 | |
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| 71 | // Disable interrupts. |
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| 72 | |
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| 73 | sreg = SREG; |
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| 74 | cli(); |
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| 75 | |
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| 76 | eeprom_busy_wait (); |
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| 77 | |
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| 78 | boot_page_erase (page); |
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| 79 | boot_spm_busy_wait (); // Wait until the memory is erased. |
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| 80 | |
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| 81 | for (i=0; i<SPM_PAGESIZE; i+=2) |
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| 82 | { |
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| 83 | // Set up little-endian word. |
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| 84 | |
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| 85 | uint16_t w = *buf++; |
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| 86 | w += (*buf++) << 8; |
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| 87 | |
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| 88 | boot_page_fill (page + i, w); |
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| 89 | } |
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| 90 | |
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| 91 | boot_page_write (page); // Store buffer in flash page. |
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| 92 | boot_spm_busy_wait(); // Wait until the memory is written. |
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| 93 | |
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| 94 | // Reenable RWW-section again. We need this if we want to jump back |
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| 95 | // to the application after bootloading. |
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| 96 | |
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| 97 | boot_rww_enable (); |
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| 98 | |
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| 99 | // Re-enable interrupts (if they were ever enabled). |
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| 100 | |
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| 101 | SREG = sreg; |
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| 102 | }\endcode */ |
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| 103 | |
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| 104 | #include <avr/eeprom.h> |
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| 105 | #include <avr/io.h> |
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| 106 | #include <inttypes.h> |
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| 107 | #include <limits.h> |
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| 108 | |
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| 109 | /* Check for SPM Control Register in processor. */ |
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| 110 | #if defined (SPMCSR) |
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| 111 | # define __SPM_REG SPMCSR |
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| 112 | #elif defined (SPMCR) |
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| 113 | # define __SPM_REG SPMCR |
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| 114 | #else |
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| 115 | # error AVR processor does not provide bootloader support! |
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| 116 | #endif |
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| 117 | |
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| 118 | |
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| 119 | /* Check for SPM Enable bit. */ |
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| 120 | #if defined(SPMEN) |
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| 121 | # define __SPM_ENABLE SPMEN |
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| 122 | #elif defined(SELFPRGEN) |
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| 123 | # define __SPM_ENABLE SELFPRGEN |
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| 124 | #else |
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| 125 | # error Cannot find SPM Enable bit definition! |
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| 126 | #endif |
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| 127 | |
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| 128 | /** \ingroup avr_boot |
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| 129 | \def BOOTLOADER_SECTION |
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| 130 | |
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| 131 | Used to declare a function or variable to be placed into a |
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| 132 | new section called .bootloader. This section and its contents |
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| 133 | can then be relocated to any address (such as the bootloader |
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| 134 | NRWW area) at link-time. */ |
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| 135 | |
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| 136 | #define BOOTLOADER_SECTION __attribute__ ((section (".bootloader"))) |
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| 137 | |
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| 138 | /* Create common bit definitions. */ |
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| 139 | #ifdef ASB |
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| 140 | #define __COMMON_ASB ASB |
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| 141 | #else |
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| 142 | #define __COMMON_ASB RWWSB |
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| 143 | #endif |
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| 144 | |
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| 145 | #ifdef ASRE |
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| 146 | #define __COMMON_ASRE ASRE |
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| 147 | #else |
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| 148 | #define __COMMON_ASRE RWWSRE |
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| 149 | #endif |
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| 150 | |
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| 151 | /* Define the bit positions of the Boot Lock Bits. */ |
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| 152 | |
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| 153 | #define BLB12 5 |
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| 154 | #define BLB11 4 |
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| 155 | #define BLB02 3 |
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| 156 | #define BLB01 2 |
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| 157 | |
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| 158 | /** \ingroup avr_boot |
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| 159 | \def boot_spm_interrupt_enable() |
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| 160 | Enable the SPM interrupt. */ |
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| 161 | |
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| 162 | #define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE)) |
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| 163 | |
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| 164 | /** \ingroup avr_boot |
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| 165 | \def boot_spm_interrupt_disable() |
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| 166 | Disable the SPM interrupt. */ |
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| 167 | |
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| 168 | #define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE)) |
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| 169 | |
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| 170 | /** \ingroup avr_boot |
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| 171 | \def boot_is_spm_interrupt() |
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| 172 | Check if the SPM interrupt is enabled. */ |
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| 173 | |
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| 174 | #define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE)) |
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| 175 | |
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| 176 | /** \ingroup avr_boot |
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| 177 | \def boot_rww_busy() |
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| 178 | Check if the RWW section is busy. */ |
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| 179 | |
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| 180 | #define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB)) |
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| 181 | |
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| 182 | /** \ingroup avr_boot |
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| 183 | \def boot_spm_busy() |
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| 184 | Check if the SPM instruction is busy. */ |
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| 185 | |
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| 186 | #define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE)) |
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| 187 | |
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| 188 | /** \ingroup avr_boot |
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| 189 | \def boot_spm_busy_wait() |
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| 190 | Wait while the SPM instruction is busy. */ |
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| 191 | |
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| 192 | #define boot_spm_busy_wait() do{}while(boot_spm_busy()) |
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| 193 | |
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| 194 | #define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS)) |
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| 195 | #define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT)) |
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| 196 | #define __BOOT_PAGE_FILL _BV(__SPM_ENABLE) |
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| 197 | #define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE)) |
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| 198 | #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET)) |
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| 199 | |
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| 200 | #define __boot_page_fill_normal(address, data) \ |
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| 201 | (__extension__({ \ |
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| 202 | __asm__ __volatile__ \ |
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| 203 | ( \ |
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| 204 | "movw r0, %3\n\t" \ |
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| 205 | "sts %0, %1\n\t" \ |
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| 206 | "spm\n\t" \ |
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| 207 | "clr r1\n\t" \ |
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| 208 | : \ |
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| 209 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 210 | "r" ((uint8_t)__BOOT_PAGE_FILL), \ |
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| 211 | "z" ((uint16_t)address), \ |
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| 212 | "r" ((uint16_t)data) \ |
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| 213 | : "r0" \ |
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| 214 | ); \ |
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| 215 | })) |
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| 216 | |
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| 217 | #define __boot_page_fill_alternate(address, data)\ |
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| 218 | (__extension__({ \ |
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| 219 | __asm__ __volatile__ \ |
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| 220 | ( \ |
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| 221 | "movw r0, %3\n\t" \ |
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| 222 | "sts %0, %1\n\t" \ |
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| 223 | "spm\n\t" \ |
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| 224 | ".word 0xffff\n\t" \ |
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| 225 | "nop\n\t" \ |
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| 226 | "clr r1\n\t" \ |
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| 227 | : \ |
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| 228 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 229 | "r" ((uint8_t)__BOOT_PAGE_FILL), \ |
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| 230 | "z" ((uint16_t)address), \ |
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| 231 | "r" ((uint16_t)data) \ |
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| 232 | : "r0" \ |
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| 233 | ); \ |
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| 234 | })) |
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| 235 | |
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| 236 | #define __boot_page_fill_extended(address, data) \ |
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| 237 | (__extension__({ \ |
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| 238 | __asm__ __volatile__ \ |
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| 239 | ( \ |
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| 240 | "movw r0, %4\n\t" \ |
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| 241 | "movw r30, %A3\n\t" \ |
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| 242 | "sts %1, %C3\n\t" \ |
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| 243 | "sts %0, %2\n\t" \ |
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| 244 | "spm\n\t" \ |
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| 245 | "clr r1\n\t" \ |
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| 246 | : \ |
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| 247 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 248 | "i" (_SFR_MEM_ADDR(RAMPZ)), \ |
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| 249 | "r" ((uint8_t)__BOOT_PAGE_FILL), \ |
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| 250 | "r" ((uint32_t)address), \ |
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| 251 | "r" ((uint16_t)data) \ |
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| 252 | : "r0", "r30", "r31" \ |
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| 253 | ); \ |
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| 254 | })) |
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| 255 | |
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| 256 | #define __boot_page_erase_normal(address) \ |
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| 257 | (__extension__({ \ |
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| 258 | __asm__ __volatile__ \ |
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| 259 | ( \ |
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| 260 | "sts %0, %1\n\t" \ |
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| 261 | "spm\n\t" \ |
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| 262 | : \ |
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| 263 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 264 | "r" ((uint8_t)__BOOT_PAGE_ERASE), \ |
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| 265 | "z" ((uint16_t)address) \ |
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| 266 | ); \ |
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| 267 | })) |
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| 268 | |
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| 269 | #define __boot_page_erase_alternate(address) \ |
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| 270 | (__extension__({ \ |
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| 271 | __asm__ __volatile__ \ |
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| 272 | ( \ |
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| 273 | "sts %0, %1\n\t" \ |
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| 274 | "spm\n\t" \ |
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| 275 | ".word 0xffff\n\t" \ |
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| 276 | "nop\n\t" \ |
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| 277 | : \ |
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| 278 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 279 | "r" ((uint8_t)__BOOT_PAGE_ERASE), \ |
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| 280 | "z" ((uint16_t)address) \ |
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| 281 | ); \ |
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| 282 | })) |
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| 283 | |
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| 284 | #define __boot_page_erase_extended(address) \ |
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| 285 | (__extension__({ \ |
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| 286 | __asm__ __volatile__ \ |
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| 287 | ( \ |
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| 288 | "movw r30, %A3\n\t" \ |
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| 289 | "sts %1, %C3\n\t" \ |
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| 290 | "sts %0, %2\n\t" \ |
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| 291 | "spm\n\t" \ |
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| 292 | : \ |
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| 293 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 294 | "i" (_SFR_MEM_ADDR(RAMPZ)), \ |
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| 295 | "r" ((uint8_t)__BOOT_PAGE_ERASE), \ |
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| 296 | "r" ((uint32_t)address) \ |
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| 297 | : "r30", "r31" \ |
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| 298 | ); \ |
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| 299 | })) |
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| 300 | |
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| 301 | #define __boot_page_write_normal(address) \ |
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| 302 | (__extension__({ \ |
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| 303 | __asm__ __volatile__ \ |
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| 304 | ( \ |
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| 305 | "sts %0, %1\n\t" \ |
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| 306 | "spm\n\t" \ |
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| 307 | : \ |
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| 308 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 309 | "r" ((uint8_t)__BOOT_PAGE_WRITE), \ |
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| 310 | "z" ((uint16_t)address) \ |
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| 311 | ); \ |
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| 312 | })) |
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| 313 | |
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| 314 | #define __boot_page_write_alternate(address) \ |
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| 315 | (__extension__({ \ |
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| 316 | __asm__ __volatile__ \ |
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| 317 | ( \ |
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| 318 | "sts %0, %1\n\t" \ |
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| 319 | "spm\n\t" \ |
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| 320 | ".word 0xffff\n\t" \ |
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| 321 | "nop\n\t" \ |
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| 322 | : \ |
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| 323 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 324 | "r" ((uint8_t)__BOOT_PAGE_WRITE), \ |
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| 325 | "z" ((uint16_t)address) \ |
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| 326 | ); \ |
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| 327 | })) |
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| 328 | |
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| 329 | #define __boot_page_write_extended(address) \ |
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| 330 | (__extension__({ \ |
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| 331 | __asm__ __volatile__ \ |
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| 332 | ( \ |
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| 333 | "movw r30, %A3\n\t" \ |
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| 334 | "sts %1, %C3\n\t" \ |
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| 335 | "sts %0, %2\n\t" \ |
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| 336 | "spm\n\t" \ |
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| 337 | : \ |
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| 338 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 339 | "i" (_SFR_MEM_ADDR(RAMPZ)), \ |
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| 340 | "r" ((uint8_t)__BOOT_PAGE_WRITE), \ |
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| 341 | "r" ((uint32_t)address) \ |
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| 342 | : "r30", "r31" \ |
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| 343 | ); \ |
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| 344 | })) |
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| 345 | |
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| 346 | #define __boot_rww_enable() \ |
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| 347 | (__extension__({ \ |
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| 348 | __asm__ __volatile__ \ |
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| 349 | ( \ |
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| 350 | "sts %0, %1\n\t" \ |
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| 351 | "spm\n\t" \ |
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| 352 | : \ |
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| 353 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 354 | "r" ((uint8_t)__BOOT_RWW_ENABLE) \ |
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| 355 | ); \ |
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| 356 | })) |
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| 357 | |
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| 358 | #define __boot_rww_enable_alternate() \ |
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| 359 | (__extension__({ \ |
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| 360 | __asm__ __volatile__ \ |
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| 361 | ( \ |
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| 362 | "sts %0, %1\n\t" \ |
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| 363 | "spm\n\t" \ |
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| 364 | ".word 0xffff\n\t" \ |
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| 365 | "nop\n\t" \ |
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| 366 | : \ |
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| 367 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 368 | "r" ((uint8_t)__BOOT_RWW_ENABLE) \ |
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| 369 | ); \ |
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| 370 | })) |
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| 371 | |
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| 372 | /* From the mega16/mega128 data sheets (maybe others): |
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| 373 | |
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| 374 | Bits by SPM To set the Boot Loader Lock bits, write the desired data to |
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| 375 | R0, write "X0001001" to SPMCR and execute SPM within four clock cycles |
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| 376 | after writing SPMCR. The only accessible Lock bits are the Boot Lock bits |
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| 377 | that may prevent the Application and Boot Loader section from any |
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| 378 | software update by the MCU. |
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| 379 | |
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| 380 | If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit |
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| 381 | will be programmed if an SPM instruction is executed within four cycles |
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| 382 | after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is |
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| 383 | don't care during this operation, but for future compatibility it is |
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| 384 | recommended to load the Z-pointer with $0001 (same as used for reading the |
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| 385 | Lock bits). For future compatibility It is also recommended to set bits 7, |
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| 386 | 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the |
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| 387 | Lock bits the entire Flash can be read during the operation. */ |
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| 388 | |
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| 389 | #define __boot_lock_bits_set(lock_bits) \ |
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| 390 | (__extension__({ \ |
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| 391 | uint8_t value = (uint8_t)(~(lock_bits)); \ |
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| 392 | __asm__ __volatile__ \ |
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| 393 | ( \ |
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| 394 | "ldi r30, 1\n\t" \ |
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| 395 | "ldi r31, 0\n\t" \ |
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| 396 | "mov r0, %2\n\t" \ |
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| 397 | "sts %0, %1\n\t" \ |
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| 398 | "spm\n\t" \ |
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| 399 | : \ |
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| 400 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 401 | "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \ |
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| 402 | "r" (value) \ |
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| 403 | : "r0", "r30", "r31" \ |
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| 404 | ); \ |
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| 405 | })) |
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| 406 | |
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| 407 | #define __boot_lock_bits_set_alternate(lock_bits) \ |
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| 408 | (__extension__({ \ |
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| 409 | uint8_t value = (uint8_t)(~(lock_bits)); \ |
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| 410 | __asm__ __volatile__ \ |
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| 411 | ( \ |
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| 412 | "ldi r30, 1\n\t" \ |
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| 413 | "ldi r31, 0\n\t" \ |
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| 414 | "mov r0, %2\n\t" \ |
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| 415 | "sts %0, %1\n\t" \ |
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| 416 | "spm\n\t" \ |
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| 417 | ".word 0xffff\n\t" \ |
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| 418 | "nop\n\t" \ |
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| 419 | : \ |
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| 420 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 421 | "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \ |
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| 422 | "r" (value) \ |
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| 423 | : "r0", "r30", "r31" \ |
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| 424 | ); \ |
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| 425 | })) |
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| 426 | |
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| 427 | /* |
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| 428 | Reading lock and fuse bits: |
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| 429 | |
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| 430 | Similarly to writing the lock bits above, set BLBSET and SPMEN (or |
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| 431 | SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an |
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| 432 | LPM instruction. |
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| 433 | |
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| 434 | Z address: contents: |
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| 435 | 0x0000 low fuse bits |
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| 436 | 0x0001 lock bits |
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| 437 | 0x0002 extended fuse bits |
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| 438 | 0x0003 high fuse bits |
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| 439 | |
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| 440 | Sounds confusing, doesn't it? |
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| 441 | |
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| 442 | Unlike the macros in pgmspace.h, no need to care for non-enhanced |
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| 443 | cores here as these old cores do not provide SPM support anyway. |
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| 444 | */ |
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| 445 | |
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| 446 | /** \ingroup avr_boot |
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| 447 | \def GET_LOW_FUSE_BITS |
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| 448 | address to read the low fuse bits, using boot_lock_fuse_bits_get |
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| 449 | */ |
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| 450 | #define GET_LOW_FUSE_BITS (0x0000) |
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| 451 | /** \ingroup avr_boot |
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| 452 | \def GET_LOCK_BITS |
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| 453 | address to read the lock bits, using boot_lock_fuse_bits_get |
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| 454 | */ |
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| 455 | #define GET_LOCK_BITS (0x0001) |
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| 456 | /** \ingroup avr_boot |
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| 457 | \def GET_EXTENDED_FUSE_BITS |
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| 458 | address to read the extended fuse bits, using boot_lock_fuse_bits_get |
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| 459 | */ |
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| 460 | #define GET_EXTENDED_FUSE_BITS (0x0002) |
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| 461 | /** \ingroup avr_boot |
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| 462 | \def GET_HIGH_FUSE_BITS |
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| 463 | address to read the high fuse bits, using boot_lock_fuse_bits_get |
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| 464 | */ |
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| 465 | #define GET_HIGH_FUSE_BITS (0x0003) |
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| 466 | |
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| 467 | /** \ingroup avr_boot |
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| 468 | \def boot_lock_fuse_bits_get(address) |
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| 469 | |
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| 470 | Read the lock or fuse bits at \c address. |
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| 471 | |
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| 472 | Parameter \c address can be any of GET_LOW_FUSE_BITS, |
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| 473 | GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS. |
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| 474 | |
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| 475 | \note The lock and fuse bits returned are the physical values, |
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| 476 | i.e. a bit returned as 0 means the corresponding fuse or lock bit |
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| 477 | is programmed. |
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| 478 | */ |
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| 479 | #define boot_lock_fuse_bits_get(address) \ |
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| 480 | (__extension__({ \ |
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| 481 | uint8_t __result; \ |
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| 482 | __asm__ __volatile__ \ |
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| 483 | ( \ |
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| 484 | "ldi r30, %3\n\t" \ |
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| 485 | "ldi r31, 0\n\t" \ |
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| 486 | "sts %1, %2\n\t" \ |
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| 487 | "lpm %0, Z\n\t" \ |
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| 488 | : "=r" (__result) \ |
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| 489 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 490 | "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \ |
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| 491 | "M" (address) \ |
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| 492 | : "r0", "r30", "r31" \ |
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| 493 | ); \ |
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| 494 | __result; \ |
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| 495 | })) |
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| 496 | |
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| 497 | /** \ingroup avr_boot |
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| 498 | \def boot_signature_byte_get(address) |
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| 499 | |
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| 500 | Read the Signature Row byte at \c address. For some MCU types, |
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| 501 | this function can also retrieve the factory-stored oscillator |
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| 502 | calibration bytes. |
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| 503 | |
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| 504 | Parameter \c address can be 0-0x1f as documented by the datasheet. |
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| 505 | \note The values are MCU type dependent. |
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| 506 | */ |
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| 507 | |
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| 508 | #define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD)) |
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| 509 | |
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| 510 | #define boot_signature_byte_get(addr) \ |
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| 511 | (__extension__({ \ |
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| 512 | uint16_t __addr16 = (uint16_t)(addr); \ |
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| 513 | uint8_t __result; \ |
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| 514 | __asm__ __volatile__ \ |
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| 515 | ( \ |
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| 516 | "sts %1, %2\n\t" \ |
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| 517 | "lpm %0, Z" "\n\t" \ |
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| 518 | : "=r" (__result) \ |
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| 519 | : "i" (_SFR_MEM_ADDR(__SPM_REG)), \ |
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| 520 | "r" ((uint8_t) __BOOT_SIGROW_READ), \ |
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| 521 | "z" (__addr16) \ |
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| 522 | ); \ |
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| 523 | __result; \ |
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| 524 | })) |
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| 525 | |
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| 526 | /** \ingroup avr_boot |
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| 527 | \def boot_page_fill(address, data) |
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| 528 | |
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| 529 | Fill the bootloader temporary page buffer for flash |
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| 530 | address with data word. |
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| 531 | |
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| 532 | \note The address is a byte address. The data is a word. The AVR |
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| 533 | writes data to the buffer a word at a time, but addresses the buffer |
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| 534 | per byte! So, increment your address by 2 between calls, and send 2 |
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| 535 | data bytes in a word format! The LSB of the data is written to the lower |
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| 536 | address; the MSB of the data is written to the higher address.*/ |
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| 537 | |
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| 538 | /** \ingroup avr_boot |
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| 539 | \def boot_page_erase(address) |
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| 540 | |
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| 541 | Erase the flash page that contains address. |
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| 542 | |
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| 543 | \note address is a byte address in flash, not a word address. */ |
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| 544 | |
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| 545 | /** \ingroup avr_boot |
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| 546 | \def boot_page_write(address) |
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| 547 | |
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| 548 | Write the bootloader temporary page buffer |
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| 549 | to flash page that contains address. |
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| 550 | |
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| 551 | \note address is a byte address in flash, not a word address. */ |
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| 552 | |
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| 553 | /** \ingroup avr_boot |
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| 554 | \def boot_rww_enable() |
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| 555 | |
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| 556 | Enable the Read-While-Write memory section. */ |
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| 557 | |
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| 558 | /** \ingroup avr_boot |
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| 559 | \def boot_lock_bits_set(lock_bits) |
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| 560 | |
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| 561 | Set the bootloader lock bits. |
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| 562 | |
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| 563 | \param lock_bits A mask of which Boot Loader Lock Bits to set. |
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| 564 | |
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| 565 | \note In this context, a 'set bit' will be written to a zero value. |
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| 566 | Note also that only BLBxx bits can be programmed by this command. |
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| 567 | |
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| 568 | For example, to disallow the SPM instruction from writing to the Boot |
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| 569 | Loader memory section of flash, you would use this macro as such: |
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| 570 | |
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| 571 | \code |
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| 572 | boot_lock_bits_set (_BV (BLB11)); |
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| 573 | \endcode |
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| 574 | |
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| 575 | \note Like any lock bits, the Boot Loader Lock Bits, once set, |
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| 576 | cannot be cleared again except by a chip erase which will in turn |
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| 577 | also erase the boot loader itself. */ |
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| 578 | |
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| 579 | /* Normal versions of the macros use 16-bit addresses. |
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| 580 | Extended versions of the macros use 32-bit addresses. |
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| 581 | Alternate versions of the macros use 16-bit addresses and require special |
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| 582 | instruction sequences after LPM. |
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| 583 | |
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| 584 | FLASHEND is defined in the ioXXXX.h file. |
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| 585 | USHRT_MAX is defined in <limits.h>. */ |
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| 586 | |
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| 587 | #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \ |
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| 588 | || defined(__AVR_ATmega323__) |
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| 589 | |
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| 590 | /* Alternate: ATmega161/163/323 and 16 bit address */ |
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| 591 | #define boot_page_fill(address, data) __boot_page_fill_alternate(address, data) |
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| 592 | #define boot_page_erase(address) __boot_page_erase_alternate(address) |
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| 593 | #define boot_page_write(address) __boot_page_write_alternate(address) |
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| 594 | #define boot_rww_enable() __boot_rww_enable_alternate() |
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| 595 | #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits) |
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| 596 | |
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| 597 | #elif (FLASHEND > USHRT_MAX) |
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| 598 | |
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| 599 | /* Extended: >16 bit address */ |
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| 600 | #define boot_page_fill(address, data) __boot_page_fill_extended(address, data) |
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| 601 | #define boot_page_erase(address) __boot_page_erase_extended(address) |
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| 602 | #define boot_page_write(address) __boot_page_write_extended(address) |
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| 603 | #define boot_rww_enable() __boot_rww_enable() |
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| 604 | #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) |
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| 605 | |
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| 606 | #else |
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| 607 | |
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| 608 | /* Normal: 16 bit address */ |
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| 609 | #define boot_page_fill(address, data) __boot_page_fill_normal(address, data) |
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| 610 | #define boot_page_erase(address) __boot_page_erase_normal(address) |
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| 611 | #define boot_page_write(address) __boot_page_write_normal(address) |
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| 612 | #define boot_rww_enable() __boot_rww_enable() |
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| 613 | #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits) |
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| 614 | |
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| 615 | #endif |
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| 616 | |
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| 617 | /** \ingroup avr_boot |
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| 618 | |
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| 619 | Same as boot_page_fill() except it waits for eeprom and spm operations to |
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| 620 | complete before filling the page. */ |
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| 621 | |
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| 622 | #define boot_page_fill_safe(address, data) \ |
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| 623 | do { \ |
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| 624 | boot_spm_busy_wait(); \ |
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| 625 | eeprom_busy_wait(); \ |
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| 626 | boot_page_fill(address, data); \ |
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| 627 | } while (0) |
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| 628 | |
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| 629 | /** \ingroup avr_boot |
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| 630 | |
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| 631 | Same as boot_page_erase() except it waits for eeprom and spm operations to |
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| 632 | complete before erasing the page. */ |
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| 633 | |
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| 634 | #define boot_page_erase_safe(address) \ |
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| 635 | do { \ |
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| 636 | boot_spm_busy_wait(); \ |
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| 637 | eeprom_busy_wait(); \ |
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| 638 | boot_page_erase (address); \ |
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| 639 | } while (0) |
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| 640 | |
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| 641 | /** \ingroup avr_boot |
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| 642 | |
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| 643 | Same as boot_page_write() except it waits for eeprom and spm operations to |
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| 644 | complete before writing the page. */ |
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| 645 | |
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| 646 | #define boot_page_write_safe(address) \ |
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| 647 | do { \ |
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| 648 | boot_spm_busy_wait(); \ |
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| 649 | eeprom_busy_wait(); \ |
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| 650 | boot_page_write (address); \ |
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| 651 | } while (0) |
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| 652 | |
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| 653 | /** \ingroup avr_boot |
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| 654 | |
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| 655 | Same as boot_rww_enable() except waits for eeprom and spm operations to |
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| 656 | complete before enabling the RWW mameory. */ |
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| 657 | |
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| 658 | #define boot_rww_enable_safe() \ |
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| 659 | do { \ |
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| 660 | boot_spm_busy_wait(); \ |
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| 661 | eeprom_busy_wait(); \ |
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| 662 | boot_rww_enable(); \ |
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| 663 | } while (0) |
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| 664 | |
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| 665 | /** \ingroup avr_boot |
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| 666 | |
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| 667 | Same as boot_lock_bits_set() except waits for eeprom and spm operations to |
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| 668 | complete before setting the lock bits. */ |
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| 669 | |
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| 670 | #define boot_lock_bits_set_safe(lock_bits) \ |
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| 671 | do { \ |
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| 672 | boot_spm_busy_wait(); \ |
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| 673 | eeprom_busy_wait(); \ |
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| 674 | boot_lock_bits_set (lock_bits); \ |
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| 675 | } while (0) |
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| 676 | |
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| 677 | #endif /* _AVR_BOOT_H_ */ |
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