source: rtems/cpukit/score/cpu/arm/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 16.0 KB
Line 
1/**
2 * @file
3 *
4 * @brief ARM Architecture Support API
5 */
6
7/*
8 *  This include file contains information pertaining to the ARM
9 *  processor.
10 *
11 *  Copyright (c) 2009-2014 embedded brains GmbH.
12 *
13 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
14 *
15 *  Copyright (c) 2006 OAR Corporation
16 *
17 *  Copyright (c) 2002 Advent Networks, Inc.
18 *        Jay Monkman <jmonkman@adventnetworks.com>
19 *
20 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
21 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
22 *
23 *  The license and distribution terms for this file may be
24 *  found in the file LICENSE in this distribution or at
25 *  http://www.rtems.org/license/LICENSE.
26 *
27 */
28
29#ifndef _RTEMS_SCORE_CPU_H
30#define _RTEMS_SCORE_CPU_H
31
32#include <rtems/score/types.h>
33#include <rtems/score/arm.h>
34
35#if defined(ARM_MULTILIB_ARCH_V4)
36
37/**
38 * @defgroup ScoreCPUARM ARM Specific Support
39 *
40 * @ingroup ScoreCPU
41 *
42 * @brief ARM specific support.
43 */
44/**@{**/
45
46#if defined(__thumb__) && !defined(__thumb2__)
47  #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
48  #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
49  #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
50  #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
51  #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
52#else
53  #define ARM_SWITCH_REGISTERS
54  #define ARM_SWITCH_TO_ARM
55  #define ARM_SWITCH_BACK
56  #define ARM_SWITCH_OUTPUT
57  #define ARM_SWITCH_ADDITIONAL_OUTPUT
58#endif
59
60/**
61 * @name Program Status Register
62 */
63/**@{**/
64
65#define ARM_PSR_N (1 << 31)
66#define ARM_PSR_Z (1 << 30)
67#define ARM_PSR_C (1 << 29)
68#define ARM_PSR_V (1 << 28)
69#define ARM_PSR_Q (1 << 27)
70#define ARM_PSR_J (1 << 24)
71#define ARM_PSR_GE_SHIFT 16
72#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
73#define ARM_PSR_E (1 << 9)
74#define ARM_PSR_A (1 << 8)
75#define ARM_PSR_I (1 << 7)
76#define ARM_PSR_F (1 << 6)
77#define ARM_PSR_T (1 << 5)
78#define ARM_PSR_M_SHIFT 0
79#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
80#define ARM_PSR_M_USR 0x10
81#define ARM_PSR_M_FIQ 0x11
82#define ARM_PSR_M_IRQ 0x12
83#define ARM_PSR_M_SVC 0x13
84#define ARM_PSR_M_ABT 0x17
85#define ARM_PSR_M_UND 0x1b
86#define ARM_PSR_M_SYS 0x1f
87
88/** @} */
89
90/** @} */
91
92#endif /* defined(ARM_MULTILIB_ARCH_V4) */
93
94/**
95 * @addtogroup ScoreCPU
96 */
97/**@{**/
98
99/* If someone uses THUMB we assume she wants minimal code size */
100#ifdef __thumb__
101  #define CPU_INLINE_ENABLE_DISPATCH FALSE
102#else
103  #define CPU_INLINE_ENABLE_DISPATCH TRUE
104#endif
105
106#if defined(__ARMEL__)
107  #define CPU_BIG_ENDIAN FALSE
108  #define CPU_LITTLE_ENDIAN TRUE
109#elif defined(__ARMEB__)
110  #define CPU_BIG_ENDIAN TRUE
111  #define CPU_LITTLE_ENDIAN FALSE
112#else
113  #error "unknown endianness"
114#endif
115
116#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
117
118/*
119 *  The ARM uses the PIC interrupt model.
120 */
121#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
122
123#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
124
125#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
126
127#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
128
129#define CPU_ISR_PASSES_FRAME_POINTER 0
130
131#define CPU_HARDWARE_FP FALSE
132
133#define CPU_SOFTWARE_FP FALSE
134
135#define CPU_ALL_TASKS_ARE_FP FALSE
136
137#define CPU_IDLE_TASK_IS_FP FALSE
138
139#define CPU_USE_DEFERRED_FP_SWITCH FALSE
140
141#if defined(ARM_MULTILIB_HAS_WFI)
142  #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
143#else
144  #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
145#endif
146
147#define CPU_STACK_GROWS_UP FALSE
148
149/* XXX Why 32? */
150#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
151
152#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
153
154/*
155 * The interrupt mask disables only normal interrupts (IRQ).
156 *
157 * In order to support fast interrupts (FIQ) such that they can do something
158 * useful, we have to disable the operating system support for FIQs.  Having
159 * operating system support for them would require that FIQs are disabled
160 * during critical sections of the operating system and application.  At this
161 * level IRQs and FIQs would be equal.  It is true that FIQs could interrupt
162 * the non critical sections of IRQs, so here they would have a small
163 * advantage.  Without operating system support, the FIQs can execute at any
164 * time (of course not during the service of another FIQ). If someone needs
165 * operating system support for a FIQ, she can trigger a software interrupt and
166 * service the request in a two-step process.
167 */
168#define CPU_MODES_INTERRUPT_MASK 0x1
169
170#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
171
172#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
173
174#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
175
176#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
177
178/* AAPCS, section 4.1, Fundamental Data Types */
179#define CPU_SIZEOF_POINTER 4
180
181/* AAPCS, section 4.1, Fundamental Data Types */
182#define CPU_ALIGNMENT 8
183
184#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
185
186/* AAPCS, section 4.3.1, Aggregates */
187#define CPU_PARTITION_ALIGNMENT 4
188
189/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
190#define CPU_STACK_ALIGNMENT 8
191
192/*
193 * Bitfield handler macros.
194 *
195 * If we had a particularly fast function for finding the first
196 * bit set in a word, it would go here. Since we don't (*), we'll
197 * just use the universal macros.
198 *
199 * (*) On ARM V5 and later, there's a CLZ function which could be
200 *     used to implement much quicker than the default macro.
201 */
202
203#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
204
205#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
206
207#define CPU_PER_CPU_CONTROL_SIZE 0
208
209/** @} */
210
211#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
212  #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
213#endif
214
215#ifdef ARM_MULTILIB_VFP
216  #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
217#endif
218
219#ifdef RTEMS_SMP
220  #ifdef ARM_MULTILIB_VFP
221    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
222  #else
223    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
224  #endif
225#endif
226
227#define ARM_EXCEPTION_FRAME_SIZE 76
228
229#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
230
231#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
232
233#define ARM_VFP_CONTEXT_SIZE 264
234
235#ifndef ASM
236
237#ifdef __cplusplus
238extern "C" {
239#endif
240
241/**
242 * @addtogroup ScoreCPU
243 */
244/**@{**/
245
246typedef struct {
247  /* There is no CPU specific per-CPU state */
248} CPU_Per_CPU_control;
249
250typedef struct {
251#if defined(ARM_MULTILIB_ARCH_V4)
252  uint32_t register_cpsr;
253  uint32_t register_r4;
254  uint32_t register_r5;
255  uint32_t register_r6;
256  uint32_t register_r7;
257  uint32_t register_r8;
258  uint32_t register_r9;
259  uint32_t register_r10;
260  uint32_t register_fp;
261  uint32_t register_sp;
262  uint32_t register_lr;
263#elif defined(ARM_MULTILIB_ARCH_V7M)
264  uint32_t register_r4;
265  uint32_t register_r5;
266  uint32_t register_r6;
267  uint32_t register_r7;
268  uint32_t register_r8;
269  uint32_t register_r9;
270  uint32_t register_r10;
271  uint32_t register_r11;
272  void *register_lr;
273  void *register_sp;
274  uint32_t isr_nest_level;
275#else
276  void *register_sp;
277#endif
278#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
279  uint32_t thread_id;
280#endif
281#ifdef ARM_MULTILIB_VFP
282  uint64_t register_d8;
283  uint64_t register_d9;
284  uint64_t register_d10;
285  uint64_t register_d11;
286  uint64_t register_d12;
287  uint64_t register_d13;
288  uint64_t register_d14;
289  uint64_t register_d15;
290#endif
291#ifdef RTEMS_SMP
292  volatile bool is_executing;
293#endif
294} Context_Control;
295
296typedef struct {
297  /* Not supported */
298} Context_Control_fp;
299
300extern uint32_t arm_cpu_mode;
301
302static inline void _ARM_Data_memory_barrier( void )
303{
304#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
305  __asm__ volatile ( "dmb" : : : "memory" );
306#endif
307}
308
309static inline void _ARM_Data_synchronization_barrier( void )
310{
311#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
312  __asm__ volatile ( "dsb" : : : "memory" );
313#endif
314}
315
316static inline void _ARM_Instruction_synchronization_barrier( void )
317{
318#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
319  __asm__ volatile ( "isb" : : : "memory" );
320#endif
321}
322
323static inline uint32_t arm_interrupt_disable( void )
324{
325  uint32_t level;
326
327#if defined(ARM_MULTILIB_ARCH_V4)
328  uint32_t arm_switch_reg;
329
330  __asm__ volatile (
331    ARM_SWITCH_TO_ARM
332    "mrs %[level], cpsr\n"
333    "orr %[arm_switch_reg], %[level], #0x80\n"
334    "msr cpsr, %[arm_switch_reg]\n"
335    ARM_SWITCH_BACK
336    : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
337  );
338#elif defined(ARM_MULTILIB_ARCH_V7M)
339  uint32_t basepri = 0x80;
340
341  __asm__ volatile (
342    "mrs %[level], basepri\n"
343    "msr basepri_max, %[basepri]\n"
344    : [level] "=&r" (level)
345    : [basepri] "r" (basepri)
346  );
347#else
348  level = 0;
349#endif
350
351  return level;
352}
353
354static inline void arm_interrupt_enable( uint32_t level )
355{
356#if defined(ARM_MULTILIB_ARCH_V4)
357  ARM_SWITCH_REGISTERS;
358
359  __asm__ volatile (
360    ARM_SWITCH_TO_ARM
361    "msr cpsr, %[level]\n"
362    ARM_SWITCH_BACK
363    : ARM_SWITCH_OUTPUT
364    : [level] "r" (level)
365  );
366#elif defined(ARM_MULTILIB_ARCH_V7M)
367  __asm__ volatile (
368    "msr basepri, %[level]\n"
369    :
370    : [level] "r" (level)
371  );
372#endif
373}
374
375static inline void arm_interrupt_flash( uint32_t level )
376{
377#if defined(ARM_MULTILIB_ARCH_V4)
378  uint32_t arm_switch_reg;
379
380  __asm__ volatile (
381    ARM_SWITCH_TO_ARM
382    "mrs %[arm_switch_reg], cpsr\n"
383    "msr cpsr, %[level]\n"
384    "msr cpsr, %[arm_switch_reg]\n"
385    ARM_SWITCH_BACK
386    : [arm_switch_reg] "=&r" (arm_switch_reg)
387    : [level] "r" (level)
388  );
389#elif defined(ARM_MULTILIB_ARCH_V7M)
390  uint32_t basepri;
391
392  __asm__ volatile (
393    "mrs %[basepri], basepri\n"
394    "msr basepri, %[level]\n"
395    "msr basepri, %[basepri]\n"
396    : [basepri] "=&r" (basepri)
397    : [level] "r" (level)
398  );
399#endif
400}
401
402#define _CPU_ISR_Disable( _isr_cookie ) \
403  do { \
404    _isr_cookie = arm_interrupt_disable(); \
405  } while (0)
406
407#define _CPU_ISR_Enable( _isr_cookie )  \
408  arm_interrupt_enable( _isr_cookie )
409
410#define _CPU_ISR_Flash( _isr_cookie ) \
411  arm_interrupt_flash( _isr_cookie )
412
413void _CPU_ISR_Set_level( uint32_t level );
414
415uint32_t _CPU_ISR_Get_level( void );
416
417void _CPU_Context_Initialize(
418  Context_Control *the_context,
419  void *stack_area_begin,
420  size_t stack_area_size,
421  uint32_t new_level,
422  void (*entry_point)( void ),
423  bool is_fp,
424  void *tls_area
425);
426
427#define _CPU_Context_Get_SP( _context ) \
428  (_context)->register_sp
429
430#ifdef RTEMS_SMP
431  static inline bool _CPU_Context_Get_is_executing(
432    const Context_Control *context
433  )
434  {
435    return context->is_executing;
436  }
437
438  static inline void _CPU_Context_Set_is_executing(
439    Context_Control *context,
440    bool is_executing
441  )
442  {
443    context->is_executing = is_executing;
444  }
445#endif
446
447#define _CPU_Context_Restart_self( _the_context ) \
448   _CPU_Context_restore( (_the_context) );
449
450#define _CPU_Context_Fp_start( _base, _offset ) \
451   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
452
453#define _CPU_Context_Initialize_fp( _destination ) \
454  do { \
455    *(*(_destination)) = _CPU_Null_fp_context; \
456  } while (0)
457
458#define _CPU_Fatal_halt( _source, _err )    \
459   do {                                     \
460     uint32_t _level;                       \
461     uint32_t _error = _err;                \
462     _CPU_ISR_Disable( _level );            \
463     (void) _level;                         \
464     __asm__ volatile ("mov r0, %0\n"       \
465                   : "=r" (_error)          \
466                   : "0" (_error)           \
467                   : "r0" );                \
468     while (1);                             \
469   } while (0);
470
471/**
472 * @brief CPU initialization.
473 */
474void _CPU_Initialize( void );
475
476void _CPU_ISR_install_vector(
477  uint32_t vector,
478  proc_ptr new_handler,
479  proc_ptr *old_handler
480);
481
482/**
483 * @brief CPU switch context.
484 */
485void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
486
487void _CPU_Context_restore( Context_Control *new_context )
488  RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
489
490#if defined(ARM_MULTILIB_ARCH_V7M)
491  void _ARMV7M_Start_multitasking( Context_Control *heir );
492  #define _CPU_Start_multitasking _ARMV7M_Start_multitasking
493#endif
494
495void _CPU_Context_volatile_clobber( uintptr_t pattern );
496
497void _CPU_Context_validate( uintptr_t pattern );
498
499#ifdef RTEMS_SMP
500  uint32_t _CPU_SMP_Initialize( void );
501
502  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
503
504  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
505
506  static inline uint32_t _CPU_SMP_Get_current_processor( void )
507  {
508    uint32_t mpidr;
509
510    /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */
511    __asm__ volatile (
512      "mrc p15, 0, %[mpidr], c0, c0, 5\n"
513      : [mpidr] "=&r" (mpidr)
514    );
515
516    return mpidr & 0xffU;
517  }
518
519  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
520
521  static inline void _ARM_Send_event( void )
522  {
523    __asm__ volatile ( "sev" : : : "memory" );
524  }
525
526  static inline void _ARM_Wait_for_event( void )
527  {
528    __asm__ volatile ( "wfe" : : : "memory" );
529  }
530
531  static inline void _CPU_SMP_Processor_event_broadcast( void )
532  {
533    _ARM_Data_synchronization_barrier();
534    _ARM_Send_event();
535  }
536
537  static inline void _CPU_SMP_Processor_event_receive( void )
538  {
539    _ARM_Wait_for_event();
540    _ARM_Data_memory_barrier();
541  }
542#endif
543
544
545static inline uint32_t CPU_swap_u32( uint32_t value )
546{
547#if defined(__thumb2__)
548  __asm__ volatile (
549    "rev %0, %0"
550    : "=r" (value)
551    : "0" (value)
552  );
553  return value;
554#elif defined(__thumb__)
555  uint32_t byte1, byte2, byte3, byte4, swapped;
556
557  byte4 = (value >> 24) & 0xff;
558  byte3 = (value >> 16) & 0xff;
559  byte2 = (value >> 8)  & 0xff;
560  byte1 =  value & 0xff;
561
562  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
563  return swapped;
564#else
565  uint32_t tmp = value; /* make compiler warnings go away */
566  __asm__ volatile ("EOR %1, %0, %0, ROR #16\n"
567                "BIC %1, %1, #0xff0000\n"
568                "MOV %0, %0, ROR #8\n"
569                "EOR %0, %0, %1, LSR #8\n"
570                : "=r" (value), "=r" (tmp)
571                : "0" (value), "1" (tmp));
572  return value;
573#endif
574}
575
576static inline uint16_t CPU_swap_u16( uint16_t value )
577{
578#if defined(__thumb2__)
579  __asm__ volatile (
580    "rev16 %0, %0"
581    : "=r" (value)
582    : "0" (value)
583  );
584  return value;
585#else
586  return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
587#endif
588}
589
590typedef uint32_t CPU_Counter_ticks;
591
592CPU_Counter_ticks _CPU_Counter_read( void );
593
594CPU_Counter_ticks _CPU_Counter_difference(
595  CPU_Counter_ticks second,
596  CPU_Counter_ticks first
597);
598
599#if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE
600  void *_CPU_Thread_Idle_body( uintptr_t ignored );
601#endif
602
603/** @} */
604
605/**
606 * @addtogroup ScoreCPUARM
607 */
608/**@{**/
609
610#if defined(ARM_MULTILIB_ARCH_V4)
611
612typedef enum {
613  ARM_EXCEPTION_RESET = 0,
614  ARM_EXCEPTION_UNDEF = 1,
615  ARM_EXCEPTION_SWI = 2,
616  ARM_EXCEPTION_PREF_ABORT = 3,
617  ARM_EXCEPTION_DATA_ABORT = 4,
618  ARM_EXCEPTION_RESERVED = 5,
619  ARM_EXCEPTION_IRQ = 6,
620  ARM_EXCEPTION_FIQ = 7,
621  MAX_EXCEPTIONS = 8,
622  ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
623} Arm_symbolic_exception_name;
624
625#endif /* defined(ARM_MULTILIB_ARCH_V4) */
626
627typedef struct {
628  uint32_t register_fpexc;
629  uint32_t register_fpscr;
630  uint64_t register_d0;
631  uint64_t register_d1;
632  uint64_t register_d2;
633  uint64_t register_d3;
634  uint64_t register_d4;
635  uint64_t register_d5;
636  uint64_t register_d6;
637  uint64_t register_d7;
638  uint64_t register_d8;
639  uint64_t register_d9;
640  uint64_t register_d10;
641  uint64_t register_d11;
642  uint64_t register_d12;
643  uint64_t register_d13;
644  uint64_t register_d14;
645  uint64_t register_d15;
646  uint64_t register_d16;
647  uint64_t register_d17;
648  uint64_t register_d18;
649  uint64_t register_d19;
650  uint64_t register_d20;
651  uint64_t register_d21;
652  uint64_t register_d22;
653  uint64_t register_d23;
654  uint64_t register_d24;
655  uint64_t register_d25;
656  uint64_t register_d26;
657  uint64_t register_d27;
658  uint64_t register_d28;
659  uint64_t register_d29;
660  uint64_t register_d30;
661  uint64_t register_d31;
662} ARM_VFP_context;
663
664typedef struct {
665  uint32_t register_r0;
666  uint32_t register_r1;
667  uint32_t register_r2;
668  uint32_t register_r3;
669  uint32_t register_r4;
670  uint32_t register_r5;
671  uint32_t register_r6;
672  uint32_t register_r7;
673  uint32_t register_r8;
674  uint32_t register_r9;
675  uint32_t register_r10;
676  uint32_t register_r11;
677  uint32_t register_r12;
678  uint32_t register_sp;
679  void *register_lr;
680  void *register_pc;
681#if defined(ARM_MULTILIB_ARCH_V4)
682  uint32_t register_cpsr;
683  Arm_symbolic_exception_name vector;
684#elif defined(ARM_MULTILIB_ARCH_V7M)
685  uint32_t register_xpsr;
686  uint32_t vector;
687#endif
688  const ARM_VFP_context *vfp_context;
689} CPU_Exception_frame;
690
691typedef CPU_Exception_frame CPU_Interrupt_frame;
692
693void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
694
695void _ARM_Exception_default( CPU_Exception_frame *frame );
696
697/** @} */
698
699#ifdef __cplusplus
700}
701#endif
702
703#endif /* ASM */
704
705#endif /* _RTEMS_SCORE_CPU_H */
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