1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @ingroup ScoreCPU |
---|
5 | * |
---|
6 | * @brief ARM architecture support API. |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * This include file contains information pertaining to the ARM |
---|
11 | * processor. |
---|
12 | * |
---|
13 | * Copyright (c) 2009-2011 embedded brains GmbH. |
---|
14 | * |
---|
15 | * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> |
---|
16 | * |
---|
17 | * Copyright (c) 2006 OAR Corporation |
---|
18 | * |
---|
19 | * Copyright (c) 2002 Advent Networks, Inc. |
---|
20 | * Jay Monkman <jmonkman@adventnetworks.com> |
---|
21 | * |
---|
22 | * COPYRIGHT (c) 2000 Canon Research Centre France SA. |
---|
23 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
---|
24 | * |
---|
25 | * The license and distribution terms for this file may be |
---|
26 | * found in the file LICENSE in this distribution or at |
---|
27 | * http://www.rtems.com/license/LICENSE. |
---|
28 | * |
---|
29 | */ |
---|
30 | |
---|
31 | #ifndef _RTEMS_SCORE_CPU_H |
---|
32 | #define _RTEMS_SCORE_CPU_H |
---|
33 | |
---|
34 | #include <rtems/score/types.h> |
---|
35 | #include <rtems/score/arm.h> |
---|
36 | |
---|
37 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
38 | |
---|
39 | /** |
---|
40 | * @defgroup ScoreCPUARM ARM Specific Support |
---|
41 | * |
---|
42 | * @ingroup ScoreCPU |
---|
43 | * |
---|
44 | * @brief ARM specific support. |
---|
45 | * |
---|
46 | * @{ |
---|
47 | */ |
---|
48 | |
---|
49 | #ifdef __thumb__ |
---|
50 | #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg |
---|
51 | #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" |
---|
52 | #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" |
---|
53 | #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) |
---|
54 | #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT |
---|
55 | #else |
---|
56 | #define ARM_SWITCH_REGISTERS |
---|
57 | #define ARM_SWITCH_TO_ARM |
---|
58 | #define ARM_SWITCH_BACK |
---|
59 | #define ARM_SWITCH_OUTPUT |
---|
60 | #define ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
61 | #endif |
---|
62 | |
---|
63 | /** |
---|
64 | * @name Program Status Register |
---|
65 | * |
---|
66 | * @{ |
---|
67 | */ |
---|
68 | |
---|
69 | #define ARM_PSR_N (1 << 31) |
---|
70 | #define ARM_PSR_Z (1 << 30) |
---|
71 | #define ARM_PSR_C (1 << 29) |
---|
72 | #define ARM_PSR_V (1 << 28) |
---|
73 | #define ARM_PSR_Q (1 << 27) |
---|
74 | #define ARM_PSR_J (1 << 24) |
---|
75 | #define ARM_PSR_GE_SHIFT 16 |
---|
76 | #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) |
---|
77 | #define ARM_PSR_E (1 << 9) |
---|
78 | #define ARM_PSR_A (1 << 8) |
---|
79 | #define ARM_PSR_I (1 << 7) |
---|
80 | #define ARM_PSR_F (1 << 6) |
---|
81 | #define ARM_PSR_T (1 << 5) |
---|
82 | #define ARM_PSR_M_SHIFT 0 |
---|
83 | #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) |
---|
84 | #define ARM_PSR_M_USR 0x10 |
---|
85 | #define ARM_PSR_M_FIQ 0x11 |
---|
86 | #define ARM_PSR_M_IRQ 0x12 |
---|
87 | #define ARM_PSR_M_SVC 0x13 |
---|
88 | #define ARM_PSR_M_ABT 0x17 |
---|
89 | #define ARM_PSR_M_UND 0x1b |
---|
90 | #define ARM_PSR_M_SYS 0x1f |
---|
91 | |
---|
92 | /** @} */ |
---|
93 | |
---|
94 | /** @} */ |
---|
95 | |
---|
96 | #endif /* defined(ARM_MULTILIB_ARCH_V4) */ |
---|
97 | |
---|
98 | /** |
---|
99 | * @addtogroup ScoreCPU |
---|
100 | * |
---|
101 | * @{ |
---|
102 | */ |
---|
103 | |
---|
104 | /* If someone uses THUMB we assume she wants minimal code size */ |
---|
105 | #ifdef __thumb__ |
---|
106 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
---|
107 | #else |
---|
108 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
---|
109 | #endif |
---|
110 | |
---|
111 | #if defined(__ARMEL__) |
---|
112 | #define CPU_BIG_ENDIAN FALSE |
---|
113 | #define CPU_LITTLE_ENDIAN TRUE |
---|
114 | #elif defined(__ARMEB__) |
---|
115 | #define CPU_BIG_ENDIAN TRUE |
---|
116 | #define CPU_LITTLE_ENDIAN FALSE |
---|
117 | #else |
---|
118 | #error "unknown endianness" |
---|
119 | #endif |
---|
120 | |
---|
121 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
---|
122 | |
---|
123 | /* |
---|
124 | * The ARM uses the PIC interrupt model. |
---|
125 | */ |
---|
126 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
---|
127 | |
---|
128 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
---|
129 | |
---|
130 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
---|
131 | |
---|
132 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
---|
133 | |
---|
134 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
---|
135 | |
---|
136 | #if ( ARM_HAS_FPU == 1 ) |
---|
137 | #define CPU_HARDWARE_FP TRUE |
---|
138 | #else |
---|
139 | #define CPU_HARDWARE_FP FALSE |
---|
140 | #endif |
---|
141 | |
---|
142 | #define CPU_SOFTWARE_FP FALSE |
---|
143 | |
---|
144 | #define CPU_ALL_TASKS_ARE_FP FALSE |
---|
145 | |
---|
146 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
147 | |
---|
148 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
---|
149 | |
---|
150 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
---|
151 | |
---|
152 | #define CPU_STACK_GROWS_UP FALSE |
---|
153 | |
---|
154 | /* XXX Why 32? */ |
---|
155 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
---|
156 | |
---|
157 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
---|
158 | |
---|
159 | /* |
---|
160 | * The interrupt mask disables only normal interrupts (IRQ). |
---|
161 | * |
---|
162 | * In order to support fast interrupts (FIQ) such that they can do something |
---|
163 | * useful, we have to disable the operating system support for FIQs. Having |
---|
164 | * operating system support for them would require that FIQs are disabled |
---|
165 | * during critical sections of the operating system and application. At this |
---|
166 | * level IRQs and FIQs would be equal. It is true that FIQs could interrupt |
---|
167 | * the non critical sections of IRQs, so here they would have a small |
---|
168 | * advantage. Without operating system support, the FIQs can execute at any |
---|
169 | * time (of course not during the service of another FIQ). If someone needs |
---|
170 | * operating system support for a FIQ, she can trigger a software interrupt and |
---|
171 | * service the request in a two-step process. |
---|
172 | */ |
---|
173 | #define CPU_MODES_INTERRUPT_MASK 0x80 |
---|
174 | |
---|
175 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
176 | |
---|
177 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
178 | |
---|
179 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 |
---|
180 | |
---|
181 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
182 | |
---|
183 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
184 | |
---|
185 | #define CPU_STACK_MINIMUM_SIZE (1024 * 4) |
---|
186 | |
---|
187 | /* AAPCS, section 4.1, Fundamental Data Types */ |
---|
188 | #define CPU_ALIGNMENT 8 |
---|
189 | |
---|
190 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
191 | |
---|
192 | /* AAPCS, section 4.3.1, Aggregates */ |
---|
193 | #define CPU_PARTITION_ALIGNMENT 4 |
---|
194 | |
---|
195 | /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ |
---|
196 | #define CPU_STACK_ALIGNMENT 8 |
---|
197 | |
---|
198 | /* |
---|
199 | * Bitfield handler macros. |
---|
200 | * |
---|
201 | * If we had a particularly fast function for finding the first |
---|
202 | * bit set in a word, it would go here. Since we don't (*), we'll |
---|
203 | * just use the universal macros. |
---|
204 | * |
---|
205 | * (*) On ARM V5 and later, there's a CLZ function which could be |
---|
206 | * used to implement much quicker than the default macro. |
---|
207 | */ |
---|
208 | |
---|
209 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
210 | |
---|
211 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
212 | |
---|
213 | /** @} */ |
---|
214 | |
---|
215 | #ifndef ASM |
---|
216 | |
---|
217 | #ifdef __cplusplus |
---|
218 | extern "C" { |
---|
219 | #endif |
---|
220 | |
---|
221 | /** |
---|
222 | * @addtogroup ScoreCPU |
---|
223 | * |
---|
224 | * @{ |
---|
225 | */ |
---|
226 | |
---|
227 | typedef struct { |
---|
228 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
229 | uint32_t register_cpsr; |
---|
230 | uint32_t register_r4; |
---|
231 | uint32_t register_r5; |
---|
232 | uint32_t register_r6; |
---|
233 | uint32_t register_r7; |
---|
234 | uint32_t register_r8; |
---|
235 | uint32_t register_r9; |
---|
236 | uint32_t register_r10; |
---|
237 | uint32_t register_fp; |
---|
238 | uint32_t register_sp; |
---|
239 | uint32_t register_lr; |
---|
240 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
---|
241 | uint32_t register_r4; |
---|
242 | uint32_t register_r5; |
---|
243 | uint32_t register_r6; |
---|
244 | uint32_t register_r7; |
---|
245 | uint32_t register_r8; |
---|
246 | uint32_t register_r9; |
---|
247 | uint32_t register_r10; |
---|
248 | uint32_t register_r11; |
---|
249 | void *register_lr; |
---|
250 | void *register_sp; |
---|
251 | uint32_t isr_nest_level; |
---|
252 | #else |
---|
253 | void *register_sp; |
---|
254 | #endif |
---|
255 | } Context_Control; |
---|
256 | |
---|
257 | typedef struct { |
---|
258 | /* Not supported */ |
---|
259 | } Context_Control_fp; |
---|
260 | |
---|
261 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
---|
262 | |
---|
263 | extern uint32_t arm_cpu_mode; |
---|
264 | |
---|
265 | static inline uint32_t arm_interrupt_disable( void ) |
---|
266 | { |
---|
267 | uint32_t level; |
---|
268 | |
---|
269 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
270 | uint32_t arm_switch_reg; |
---|
271 | |
---|
272 | __asm__ volatile ( |
---|
273 | ARM_SWITCH_TO_ARM |
---|
274 | "mrs %[level], cpsr\n" |
---|
275 | "orr %[arm_switch_reg], %[level], #0x80\n" |
---|
276 | "msr cpsr, %[arm_switch_reg]\n" |
---|
277 | ARM_SWITCH_BACK |
---|
278 | : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) |
---|
279 | ); |
---|
280 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
---|
281 | uint32_t basepri = 0x80; |
---|
282 | |
---|
283 | __asm__ volatile ( |
---|
284 | "mrs %[level], basepri\n" |
---|
285 | "msr basepri_max, %[basepri]\n" |
---|
286 | : [level] "=&r" (level) |
---|
287 | : [basepri] "r" (basepri) |
---|
288 | ); |
---|
289 | #else |
---|
290 | level = 0; |
---|
291 | #endif |
---|
292 | |
---|
293 | return level; |
---|
294 | } |
---|
295 | |
---|
296 | static inline void arm_interrupt_enable( uint32_t level ) |
---|
297 | { |
---|
298 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
299 | ARM_SWITCH_REGISTERS; |
---|
300 | |
---|
301 | __asm__ volatile ( |
---|
302 | ARM_SWITCH_TO_ARM |
---|
303 | "msr cpsr, %[level]\n" |
---|
304 | ARM_SWITCH_BACK |
---|
305 | : ARM_SWITCH_OUTPUT |
---|
306 | : [level] "r" (level) |
---|
307 | ); |
---|
308 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
---|
309 | __asm__ volatile ( |
---|
310 | "msr basepri, %[level]\n" |
---|
311 | : |
---|
312 | : [level] "r" (level) |
---|
313 | ); |
---|
314 | #endif |
---|
315 | } |
---|
316 | |
---|
317 | static inline void arm_interrupt_flash( uint32_t level ) |
---|
318 | { |
---|
319 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
320 | uint32_t arm_switch_reg; |
---|
321 | |
---|
322 | __asm__ volatile ( |
---|
323 | ARM_SWITCH_TO_ARM |
---|
324 | "mrs %[arm_switch_reg], cpsr\n" |
---|
325 | "msr cpsr, %[level]\n" |
---|
326 | "msr cpsr, %[arm_switch_reg]\n" |
---|
327 | ARM_SWITCH_BACK |
---|
328 | : [arm_switch_reg] "=&r" (arm_switch_reg) |
---|
329 | : [level] "r" (level) |
---|
330 | ); |
---|
331 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
---|
332 | uint32_t basepri; |
---|
333 | |
---|
334 | __asm__ volatile ( |
---|
335 | "mrs %[basepri], basepri\n" |
---|
336 | "msr basepri, %[level]\n" |
---|
337 | "msr basepri, %[basepri]\n" |
---|
338 | : [basepri] "=&r" (basepri) |
---|
339 | : [level] "r" (level) |
---|
340 | ); |
---|
341 | #endif |
---|
342 | } |
---|
343 | |
---|
344 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
345 | do { \ |
---|
346 | _isr_cookie = arm_interrupt_disable(); \ |
---|
347 | } while (0) |
---|
348 | |
---|
349 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
350 | arm_interrupt_enable( _isr_cookie ) |
---|
351 | |
---|
352 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
353 | arm_interrupt_flash( _isr_cookie ) |
---|
354 | |
---|
355 | void _CPU_ISR_Set_level( uint32_t level ); |
---|
356 | |
---|
357 | uint32_t _CPU_ISR_Get_level( void ); |
---|
358 | |
---|
359 | void _CPU_Context_Initialize( |
---|
360 | Context_Control *the_context, |
---|
361 | void *stack_area_begin, |
---|
362 | size_t stack_area_size, |
---|
363 | uint32_t new_level, |
---|
364 | void (*entry_point)( void ), |
---|
365 | bool is_fp |
---|
366 | ); |
---|
367 | |
---|
368 | #define _CPU_Context_Get_SP( _context ) \ |
---|
369 | (_context)->register_sp |
---|
370 | |
---|
371 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
372 | _CPU_Context_restore( (_the_context) ); |
---|
373 | |
---|
374 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
375 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
376 | |
---|
377 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
378 | do { \ |
---|
379 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
380 | } while (0) |
---|
381 | |
---|
382 | #define _CPU_Fatal_halt( _err ) \ |
---|
383 | do { \ |
---|
384 | uint32_t _level; \ |
---|
385 | uint32_t _error = _err; \ |
---|
386 | _CPU_ISR_Disable( _level ); \ |
---|
387 | __asm__ volatile ("mov r0, %0\n" \ |
---|
388 | : "=r" (_error) \ |
---|
389 | : "0" (_error) \ |
---|
390 | : "r0" ); \ |
---|
391 | while (1); \ |
---|
392 | } while (0); |
---|
393 | |
---|
394 | void _CPU_Initialize( void ); |
---|
395 | |
---|
396 | void _CPU_ISR_install_vector( |
---|
397 | uint32_t vector, |
---|
398 | proc_ptr new_handler, |
---|
399 | proc_ptr *old_handler |
---|
400 | ); |
---|
401 | |
---|
402 | void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); |
---|
403 | |
---|
404 | void _CPU_Context_restore( Context_Control *new_context ) |
---|
405 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
406 | |
---|
407 | #if defined(ARM_MULTILIB_ARCH_V7M) |
---|
408 | void _ARMV7M_Start_multitasking( Context_Control *bsp, Context_Control *heir ); |
---|
409 | void _ARMV7M_Stop_multitasking( Context_Control *bsp ) |
---|
410 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
411 | #define _CPU_Start_multitasking _ARMV7M_Start_multitasking |
---|
412 | #define _CPU_Stop_multitasking _ARMV7M_Stop_multitasking |
---|
413 | #endif |
---|
414 | |
---|
415 | void _CPU_Context_save_fp( Context_Control_fp **fp_context_ptr ); |
---|
416 | |
---|
417 | void _CPU_Context_restore_fp( Context_Control_fp **fp_context_ptr ); |
---|
418 | |
---|
419 | static inline uint32_t CPU_swap_u32( uint32_t value ) |
---|
420 | { |
---|
421 | #if defined(__thumb2__) |
---|
422 | __asm__ volatile ( |
---|
423 | "rev %0, %0" |
---|
424 | : "=r" (value) |
---|
425 | : "0" (value) |
---|
426 | ); |
---|
427 | return value; |
---|
428 | #elif defined(__thumb__) |
---|
429 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
430 | |
---|
431 | byte4 = (value >> 24) & 0xff; |
---|
432 | byte3 = (value >> 16) & 0xff; |
---|
433 | byte2 = (value >> 8) & 0xff; |
---|
434 | byte1 = value & 0xff; |
---|
435 | |
---|
436 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
437 | return swapped; |
---|
438 | #else |
---|
439 | uint32_t tmp = value; /* make compiler warnings go away */ |
---|
440 | __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" |
---|
441 | "BIC %1, %1, #0xff0000\n" |
---|
442 | "MOV %0, %0, ROR #8\n" |
---|
443 | "EOR %0, %0, %1, LSR #8\n" |
---|
444 | : "=r" (value), "=r" (tmp) |
---|
445 | : "0" (value), "1" (tmp)); |
---|
446 | return value; |
---|
447 | #endif |
---|
448 | } |
---|
449 | |
---|
450 | static inline uint16_t CPU_swap_u16( uint16_t value ) |
---|
451 | { |
---|
452 | #if defined(__thumb2__) |
---|
453 | __asm__ volatile ( |
---|
454 | "rev16 %0, %0" |
---|
455 | : "=r" (value) |
---|
456 | : "0" (value) |
---|
457 | ); |
---|
458 | return value; |
---|
459 | #else |
---|
460 | return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); |
---|
461 | #endif |
---|
462 | } |
---|
463 | |
---|
464 | /** @} */ |
---|
465 | |
---|
466 | #if defined(ARM_MULTILIB_ARCH_V4) |
---|
467 | |
---|
468 | /** |
---|
469 | * @addtogroup ScoreCPUARM |
---|
470 | * |
---|
471 | * @{ |
---|
472 | */ |
---|
473 | |
---|
474 | typedef struct { |
---|
475 | uint32_t r0; |
---|
476 | uint32_t r1; |
---|
477 | uint32_t r2; |
---|
478 | uint32_t r3; |
---|
479 | uint32_t r4; |
---|
480 | uint32_t r5; |
---|
481 | uint32_t r6; |
---|
482 | uint32_t r7; |
---|
483 | uint32_t r8; |
---|
484 | uint32_t r9; |
---|
485 | uint32_t r10; |
---|
486 | uint32_t r11; |
---|
487 | uint32_t r12; |
---|
488 | uint32_t sp; |
---|
489 | uint32_t lr; |
---|
490 | uint32_t pc; |
---|
491 | uint32_t cpsr; |
---|
492 | } arm_cpu_context; |
---|
493 | |
---|
494 | typedef void arm_exc_abort_handler( arm_cpu_context *context ); |
---|
495 | |
---|
496 | typedef enum { |
---|
497 | ARM_EXCEPTION_RESET = 0, |
---|
498 | ARM_EXCEPTION_UNDEF = 1, |
---|
499 | ARM_EXCEPTION_SWI = 2, |
---|
500 | ARM_EXCEPTION_PREF_ABORT = 3, |
---|
501 | ARM_EXCEPTION_DATA_ABORT = 4, |
---|
502 | ARM_EXCEPTION_RESERVED = 5, |
---|
503 | ARM_EXCEPTION_IRQ = 6, |
---|
504 | ARM_EXCEPTION_FIQ = 7, |
---|
505 | MAX_EXCEPTIONS = 8 |
---|
506 | } Arm_symbolic_exception_name; |
---|
507 | |
---|
508 | static inline uint32_t arm_status_irq_enable( void ) |
---|
509 | { |
---|
510 | uint32_t arm_switch_reg; |
---|
511 | uint32_t psr; |
---|
512 | |
---|
513 | RTEMS_COMPILER_MEMORY_BARRIER(); |
---|
514 | |
---|
515 | __asm__ volatile ( |
---|
516 | ARM_SWITCH_TO_ARM |
---|
517 | "mrs %[psr], cpsr\n" |
---|
518 | "bic %[arm_switch_reg], %[psr], #0x80\n" |
---|
519 | "msr cpsr, %[arm_switch_reg]\n" |
---|
520 | ARM_SWITCH_BACK |
---|
521 | : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr) |
---|
522 | ); |
---|
523 | |
---|
524 | return psr; |
---|
525 | } |
---|
526 | |
---|
527 | static inline void arm_status_restore( uint32_t psr ) |
---|
528 | { |
---|
529 | ARM_SWITCH_REGISTERS; |
---|
530 | |
---|
531 | __asm__ volatile ( |
---|
532 | ARM_SWITCH_TO_ARM |
---|
533 | "msr cpsr, %[psr]\n" |
---|
534 | ARM_SWITCH_BACK |
---|
535 | : ARM_SWITCH_OUTPUT |
---|
536 | : [psr] "r" (psr) |
---|
537 | ); |
---|
538 | |
---|
539 | RTEMS_COMPILER_MEMORY_BARRIER(); |
---|
540 | } |
---|
541 | |
---|
542 | void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler ); |
---|
543 | |
---|
544 | void arm_exc_data_abort( void ); |
---|
545 | |
---|
546 | void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler ); |
---|
547 | |
---|
548 | void arm_exc_prefetch_abort( void ); |
---|
549 | |
---|
550 | void bsp_interrupt_dispatch( void ); |
---|
551 | |
---|
552 | void arm_exc_interrupt( void ); |
---|
553 | |
---|
554 | void arm_exc_undefined( void ); |
---|
555 | |
---|
556 | /** @} */ |
---|
557 | |
---|
558 | /* XXX This is out of date */ |
---|
559 | typedef struct { |
---|
560 | uint32_t register_r0; |
---|
561 | uint32_t register_r1; |
---|
562 | uint32_t register_r2; |
---|
563 | uint32_t register_r3; |
---|
564 | uint32_t register_ip; |
---|
565 | uint32_t register_lr; |
---|
566 | } CPU_Exception_frame; |
---|
567 | |
---|
568 | typedef CPU_Exception_frame CPU_Interrupt_frame; |
---|
569 | |
---|
570 | #else /* !defined(ARM_MULTILIB_ARCH_V4) */ |
---|
571 | |
---|
572 | typedef void CPU_Interrupt_frame; |
---|
573 | |
---|
574 | #endif /* !defined(ARM_MULTILIB_ARCH_V4) */ |
---|
575 | |
---|
576 | #ifdef __cplusplus |
---|
577 | } |
---|
578 | #endif |
---|
579 | |
---|
580 | #endif /* ASM */ |
---|
581 | |
---|
582 | #endif /* _RTEMS_SCORE_CPU_H */ |
---|