source: rtems/cpukit/score/cpu/arm/rtems/score/cpu.h @ c346f33d

4.104.114.84.95
Last change on this file since c346f33d was c346f33d, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 30, 2004 at 11:49:14 AM

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 29.8 KB
Line 
1/*
2 * $Id$
3 *
4 *  This include file contains information pertaining to the ARM
5 *  processor.
6 *
7 *  Copyright (c) 2002 Advent Networks, Inc.
8 *        Jay Monkman <jmonkman@adventnetworks.com>
9 *
10 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
11 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 *
17 */
18
19/* FIXME: finish commenting/cleaning up this file */
20#ifndef __CPU_h
21#define __CPU_h
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems/score/arm.h>            /* pick up machine definitions */
28#ifndef ASM
29#include <rtems/score/types.h>
30#endif
31
32/* conditional compilation parameters */
33
34/*
35 *  Should the calls to _Thread_Enable_dispatch be inlined?
36 *
37 *  If TRUE, then they are inlined.
38 *  If FALSE, then a subroutine call is made.
39 *
40 *  Basically this is an example of the classic trade-off of size
41 *  versus speed.  Inlining the call (TRUE) typically increases the
42 *  size of RTEMS while speeding up the enabling of dispatching.
43 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
44 *  only be 0 or 1 unless you are in an interrupt handler and that
45 *  interrupt handler invokes the executive.]  When not inlined
46 *  something calls _Thread_Enable_dispatch which in turns calls
47 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
48 *  one subroutine call is avoided entirely.]
49 */
50
51#define CPU_INLINE_ENABLE_DISPATCH       TRUE
52
53/*
54 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
55 *  be unrolled one time?  In unrolled each iteration of the loop examines
56 *  two "nodes" on the chain being searched.  Otherwise, only one node
57 *  is examined per iteration.
58 *
59 *  If TRUE, then the loops are unrolled.
60 *  If FALSE, then the loops are not unrolled.
61 *
62 *  The primary factor in making this decision is the cost of disabling
63 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
64 *  body of the loop.  On some CPUs, the flash is more expensive than
65 *  one iteration of the loop body.  In this case, it might be desirable
66 *  to unroll the loop.  It is important to note that on some CPUs, this
67 *  code is the longest interrupt disable period in RTEMS.  So it is
68 *  necessary to strike a balance when setting this parameter.
69 */
70
71#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
72
73/*
74 *  Does RTEMS manage a dedicated interrupt stack in software?
75 *
76 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
77 *  If FALSE, nothing is done.
78 *
79 *  If the CPU supports a dedicated interrupt stack in hardware,
80 *  then it is generally the responsibility of the BSP to allocate it
81 *  and set it up.
82 *
83 *  If the CPU does not support a dedicated interrupt stack, then
84 *  the porter has two options: (1) execute interrupts on the
85 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
86 *  interrupt stack.
87 *
88 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
89 *
90 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
91 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
92 *  possible that both are FALSE for a particular CPU.  Although it
93 *  is unclear what that would imply about the interrupt processing
94 *  procedure on that CPU.
95 */
96
97#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
98
99/*
100 *  Does this CPU have hardware support for a dedicated interrupt stack?
101 *
102 *  If TRUE, then it must be installed during initialization.
103 *  If FALSE, then no installation is performed.
104 *
105 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
106 *
107 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
108 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
109 *  possible that both are FALSE for a particular CPU.  Although it
110 *  is unclear what that would imply about the interrupt processing
111 *  procedure on that CPU.
112 */
113
114#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
115
116/*
117 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
118 *
119 *  If TRUE, then the memory is allocated during initialization.
120 *  If FALSE, then the memory is allocated during initialization.
121 *
122 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
123 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
124 */
125
126#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
127
128/*
129 *  Does the RTEMS invoke the user's ISR with the vector number and
130 *  a pointer to the saved interrupt frame (1) or just the vector
131 *  number (0)?
132 */
133
134#define CPU_ISR_PASSES_FRAME_POINTER 0
135
136/*
137 *  Does the CPU have hardware floating point?
138 *
139 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
140 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
141 *
142 *  If there is a FP coprocessor such as the i387 or mc68881, then
143 *  the answer is TRUE.
144 *
145 *  The macro name "ARM_HAS_FPU" should be made CPU specific.
146 *  It indicates whether or not this CPU model has FP support.  For
147 *  example, it would be possible to have an i386_nofp CPU model
148 *  which set this to false to indicate that you have an i386 without
149 *  an i387 and wish to leave floating point support out of RTEMS.
150 */
151
152#if ( ARM_HAS_FPU == 1 )
153#define CPU_HARDWARE_FP     TRUE
154#else
155#define CPU_HARDWARE_FP     FALSE
156#endif
157
158#define CPU_SOFTWARE_FP     FALSE
159
160/*
161 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
162 *
163 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
164 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
165 *
166 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
167 */
168
169#define CPU_ALL_TASKS_ARE_FP     FALSE
170
171/*
172 *  Should the IDLE task have a floating point context?
173 *
174 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
175 *  and it has a floating point context which is switched in and out.
176 *  If FALSE, then the IDLE task does not have a floating point context.
177 *
178 *  Setting this to TRUE negatively impacts the time required to preempt
179 *  the IDLE task from an interrupt because the floating point context
180 *  must be saved as part of the preemption.
181 */
182
183#define CPU_IDLE_TASK_IS_FP      FALSE
184
185/*
186 *  Should the saving of the floating point registers be deferred
187 *  until a context switch is made to another different floating point
188 *  task?
189 *
190 *  If TRUE, then the floating point context will not be stored until
191 *  necessary.  It will remain in the floating point registers and not
192 *  disturned until another floating point task is switched to.
193 *
194 *  If FALSE, then the floating point context is saved when a floating
195 *  point task is switched out and restored when the next floating point
196 *  task is restored.  The state of the floating point registers between
197 *  those two operations is not specified.
198 *
199 *  If the floating point context does NOT have to be saved as part of
200 *  interrupt dispatching, then it should be safe to set this to TRUE.
201 *
202 *  Setting this flag to TRUE results in using a different algorithm
203 *  for deciding when to save and restore the floating point context.
204 *  The deferred FP switch algorithm minimizes the number of times
205 *  the FP context is saved and restored.  The FP context is not saved
206 *  until a context switch is made to another, different FP task.
207 *  Thus in a system with only one FP task, the FP context will never
208 *  be saved or restored.
209 */
210
211#define CPU_USE_DEFERRED_FP_SWITCH   FALSE
212
213/*
214 *  Does this port provide a CPU dependent IDLE task implementation?
215 *
216 *  If TRUE, then the routine _CPU_Thread_Idle_body
217 *  must be provided and is the default IDLE thread body instead of
218 *  _CPU_Thread_Idle_body.
219 *
220 *  If FALSE, then use the generic IDLE thread body if the BSP does
221 *  not provide one.
222 *
223 *  This is intended to allow for supporting processors which have
224 *  a low power or idle mode.  When the IDLE thread is executed, then
225 *  the CPU can be powered down.
226 *
227 *  The order of precedence for selecting the IDLE thread body is:
228 *
229 *    1.  BSP provided
230 *    2.  CPU dependent (if provided)
231 *    3.  generic (if no BSP and no CPU dependent)
232 */
233
234#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
235
236/*
237 *  Does the stack grow up (toward higher addresses) or down
238 *  (toward lower addresses)?
239 *
240 *  If TRUE, then the grows upward.
241 *  If FALSE, then the grows toward smaller addresses.
242 */
243
244#define CPU_STACK_GROWS_UP               FALSE
245
246/*
247 *  The following is the variable attribute used to force alignment
248 *  of critical RTEMS structures.  On some processors it may make
249 *  sense to have these aligned on tighter boundaries than
250 *  the minimum requirements of the compiler in order to have as
251 *  much of the critical data area as possible in a cache line.
252 *
253 *  The placement of this macro in the declaration of the variables
254 *  is based on the syntactically requirements of the GNU C
255 *  "__attribute__" extension.  For example with GNU C, use
256 *  the following to force a structures to a 32 byte boundary.
257 *
258 *      __attribute__ ((aligned (32)))
259 *
260 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
261 *         To benefit from using this, the data must be heavily
262 *         used so it will stay in the cache and used frequently enough
263 *         in the executive to justify turning this on.
264 */
265
266#define CPU_STRUCTURE_ALIGNMENT  __attribute__ ((aligned (32)))
267
268/*
269 *  Define what is required to specify how the network to host conversion
270 *  routines are handled.
271 */
272
273#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
274
275#if defined(__ARMEL__)
276#define CPU_BIG_ENDIAN          FALSE
277#define CPU_LITTLE_ENDIAN       TRUE
278#elif define(__ARMEB__)
279#define CPU_BIG_ENDIAN          TRUE
280#define CPU_LITTLE_ENDIAN       FALSE
281#else
282#error "Unknown endianness"
283#endif
284                       
285/*
286 *  The following defines the number of bits actually used in the
287 *  interrupt field of the task mode.  How those bits map to the
288 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
289 */
290
291#define CPU_MODES_INTERRUPT_MASK   0x000000c0
292
293/*
294 *  Processor defined structures
295 *
296 *  Examples structures include the descriptor tables from the i386
297 *  and the processor control structure on the i960ca.
298 */
299
300/* may need to put some structures here.  */
301
302/*
303 * Contexts
304 *
305 *  Generally there are 2 types of context to save.
306 *     1. Interrupt registers to save
307 *     2. Task level registers to save
308 *
309 *  This means we have the following 3 context items:
310 *     1. task level context stuff::  Context_Control
311 *     2. floating point task stuff:: Context_Control_fp
312 *     3. special interrupt level context :: Context_Control_interrupt
313 *
314 *  On some processors, it is cost-effective to save only the callee
315 *  preserved registers during a task context switch.  This means
316 *  that the ISR code needs to save those registers which do not
317 *  persist across function calls.  It is not mandatory to make this
318 *  distinctions between the caller/callee saves registers for the
319 *  purpose of minimizing context saved during task switch and on interrupts.
320 *  If the cost of saving extra registers is minimal, simplicity is the
321 *  choice.  Save the same context on interrupt entry as for tasks in
322 *  this case.
323 *
324 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
325 *  care should be used in designing the context area.
326 *
327 *  On some CPUs with hardware floating point support, the Context_Control_fp
328 *  structure will not be used or it simply consist of an array of a
329 *  fixed number of bytes.   This is done when the floating point context
330 *  is dumped by a "FP save context" type instruction and the format
331 *  is not really defined by the CPU.  In this case, there is no need
332 *  to figure out the exact format -- only the size.  Of course, although
333 *  this is enough information for RTEMS, it is probably not enough for
334 *  a debugger such as gdb.  But that is another problem.
335 */
336typedef struct {
337    uint32_t   register_cpsr;
338    uint32_t   register_r4;
339    uint32_t   register_r5;
340    uint32_t   register_r6;
341    uint32_t   register_r7;
342    uint32_t   register_r8;
343    uint32_t   register_r9;
344    uint32_t   register_r10;
345    uint32_t   register_fp;
346    uint32_t   register_sp;
347    uint32_t   register_lr;
348    uint32_t   register_pc;
349} Context_Control;
350
351typedef struct {
352    double      some_float_register;
353} Context_Control_fp;
354
355typedef struct {
356    uint32_t   register_r0;
357    uint32_t   register_r1;
358    uint32_t   register_r2;
359    uint32_t   register_r3;
360    uint32_t   register_ip;
361    uint32_t   register_lr;
362} CPU_Exception_frame;
363
364typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
365extern cpuExcHandlerType _currentExcHandler;
366extern void rtems_exception_init_mngt();
367 
368/*
369 *  The following structure defines the set of information saved
370 *  on the current stack by RTEMS upon receipt of each interrupt
371 *  that will lead to re-enter the kernel to signal the thread.
372 */
373
374typedef CPU_Exception_frame CPU_Interrupt_frame;
375
376/*
377 *  The following table contains the information required to configure
378 *  the XXX processor specific parameters.
379 */
380
381typedef struct {
382  void       (*pretasking_hook)( void );
383  void       (*predriver_hook)( void );
384  void       (*postdriver_hook)( void );
385  void       (*idle_task)( void );
386  boolean      do_zero_of_workspace;
387  uint32_t     idle_task_stack_size;
388  uint32_t     interrupt_stack_size;
389  uint32_t     extra_mpci_receive_server_stack;
390  void *     (*stack_allocate_hook)( uint32_t   );
391  void       (*stack_free_hook)( void* );
392  /* end of fields required on all CPUs */
393
394}   rtems_cpu_table;
395
396/*
397 *  Macros to access required entires in the CPU Table are in
398 *  the file rtems/system.h.
399 */
400
401/*
402 *  Macros to access ARM specific additions to the CPU Table
403 *
404 *  none required
405 */
406
407/* There are no CPU specific additions to the CPU Table for this port. */
408
409/*
410 *  This variable is optional.  It is used on CPUs on which it is difficult
411 *  to generate an "uninitialized" FP context.  It is filled in by
412 *  _CPU_Initialize and copied into the task's FP context area during
413 *  _CPU_Context_Initialize.
414 */
415
416SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
417
418/*
419 *  The size of the floating point context area.  On some CPUs this
420 *  will not be a "sizeof" because the format of the floating point
421 *  area is not defined -- only the size is.  This is usually on
422 *  CPUs with a "floating point save context" instruction.
423 */
424
425#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
426
427/*
428 *  Amount of extra stack (above minimum stack size) required by
429 *  MPCI receive server thread.  Remember that in a multiprocessor
430 *  system this thread must exist and be able to process all directives.
431 */
432
433#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
434
435/*
436 *  This defines the number of entries in the ISR_Vector_table managed
437 *  by RTEMS.
438 */
439
440#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
441#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
442
443/*
444 *  This is defined if the port has a special way to report the ISR nesting
445 *  level.  Most ports maintain the variable _ISR_Nest_level.
446 */
447
448#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
449
450/*
451 *  Should be large enough to run all RTEMS tests.  This insures
452 *  that a "reasonable" small application should not have any problems.
453 */
454
455#define CPU_STACK_MINIMUM_SIZE          (1024*4)
456
457/*
458 *  CPU's worst alignment requirement for data types on a byte boundary.  This
459 *  alignment does not take into account the requirements for the stack.
460 */
461
462#define CPU_ALIGNMENT              4
463
464/*
465 *  This number corresponds to the byte alignment requirement for the
466 *  heap handler.  This alignment requirement may be stricter than that
467 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
468 *  common for the heap to follow the same alignment requirement as
469 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
470 *  then this should be set to CPU_ALIGNMENT.
471 *
472 *  NOTE:  This does not have to be a power of 2.  It does have to
473 *         be greater or equal to than CPU_ALIGNMENT.
474 */
475
476#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
477
478/*
479 *  This number corresponds to the byte alignment requirement for memory
480 *  buffers allocated by the partition manager.  This alignment requirement
481 *  may be stricter than that for the data types alignment specified by
482 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
483 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
484 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
485 *
486 *  NOTE:  This does not have to be a power of 2.  It does have to
487 *         be greater or equal to than CPU_ALIGNMENT.
488 */
489
490#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
491
492/*
493 *  This number corresponds to the byte alignment requirement for the
494 *  stack.  This alignment requirement may be stricter than that for the
495 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
496 *  is strict enough for the stack, then this should be set to 0.
497 *
498 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
499 */
500
501#define CPU_STACK_ALIGNMENT        4
502
503/* ISR handler macros */
504
505/*
506 *  Support routine to initialize the RTEMS vector table after it is allocated.
507 */
508
509#define _CPU_Initialize_vectors()
510
511/*
512 *  Disable all interrupts for an RTEMS critical section.  The previous
513 *  level is returned in _level.
514 */
515
516#define _CPU_ISR_Disable( _level )                \
517  {                                               \
518    int reg;                                       \
519    asm volatile ("MRS  %0, cpsr \n"               \
520                  "ORR  %1, %0, #0xc0 \n"          \
521                  "MSR  cpsr, %1 \n"               \
522                   : "=&r" (_level), "=&r" (reg)); \
523  }
524
525/*
526 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
527 *  This indicates the end of an RTEMS critical section.  The parameter
528 *  _level is not modified.
529 */
530
531#define _CPU_ISR_Enable( _level )               \
532  {                                             \
533    asm volatile ("MSR  cpsr, %0 \n"            \
534                  : : "r" (_level));            \
535  }
536
537/*
538 *  This temporarily restores the interrupt to _level before immediately
539 *  disabling them again.  This is used to divide long RTEMS critical
540 *  sections into two or more parts.  The parameter _level is not
541 * modified.
542 */
543
544#define _CPU_ISR_Flash( _level ) \
545  { \
546    int reg;                                    \
547    asm volatile ("MRS  %0, cpsr \n"            \
548                  "MSR  cpsr, %1 \n"            \
549                  "MSR  cpsr, %0 \n"            \
550                  : "=&r" (reg)                 \
551                  : "r" (_level));              \
552  }
553
554/*
555 *  Map interrupt level in task mode onto the hardware that the CPU
556 *  actually provides.  Currently, interrupt levels which do not
557 *  map onto the CPU in a generic fashion are undefined.  Someday,
558 *  it would be nice if these were "mapped" by the application
559 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
560 *  8 - 255 would be available for bsp/application specific meaning.
561 *  This could be used to manage a programmable interrupt controller
562 *  via the rtems_task_mode directive.
563 *
564 *  The get routine usually must be implemented as a subroutine.
565 */
566
567#define _CPU_ISR_Set_level( new_level )         \
568  {                                             \
569    int reg = 0; /* to avoid warning */         \
570    asm volatile ("MRS  %0, cpsr \n"            \
571                  "BIC  %0, %0, #0xc0 \n"       \
572                  "ORR  %0, %0, %2 \n"          \
573                  "MSR  cpsr_c, %0 \n"          \
574                  : "=r" (reg)                  \
575                  : "r" (reg), "0" (reg));      \
576  }
577
578
579uint32_t   _CPU_ISR_Get_level( void );
580
581/* end of ISR handler macros */
582
583/* Context handler macros */
584
585/*
586 *  Initialize the context to a state suitable for starting a
587 *  task after a context restore operation.  Generally, this
588 *  involves:
589 *
590 *     - setting a starting address
591 *     - preparing the stack
592 *     - preparing the stack and frame pointers
593 *     - setting the proper interrupt level in the context
594 *     - initializing the floating point context
595 *
596 *  This routine generally does not set any unnecessary register
597 *  in the context.  The state of the "general data" registers is
598 *  undefined at task start time.
599 *
600 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
601 *        point thread.  This is typically only used on CPUs where the
602 *        FPU may be easily disabled by software such as on the SPARC
603 *        where the PSR contains an enable FPU bit.
604 */
605
606void _CPU_Context_Initialize(
607  Context_Control  *the_context,
608  uint32_t         *stack_base,
609  uint32_t          size,
610  uint32_t          new_level,
611  void             *entry_point,
612  boolean           is_fp
613);
614
615/*
616 *  This routine is responsible for somehow restarting the currently
617 *  executing task.  If you are lucky, then all that is necessary
618 *  is restoring the context.  Otherwise, there will need to be
619 *  a special assembly routine which does something special in this
620 *  case.  Context_Restore should work most of the time.  It will
621 *  not work if restarting self conflicts with the stack frame
622 *  assumptions of restoring a context.
623 */
624
625#define _CPU_Context_Restart_self( _the_context ) \
626   _CPU_Context_restore( (_the_context) );
627
628/*
629 *  The purpose of this macro is to allow the initial pointer into
630 *  a floating point context area (used to save the floating point
631 *  context) to be at an arbitrary place in the floating point
632 *  context area.
633 *
634 *  This is necessary because some FP units are designed to have
635 *  their context saved as a stack which grows into lower addresses.
636 *  Other FP units can be saved by simply moving registers into offsets
637 *  from the base of the context area.  Finally some FP units provide
638 *  a "dump context" instruction which could fill in from high to low
639 *  or low to high based on the whim of the CPU designers.
640 */
641
642#define _CPU_Context_Fp_start( _base, _offset ) \
643   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
644
645/*
646 *  This routine initializes the FP context area passed to it to.
647 *  There are a few standard ways in which to initialize the
648 *  floating point context.  The code included for this macro assumes
649 *  that this is a CPU in which a "initial" FP context was saved into
650 *  _CPU_Null_fp_context and it simply copies it to the destination
651 *  context passed to it.
652 *
653 *  Other models include (1) not doing anything, and (2) putting
654 *  a "null FP status word" in the correct place in the FP context.
655 */
656
657#define _CPU_Context_Initialize_fp( _destination ) \
658  { \
659   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
660  }
661
662/* end of Context handler macros */
663
664/* Fatal Error manager macros */
665
666/*
667 *  This routine copies _error into a known place -- typically a stack
668 *  location or a register, optionally disables interrupts, and
669 *  halts/stops the CPU.
670 */
671
672#define _CPU_Fatal_halt( _error )           \
673   do {                                     \
674     int _level;                            \
675     _CPU_ISR_Disable( _level );            \
676     asm volatile ("mov r0, %0\n"           \
677                   : "=r" (_error)          \
678                   : "0" (_error)           \
679                   : "r0" );                \
680     while(1) ;                             \
681   } while(0);
682 
683
684/* end of Fatal Error manager macros */
685
686/* Bitfield handler macros */
687
688/*
689 *  This routine sets _output to the bit number of the first bit
690 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
691 *  This type may be either 16 or 32 bits wide although only the 16
692 *  least significant bits will be used.
693 *
694 *  There are a number of variables in using a "find first bit" type
695 *  instruction.
696 *
697 *    (1) What happens when run on a value of zero?
698 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
699 *    (3) The numbering may be zero or one based.
700 *    (4) The "find first bit" instruction may search from MSB or LSB.
701 *
702 *  RTEMS guarantees that (1) will never happen so it is not a concern.
703 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
704 *  _CPU_Priority_bits_index().  These three form a set of routines
705 *  which must logically operate together.  Bits in the _value are
706 *  set and cleared based on masks built by _CPU_Priority_mask().
707 *  The basic major and minor values calculated by _Priority_Major()
708 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
709 *  to properly range between the values returned by the "find first bit"
710 *  instruction.  This makes it possible for _Priority_Get_highest() to
711 *  calculate the major and directly index into the minor table.
712 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
713 *  is the first bit found.
714 *
715 *  This entire "find first bit" and mapping process depends heavily
716 *  on the manner in which a priority is broken into a major and minor
717 *  components with the major being the 4 MSB of a priority and minor
718 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
719 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
720 *  to the lowest priority.
721 *
722 *  If your CPU does not have a "find first bit" instruction, then
723 *  there are ways to make do without it.  Here are a handful of ways
724 *  to implement this in software:
725 *
726 *    - a series of 16 bit test instructions
727 *    - a "binary search using if's"
728 *    - _number = 0
729 *      if _value > 0x00ff
730 *        _value >>=8
731 *        _number = 8;
732 *
733 *      if _value > 0x0000f
734 *        _value >=8
735 *        _number += 4
736 *
737 *      _number += bit_set_table[ _value ]
738 *
739 *    where bit_set_table[ 16 ] has values which indicate the first
740 *      bit set
741 */
742#if (ARM_HAS_CLZ == 0)
743#  define CPU_USE_GENERIC_BITFIELD_CODE TRUE
744#  define CPU_USE_GENERIC_BITFIELD_DATA TRUE
745#else
746#  define CPU_USE_GENERIC_BITFIELD_CODE FALSE
747#  define CPU_USE_GENERIC_BITFIELD_DATA FALSE
748
749#  define _CPU_Bitfield_Find_first_bit( _value, _output ) \
750   { \
751     (_output) = 0;   /* do something to prevent warnings */ \
752   }
753
754/* end of Bitfield handler macros */
755
756/*
757 *  This routine builds the mask which corresponds to the bit fields
758 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
759 *  for that routine.
760 */
761
762
763#  define _CPU_Priority_Mask( _bit_number ) \
764   ( 1 << (_bit_number) )
765
766
767/*
768 *  This routine translates the bit numbers returned by
769 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
770 *  a major or minor component of a priority.  See the discussion
771 *  for that routine.
772 */
773
774
775#  define _CPU_Priority_bits_index( _priority ) \
776   (_priority)
777
778#  error "Implement CLZ version of priority bit functions for ARMv5"
779#endif
780
781/* end of Priority handler macros */
782
783/* functions */
784
785/*
786 *  _CPU_Initialize
787 *
788 *  This routine performs CPU dependent initialization.
789 */
790
791void _CPU_Initialize(
792  rtems_cpu_table  *cpu_table,
793  void      (*thread_dispatch)
794);
795
796typedef enum {
797  ARM_EXCEPTION_RESET      = 0,
798  ARM_EXCEPTION_UNDEF      = 1,
799  ARM_EXCEPTION_SWI        = 2,
800  ARM_EXCEPTION_PREF_ABORT = 3,
801  ARM_EXCEPTION_DATA_ABORT = 4,
802  ARM_EXCEPTION_RESERVED   = 5,
803  ARM_EXCEPTION_IRQ        = 6,
804  ARM_EXCEPTION_FIQ        = 7,
805  MAX_EXCEPTIONS           = 8
806} Arm_symbolic_exception_name;
807
808/*
809 *  _CPU_ISR_install_vector
810 *
811 *  This routine installs an interrupt vector.
812 */
813
814void _CPU_ISR_install_vector(
815  uint32_t    vector,
816  proc_ptr    new_handler,
817  proc_ptr   *old_handler
818);
819
820/*
821 *  _CPU_Install_interrupt_stack
822 *
823 *  This routine installs the hardware interrupt stack pointer.
824 *
825 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
826 *         is TRUE.
827 */
828
829void _CPU_Install_interrupt_stack( void );
830
831/*
832 *  _CPU_Context_switch
833 *
834 *  This routine switches from the run context to the heir context.
835 */
836
837void _CPU_Context_switch(
838  Context_Control  *run,
839  Context_Control  *heir
840);
841
842/*
843 *  _CPU_Context_restore
844 *
845 *  This routine is generally used only to restart self in an
846 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
847 *
848 *  NOTE: May be unnecessary to reload some registers.
849 */
850
851void _CPU_Context_restore(
852  Context_Control *new_context
853);
854
855#if (ARM_HAS_FPU == 1)
856/*
857 *  _CPU_Context_save_fp
858 *
859 *  This routine saves the floating point context passed to it.
860 */
861
862void _CPU_Context_save_fp(
863  void **fp_context_ptr
864);
865
866/*
867 *  _CPU_Context_restore_fp
868 *
869 *  This routine restores the floating point context passed to it.
870 */
871
872void _CPU_Context_restore_fp(
873  void **fp_context_ptr
874);
875#endif /* (ARM_HAS_FPU == 1) */
876
877/*  The following routine swaps the endian format of an unsigned int.
878 *  It must be static because it is referenced indirectly.
879 *
880 *  This version will work on any processor, but if there is a better
881 *  way for your CPU PLEASE use it.  The most common way to do this is to:
882 *
883 *     swap least significant two bytes with 16-bit rotate
884 *     swap upper and lower 16-bits
885 *     swap most significant two bytes with 16-bit rotate
886 *
887 *  Some CPUs have special instructions which swap a 32-bit quantity in
888 *  a single instruction (e.g. i486).  It is probably best to avoid
889 *  an "endian swapping control bit" in the CPU.  One good reason is
890 *  that interrupts would probably have to be disabled to insure that
891 *  an interrupt does not try to access the same "chunk" with the wrong
892 *  endian.  Another good reason is that on some CPUs, the endian bit
893 *  endianness for ALL fetches -- both code and data -- so the code
894 *  will be fetched incorrectly.
895 */
896 
897static inline unsigned int CPU_swap_u32(
898  unsigned int value
899)
900{
901    uint32_t   tmp = value; /* make compiler warnings go away */
902    asm volatile ("EOR   %1, %0, %0, ROR #16\n" 
903                  "BIC   %1, %1, #0xff0000\n"   
904                  "MOV   %0, %0, ROR #8\n"     
905                  "EOR   %0, %0, %1, LSR #8\n" 
906                  : "=r" (value), "=r" (tmp) 
907                  : "0" (value), "1" (tmp));
908
909    return value;
910}
911
912static inline uint16_t   CPU_swap_u16(uint16_t   value)
913{
914    uint16_t   lower;
915    uint16_t   upper;
916
917    value = value & (uint16_t  ) 0xffff;
918    lower = (value >> 8) ;
919    upper = (value << 8) ;
920
921    return (lower | upper);
922}
923
924#ifdef __cplusplus
925}
926#endif
927
928#endif
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