source: rtems/cpukit/score/cpu/arm/rtems/score/cpu.h @ 8b58477

4.104.114.84.95
Last change on this file since 8b58477 was 8b58477, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 5, 2002 at 7:20:40 PM

2002-08-05 Joel Sherrill <joel@…>

  • rtems/score/cpu.h, rtems/score/types.h: Updated to fix some typos.
  • Property mode set to 100644
File size: 30.2 KB
Line 
1/*
2 * $RCSfile$
3 *
4 *  This include file contains information pertaining to the ARM
5 *  processor.
6 *
7 *  Copyright (c) 2002 Advent Networks, Inc.
8 *        Jay Monkman <jmonkman@adventnetworks.com>
9 *
10 *  COPYRIGHT (c) 2000 Canon Research Centre France SA.
11 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.OARcorp.com/rtems/license.html.
16 *
17 */
18
19/* FIXME: finish commenting/cleaning up this file */
20#ifndef __CPU_h
21#define __CPU_h
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems/score/arm.h>            /* pick up machine definitions */
28#ifndef ASM
29#include <rtems/score/types.h>
30#endif
31
32/* conditional compilation parameters */
33
34/*
35 *  Should the calls to _Thread_Enable_dispatch be inlined?
36 *
37 *  If TRUE, then they are inlined.
38 *  If FALSE, then a subroutine call is made.
39 *
40 *  Basically this is an example of the classic trade-off of size
41 *  versus speed.  Inlining the call (TRUE) typically increases the
42 *  size of RTEMS while speeding up the enabling of dispatching.
43 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
44 *  only be 0 or 1 unless you are in an interrupt handler and that
45 *  interrupt handler invokes the executive.]  When not inlined
46 *  something calls _Thread_Enable_dispatch which in turns calls
47 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
48 *  one subroutine call is avoided entirely.]
49 */
50
51#define CPU_INLINE_ENABLE_DISPATCH       TRUE
52
53/*
54 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
55 *  be unrolled one time?  In unrolled each iteration of the loop examines
56 *  two "nodes" on the chain being searched.  Otherwise, only one node
57 *  is examined per iteration.
58 *
59 *  If TRUE, then the loops are unrolled.
60 *  If FALSE, then the loops are not unrolled.
61 *
62 *  The primary factor in making this decision is the cost of disabling
63 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
64 *  body of the loop.  On some CPUs, the flash is more expensive than
65 *  one iteration of the loop body.  In this case, it might be desirable
66 *  to unroll the loop.  It is important to note that on some CPUs, this
67 *  code is the longest interrupt disable period in RTEMS.  So it is
68 *  necessary to strike a balance when setting this parameter.
69 */
70
71#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
72
73/*
74 *  Does RTEMS manage a dedicated interrupt stack in software?
75 *
76 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
77 *  If FALSE, nothing is done.
78 *
79 *  If the CPU supports a dedicated interrupt stack in hardware,
80 *  then it is generally the responsibility of the BSP to allocate it
81 *  and set it up.
82 *
83 *  If the CPU does not support a dedicated interrupt stack, then
84 *  the porter has two options: (1) execute interrupts on the
85 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
86 *  interrupt stack.
87 *
88 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
89 *
90 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
91 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
92 *  possible that both are FALSE for a particular CPU.  Although it
93 *  is unclear what that would imply about the interrupt processing
94 *  procedure on that CPU.
95 */
96
97#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
98
99/*
100 *  Does this CPU have hardware support for a dedicated interrupt stack?
101 *
102 *  If TRUE, then it must be installed during initialization.
103 *  If FALSE, then no installation is performed.
104 *
105 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
106 *
107 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
108 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
109 *  possible that both are FALSE for a particular CPU.  Although it
110 *  is unclear what that would imply about the interrupt processing
111 *  procedure on that CPU.
112 */
113
114#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
115
116/*
117 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
118 *
119 *  If TRUE, then the memory is allocated during initialization.
120 *  If FALSE, then the memory is allocated during initialization.
121 *
122 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
123 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
124 */
125
126#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
127
128/*
129 *  Does the RTEMS invoke the user's ISR with the vector number and
130 *  a pointer to the saved interrupt frame (1) or just the vector
131 *  number (0)?
132 */
133
134#define CPU_ISR_PASSES_FRAME_POINTER 0
135
136/*
137 *  Does the CPU have hardware floating point?
138 *
139 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
140 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
141 *
142 *  If there is a FP coprocessor such as the i387 or mc68881, then
143 *  the answer is TRUE.
144 *
145 *  The macro name "ARM_HAS_FPU" should be made CPU specific.
146 *  It indicates whether or not this CPU model has FP support.  For
147 *  example, it would be possible to have an i386_nofp CPU model
148 *  which set this to false to indicate that you have an i386 without
149 *  an i387 and wish to leave floating point support out of RTEMS.
150 */
151
152#if ( ARM_HAS_FPU == 1 )
153#define CPU_HARDWARE_FP     TRUE
154#else
155#define CPU_HARDWARE_FP     FALSE
156#endif
157
158#define CPU_SOFTWARE_FP     FALSE
159
160/*
161 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
162 *
163 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
164 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
165 *
166 *  So far, the only CPU in which this option has been used is the
167 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
168 *  floating point registers to perform integer multiplies.  If
169 *  a function which you would not think utilize the FP unit DOES,
170 *  then one can not easily predict which tasks will use the FP hardware.
171 *  In this case, this option should be TRUE.
172 *
173 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
174 */
175
176#define CPU_ALL_TASKS_ARE_FP     FALSE
177
178/*
179 *  Should the IDLE task have a floating point context?
180 *
181 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
182 *  and it has a floating point context which is switched in and out.
183 *  If FALSE, then the IDLE task does not have a floating point context.
184 *
185 *  Setting this to TRUE negatively impacts the time required to preempt
186 *  the IDLE task from an interrupt because the floating point context
187 *  must be saved as part of the preemption.
188 */
189
190#define CPU_IDLE_TASK_IS_FP      FALSE
191
192/*
193 *  Should the saving of the floating point registers be deferred
194 *  until a context switch is made to another different floating point
195 *  task?
196 *
197 *  If TRUE, then the floating point context will not be stored until
198 *  necessary.  It will remain in the floating point registers and not
199 *  disturned until another floating point task is switched to.
200 *
201 *  If FALSE, then the floating point context is saved when a floating
202 *  point task is switched out and restored when the next floating point
203 *  task is restored.  The state of the floating point registers between
204 *  those two operations is not specified.
205 *
206 *  If the floating point context does NOT have to be saved as part of
207 *  interrupt dispatching, then it should be safe to set this to TRUE.
208 *
209 *  Setting this flag to TRUE results in using a different algorithm
210 *  for deciding when to save and restore the floating point context.
211 *  The deferred FP switch algorithm minimizes the number of times
212 *  the FP context is saved and restored.  The FP context is not saved
213 *  until a context switch is made to another, different FP task.
214 *  Thus in a system with only one FP task, the FP context will never
215 *  be saved or restored.
216 */
217
218#define CPU_USE_DEFERRED_FP_SWITCH   FALSE
219
220/*
221 *  Does this port provide a CPU dependent IDLE task implementation?
222 *
223 *  If TRUE, then the routine _CPU_Thread_Idle_body
224 *  must be provided and is the default IDLE thread body instead of
225 *  _CPU_Thread_Idle_body.
226 *
227 *  If FALSE, then use the generic IDLE thread body if the BSP does
228 *  not provide one.
229 *
230 *  This is intended to allow for supporting processors which have
231 *  a low power or idle mode.  When the IDLE thread is executed, then
232 *  the CPU can be powered down.
233 *
234 *  The order of precedence for selecting the IDLE thread body is:
235 *
236 *    1.  BSP provided
237 *    2.  CPU dependent (if provided)
238 *    3.  generic (if no BSP and no CPU dependent)
239 */
240
241#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
242
243/*
244 *  Does the stack grow up (toward higher addresses) or down
245 *  (toward lower addresses)?
246 *
247 *  If TRUE, then the grows upward.
248 *  If FALSE, then the grows toward smaller addresses.
249 */
250
251#define CPU_STACK_GROWS_UP               FALSE
252
253/*
254 *  The following is the variable attribute used to force alignment
255 *  of critical RTEMS structures.  On some processors it may make
256 *  sense to have these aligned on tighter boundaries than
257 *  the minimum requirements of the compiler in order to have as
258 *  much of the critical data area as possible in a cache line.
259 *
260 *  The placement of this macro in the declaration of the variables
261 *  is based on the syntactically requirements of the GNU C
262 *  "__attribute__" extension.  For example with GNU C, use
263 *  the following to force a structures to a 32 byte boundary.
264 *
265 *      __attribute__ ((aligned (32)))
266 *
267 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
268 *         To benefit from using this, the data must be heavily
269 *         used so it will stay in the cache and used frequently enough
270 *         in the executive to justify turning this on.
271 */
272
273#define CPU_STRUCTURE_ALIGNMENT  __attribute__ ((aligned (32)))
274
275/*
276 *  Define what is required to specify how the network to host conversion
277 *  routines are handled.
278 */
279
280#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
281#define CPU_BIG_ENDIAN                           FALSE
282#define CPU_LITTLE_ENDIAN                        TRUE
283
284/*
285 *  The following defines the number of bits actually used in the
286 *  interrupt field of the task mode.  How those bits map to the
287 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
288 */
289
290#define CPU_MODES_INTERRUPT_MASK   0x000000c0
291
292/*
293 *  Processor defined structures
294 *
295 *  Examples structures include the descriptor tables from the i386
296 *  and the processor control structure on the i960ca.
297 */
298
299/* may need to put some structures here.  */
300
301/*
302 * Contexts
303 *
304 *  Generally there are 2 types of context to save.
305 *     1. Interrupt registers to save
306 *     2. Task level registers to save
307 *
308 *  This means we have the following 3 context items:
309 *     1. task level context stuff::  Context_Control
310 *     2. floating point task stuff:: Context_Control_fp
311 *     3. special interrupt level context :: Context_Control_interrupt
312 *
313 *  On some processors, it is cost-effective to save only the callee
314 *  preserved registers during a task context switch.  This means
315 *  that the ISR code needs to save those registers which do not
316 *  persist across function calls.  It is not mandatory to make this
317 *  distinctions between the caller/callee saves registers for the
318 *  purpose of minimizing context saved during task switch and on interrupts.
319 *  If the cost of saving extra registers is minimal, simplicity is the
320 *  choice.  Save the same context on interrupt entry as for tasks in
321 *  this case.
322 *
323 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
324 *  care should be used in designing the context area.
325 *
326 *  On some CPUs with hardware floating point support, the Context_Control_fp
327 *  structure will not be used or it simply consist of an array of a
328 *  fixed number of bytes.   This is done when the floating point context
329 *  is dumped by a "FP save context" type instruction and the format
330 *  is not really defined by the CPU.  In this case, there is no need
331 *  to figure out the exact format -- only the size.  Of course, although
332 *  this is enough information for RTEMS, it is probably not enough for
333 *  a debugger such as gdb.  But that is another problem.
334 */
335typedef struct {
336    unsigned32 register_cpsr;
337    unsigned32 register_r4;
338    unsigned32 register_r5;
339    unsigned32 register_r6;
340    unsigned32 register_r7;
341    unsigned32 register_r8;
342    unsigned32 register_r9;
343    unsigned32 register_r10;
344    unsigned32 register_fp;
345    unsigned32 register_sp;
346    unsigned32 register_lr;
347    unsigned32 register_pc;
348} Context_Control;
349
350typedef struct {
351    double      some_float_register;
352} Context_Control_fp;
353
354typedef struct {
355    unsigned32 register_r0;
356    unsigned32 register_r1;
357    unsigned32 register_r2;
358    unsigned32 register_r3;
359    unsigned32 register_ip;
360    unsigned32 register_lr;
361} CPU_Exception_frame;
362
363typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
364extern cpuExcHandlerType _currentExcHandler;
365extern void rtems_exception_init_mngt();
366 
367/*
368 *  The following structure defines the set of information saved
369 *  on the current stack by RTEMS upon receipt of each interrupt
370 *  that will lead to re-enter the kernel to signal the thread.
371 */
372
373typedef CPU_Exception_frame CPU_Interrupt_frame;
374
375/*
376 *  The following table contains the information required to configure
377 *  the XXX processor specific parameters.
378 */
379
380typedef struct {
381  void       (*pretasking_hook)( void );
382  void       (*predriver_hook)( void );
383  void       (*postdriver_hook)( void );
384  void       (*idle_task)( void );
385  boolean      do_zero_of_workspace;
386  unsigned32   idle_task_stack_size;
387  unsigned32   interrupt_stack_size;
388  unsigned32   extra_mpci_receive_server_stack;
389  void *     (*stack_allocate_hook)( unsigned32 );
390  void       (*stack_free_hook)( void* );
391  /* end of fields required on all CPUs */
392
393}   rtems_cpu_table;
394
395/*
396 *  Macros to access required entires in the CPU Table are in
397 *  the file rtems/system.h.
398 */
399
400/*
401 *  Macros to access ARM specific additions to the CPU Table
402 *
403 *  none required
404 */
405
406/* There are no CPU specific additions to the CPU Table for this port. */
407
408/*
409 *  This variable is optional.  It is used on CPUs on which it is difficult
410 *  to generate an "uninitialized" FP context.  It is filled in by
411 *  _CPU_Initialize and copied into the task's FP context area during
412 *  _CPU_Context_Initialize.
413 */
414
415SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
416
417/*
418 *  The size of the floating point context area.  On some CPUs this
419 *  will not be a "sizeof" because the format of the floating point
420 *  area is not defined -- only the size is.  This is usually on
421 *  CPUs with a "floating point save context" instruction.
422 */
423
424#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
425
426/*
427 *  Amount of extra stack (above minimum stack size) required by
428 *  MPCI receive server thread.  Remember that in a multiprocessor
429 *  system this thread must exist and be able to process all directives.
430 */
431
432#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
433
434/*
435 *  This defines the number of entries in the ISR_Vector_table managed
436 *  by RTEMS.
437 */
438
439#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
440#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
441
442/*
443 *  This is defined if the port has a special way to report the ISR nesting
444 *  level.  Most ports maintain the variable _ISR_Nest_level.
445 */
446
447#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
448
449/*
450 *  Should be large enough to run all RTEMS tests.  This insures
451 *  that a "reasonable" small application should not have any problems.
452 */
453
454#define CPU_STACK_MINIMUM_SIZE          (1024*4)
455
456/*
457 *  CPU's worst alignment requirement for data types on a byte boundary.  This
458 *  alignment does not take into account the requirements for the stack.
459 */
460
461#define CPU_ALIGNMENT              4
462
463/*
464 *  This number corresponds to the byte alignment requirement for the
465 *  heap handler.  This alignment requirement may be stricter than that
466 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
467 *  common for the heap to follow the same alignment requirement as
468 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
469 *  then this should be set to CPU_ALIGNMENT.
470 *
471 *  NOTE:  This does not have to be a power of 2.  It does have to
472 *         be greater or equal to than CPU_ALIGNMENT.
473 */
474
475#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
476
477/*
478 *  This number corresponds to the byte alignment requirement for memory
479 *  buffers allocated by the partition manager.  This alignment requirement
480 *  may be stricter than that for the data types alignment specified by
481 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
482 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
483 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
484 *
485 *  NOTE:  This does not have to be a power of 2.  It does have to
486 *         be greater or equal to than CPU_ALIGNMENT.
487 */
488
489#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
490
491/*
492 *  This number corresponds to the byte alignment requirement for the
493 *  stack.  This alignment requirement may be stricter than that for the
494 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
495 *  is strict enough for the stack, then this should be set to 0.
496 *
497 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
498 */
499
500#define CPU_STACK_ALIGNMENT        4
501
502/* ISR handler macros */
503
504/*
505 *  Support routine to initialize the RTEMS vector table after it is allocated.
506 */
507
508#define _CPU_Initialize_vectors()
509
510/*
511 *  Disable all interrupts for an RTEMS critical section.  The previous
512 *  level is returned in _level.
513 */
514
515#define _CPU_ISR_Disable( _level )                \
516  {                                               \
517    int reg;                                       \
518    asm volatile ("MRS  %0, cpsr \n"               \
519                  "ORR  %1, %0, #0xc0 \n"          \
520                  "MSR  cpsr, %1 \n"               \
521                   : "=&r" (_level), "=&r" (reg)); \
522  }
523
524/*
525 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
526 *  This indicates the end of an RTEMS critical section.  The parameter
527 *  _level is not modified.
528 */
529
530#define _CPU_ISR_Enable( _level )               \
531  {                                             \
532    asm volatile ("MSR  cpsr, %0 \n"            \
533                  : : "r" (_level));            \
534  }
535
536/*
537 *  This temporarily restores the interrupt to _level before immediately
538 *  disabling them again.  This is used to divide long RTEMS critical
539 *  sections into two or more parts.  The parameter _level is not
540 * modified.
541 */
542
543#define _CPU_ISR_Flash( _level ) \
544  { \
545    int reg;                                    \
546    asm volatile ("MRS  %0, cpsr \n"            \
547                  "MSR  cpsr, %1 \n"            \
548                  "MSR  cpsr, %0 \n"            \
549                  : "=&r" (reg)                 \
550                  : "r" (_level));              \
551  }
552
553/*
554 *  Map interrupt level in task mode onto the hardware that the CPU
555 *  actually provides.  Currently, interrupt levels which do not
556 *  map onto the CPU in a generic fashion are undefined.  Someday,
557 *  it would be nice if these were "mapped" by the application
558 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
559 *  8 - 255 would be available for bsp/application specific meaning.
560 *  This could be used to manage a programmable interrupt controller
561 *  via the rtems_task_mode directive.
562 *
563 *  The get routine usually must be implemented as a subroutine.
564 */
565
566#define _CPU_ISR_Set_level( new_level )         \
567  {                                             \
568    int reg;                                    \
569    asm volatile ("MRS  %0, cpsr \n"            \
570                  "BIC  %0, %0, #0xc0 \n"       \
571                  "ORR  %0, %0, %2 \n"          \
572                  "MSR  cpsr_c, %0 \n"          \
573                  : "=r" (reg)                  \
574                  : "r" (reg), "0" (reg));      \
575  }
576
577
578unsigned32 _CPU_ISR_Get_level( void );
579
580/* end of ISR handler macros */
581
582/* Context handler macros */
583
584/*
585 *  Initialize the context to a state suitable for starting a
586 *  task after a context restore operation.  Generally, this
587 *  involves:
588 *
589 *     - setting a starting address
590 *     - preparing the stack
591 *     - preparing the stack and frame pointers
592 *     - setting the proper interrupt level in the context
593 *     - initializing the floating point context
594 *
595 *  This routine generally does not set any unnecessary register
596 *  in the context.  The state of the "general data" registers is
597 *  undefined at task start time.
598 *
599 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
600 *        point thread.  This is typically only used on CPUs where the
601 *        FPU may be easily disabled by software such as on the SPARC
602 *        where the PSR contains an enable FPU bit.
603 */
604
605void _CPU_Context_Initialize(
606  Context_Control  *the_context,
607  unsigned32       *stack_base,
608  unsigned32        size,
609  unsigned32        new_level,
610  void             *entry_point,
611  boolean           is_fp
612);
613
614/*
615 *  This routine is responsible for somehow restarting the currently
616 *  executing task.  If you are lucky, then all that is necessary
617 *  is restoring the context.  Otherwise, there will need to be
618 *  a special assembly routine which does something special in this
619 *  case.  Context_Restore should work most of the time.  It will
620 *  not work if restarting self conflicts with the stack frame
621 *  assumptions of restoring a context.
622 */
623
624#define _CPU_Context_Restart_self( _the_context ) \
625   _CPU_Context_restore( (_the_context) );
626
627/*
628 *  The purpose of this macro is to allow the initial pointer into
629 *  a floating point context area (used to save the floating point
630 *  context) to be at an arbitrary place in the floating point
631 *  context area.
632 *
633 *  This is necessary because some FP units are designed to have
634 *  their context saved as a stack which grows into lower addresses.
635 *  Other FP units can be saved by simply moving registers into offsets
636 *  from the base of the context area.  Finally some FP units provide
637 *  a "dump context" instruction which could fill in from high to low
638 *  or low to high based on the whim of the CPU designers.
639 */
640
641#define _CPU_Context_Fp_start( _base, _offset ) \
642   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
643
644/*
645 *  This routine initializes the FP context area passed to it to.
646 *  There are a few standard ways in which to initialize the
647 *  floating point context.  The code included for this macro assumes
648 *  that this is a CPU in which a "initial" FP context was saved into
649 *  _CPU_Null_fp_context and it simply copies it to the destination
650 *  context passed to it.
651 *
652 *  Other models include (1) not doing anything, and (2) putting
653 *  a "null FP status word" in the correct place in the FP context.
654 */
655
656#define _CPU_Context_Initialize_fp( _destination ) \
657  { \
658   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
659  }
660
661/* end of Context handler macros */
662
663/* Fatal Error manager macros */
664
665/*
666 *  This routine copies _error into a known place -- typically a stack
667 *  location or a register, optionally disables interrupts, and
668 *  halts/stops the CPU.
669 */
670
671#define _CPU_Fatal_halt( _error )           \
672   do {                                     \
673     int _level;                            \
674     _CPU_ISR_Disable( _level );            \
675     asm volatile ("mov r0, %0\n"           \
676                   : "=r" (_error)          \
677                   : "0" (_error)           \
678                   : "r0" );                \
679     while(1) ;                             \
680   } while(0);
681 
682
683/* end of Fatal Error manager macros */
684
685/* Bitfield handler macros */
686
687/*
688 *  This routine sets _output to the bit number of the first bit
689 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
690 *  This type may be either 16 or 32 bits wide although only the 16
691 *  least significant bits will be used.
692 *
693 *  There are a number of variables in using a "find first bit" type
694 *  instruction.
695 *
696 *    (1) What happens when run on a value of zero?
697 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
698 *    (3) The numbering may be zero or one based.
699 *    (4) The "find first bit" instruction may search from MSB or LSB.
700 *
701 *  RTEMS guarantees that (1) will never happen so it is not a concern.
702 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
703 *  _CPU_Priority_bits_index().  These three form a set of routines
704 *  which must logically operate together.  Bits in the _value are
705 *  set and cleared based on masks built by _CPU_Priority_mask().
706 *  The basic major and minor values calculated by _Priority_Major()
707 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
708 *  to properly range between the values returned by the "find first bit"
709 *  instruction.  This makes it possible for _Priority_Get_highest() to
710 *  calculate the major and directly index into the minor table.
711 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
712 *  is the first bit found.
713 *
714 *  This entire "find first bit" and mapping process depends heavily
715 *  on the manner in which a priority is broken into a major and minor
716 *  components with the major being the 4 MSB of a priority and minor
717 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
718 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
719 *  to the lowest priority.
720 *
721 *  If your CPU does not have a "find first bit" instruction, then
722 *  there are ways to make do without it.  Here are a handful of ways
723 *  to implement this in software:
724 *
725 *    - a series of 16 bit test instructions
726 *    - a "binary search using if's"
727 *    - _number = 0
728 *      if _value > 0x00ff
729 *        _value >>=8
730 *        _number = 8;
731 *
732 *      if _value > 0x0000f
733 *        _value >=8
734 *        _number += 4
735 *
736 *      _number += bit_set_table[ _value ]
737 *
738 *    where bit_set_table[ 16 ] has values which indicate the first
739 *      bit set
740 */
741#if (ARM_HAS_CLZ == 0)
742#  define CPU_USE_GENERIC_BITFIELD_CODE TRUE
743#  define CPU_USE_GENERIC_BITFIELD_DATA TRUE
744#else
745#  define CPU_USE_GENERIC_BITFIELD_CODE FALSE
746#  define CPU_USE_GENERIC_BITFIELD_DATA FALSE
747
748#  define _CPU_Bitfield_Find_first_bit( _value, _output ) \
749   { \
750     (_output) = 0;   /* do something to prevent warnings */ \
751   }
752
753/* end of Bitfield handler macros */
754
755/*
756 *  This routine builds the mask which corresponds to the bit fields
757 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
758 *  for that routine.
759 */
760
761
762#  define _CPU_Priority_Mask( _bit_number ) \
763   ( 1 << (_bit_number) )
764
765
766/*
767 *  This routine translates the bit numbers returned by
768 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
769 *  a major or minor component of a priority.  See the discussion
770 *  for that routine.
771 */
772
773
774#  define _CPU_Priority_bits_index( _priority ) \
775   (_priority)
776
777#  error "Implement CLZ verson of priority bit functions for ARMv5"
778#endif
779
780/* end of Priority handler macros */
781
782/* functions */
783
784/*
785 *  _CPU_Initialize
786 *
787 *  This routine performs CPU dependent initialization.
788 */
789
790void _CPU_Initialize(
791  rtems_cpu_table  *cpu_table,
792  void      (*thread_dispatch)
793);
794
795typedef enum {
796  ARM_EXCEPTION_RESET      = 0,
797  ARM_EXCEPTION_UNDEF      = 1,
798  ARM_EXCEPTION_SWI        = 2,
799  ARM_EXCEPTION_PREF_ABORT = 3,
800  ARM_EXCEPTION_DATA_ABORT = 4,
801  ARM_EXCEPTION_RESERVED   = 5,
802  ARM_EXCEPTION_IRQ        = 6,
803  ARM_EXCEPTION_FIQ        = 7,
804  MAX_EXCEPTIONS           = 8
805} Arm_symbolic_exception_name;
806
807/*
808 *  _CPU_ISR_install_vector
809 *
810 *  This routine installs an interrupt vector.
811 */
812
813void _CPU_ISR_install_vector(
814  unsigned32  vector,
815  proc_ptr    new_handler,
816  proc_ptr   *old_handler
817);
818
819/*
820 *  _CPU_Install_interrupt_stack
821 *
822 *  This routine installs the hardware interrupt stack pointer.
823 *
824 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
825 *         is TRUE.
826 */
827
828void _CPU_Install_interrupt_stack( void );
829
830/*
831 *  _CPU_Context_switch
832 *
833 *  This routine switches from the run context to the heir context.
834 */
835
836void _CPU_Context_switch(
837  Context_Control  *run,
838  Context_Control  *heir
839);
840
841/*
842 *  _CPU_Context_restore
843 *
844 *  This routine is generally used only to restart self in an
845 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
846 *
847 *  NOTE: May be unnecessary to reload some registers.
848 */
849
850void _CPU_Context_restore(
851  Context_Control *new_context
852);
853
854#if (ARM_HAS_FPU == 1)
855/*
856 *  _CPU_Context_save_fp
857 *
858 *  This routine saves the floating point context passed to it.
859 */
860
861void _CPU_Context_save_fp(
862  void **fp_context_ptr
863);
864
865/*
866 *  _CPU_Context_restore_fp
867 *
868 *  This routine restores the floating point context passed to it.
869 */
870
871void _CPU_Context_restore_fp(
872  void **fp_context_ptr
873);
874#endif /* (ARM_HAS_FPU == 1) */
875
876/*  The following routine swaps the endian format of an unsigned int.
877 *  It must be static because it is referenced indirectly.
878 *
879 *  This version will work on any processor, but if there is a better
880 *  way for your CPU PLEASE use it.  The most common way to do this is to:
881 *
882 *     swap least significant two bytes with 16-bit rotate
883 *     swap upper and lower 16-bits
884 *     swap most significant two bytes with 16-bit rotate
885 *
886 *  Some CPUs have special instructions which swap a 32-bit quantity in
887 *  a single instruction (e.g. i486).  It is probably best to avoid
888 *  an "endian swapping control bit" in the CPU.  One good reason is
889 *  that interrupts would probably have to be disabled to insure that
890 *  an interrupt does not try to access the same "chunk" with the wrong
891 *  endian.  Another good reason is that on some CPUs, the endian bit
892 *  endianness for ALL fetches -- both code and data -- so the code
893 *  will be fetched incorrectly.
894 */
895 
896static inline unsigned int CPU_swap_u32(
897  unsigned int value
898)
899{
900    unsigned32 tmp;
901    asm volatile ("EOR   %1, %0, %0, ROR #16\n"  \
902                  "BIC   %1, %1, #0xff0000\n"    \
903                  "MOV   %0, %0, ROR #8\n"       \
904                  "EOR   %0, %0, %1, LSR #8\n"   \
905                  : "=&r" (value), "=&r" (tmp)     \
906                  : "0" (value));
907
908    return value;
909}
910
911static inline unsigned16 CPU_swap_u16(unsigned16 value)
912{
913    unsigned32 tmp = value;   /* make compiler warnings go away */
914    asm volatile ("MOV   %1, %0, LSR #8\n"       \
915                  "BIC   %0, %0, #0xff00\n"      \
916                  "MOV   %0, %0, LSL #8\n"       \
917                  "ORR   %0, %0, %1\n"           \
918                  : "=&r" (value), "=&r" (tmp)     \
919                  : "0" (value));
920    return value;
921}
922
923#ifdef __cplusplus
924}
925#endif
926
927#endif
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